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jeremybenn |
;; Octeon pipeline description.
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;; Copyright (C) 2008
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;; Free Software Foundation, Inc.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Copyright (C) 2004, 2005, 2006 Cavium Networks.
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;; Octeon is a dual-issue processor that can issue all instructions on
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;; pipe0 and a subset on pipe1.
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(define_automaton "octeon_main, octeon_mult")
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(define_cpu_unit "octeon_pipe0" "octeon_main")
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(define_cpu_unit "octeon_pipe1" "octeon_main")
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(define_cpu_unit "octeon_mult" "octeon_mult")
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(define_insn_reservation "octeon_arith" 1
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(and (eq_attr "cpu" "octeon,octeon2")
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(eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
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"octeon_pipe0 | octeon_pipe1")
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(define_insn_reservation "octeon_condmove" 2
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(and (eq_attr "cpu" "octeon,octeon2")
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(eq_attr "type" "condmove"))
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"octeon_pipe0 | octeon_pipe1")
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(define_insn_reservation "octeon_load_o1" 2
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "load,prefetch,mtc,mfc"))
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"octeon_pipe0")
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(define_insn_reservation "octeon_load_o2" 3
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "load,prefetch"))
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"octeon_pipe0")
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;; ??? memory-related cop0 reads are pipe0 with 3-cycle latency.
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;; Front-end-related ones are 1-cycle on pipe1. Assume front-end for now.
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(define_insn_reservation "octeon_cop_o2" 1
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "mtc,mfc"))
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"octeon_pipe1")
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(define_insn_reservation "octeon_store" 1
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(and (eq_attr "cpu" "octeon,octeon2")
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(eq_attr "type" "store"))
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"octeon_pipe0")
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(define_insn_reservation "octeon_brj_o1" 1
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "branch,jump,call,trap"))
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"octeon_pipe0")
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(define_insn_reservation "octeon_brj_o2" 2
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "branch,jump,call,trap"))
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"octeon_pipe1")
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(define_insn_reservation "octeon_imul3_o1" 5
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "imul3,pop,clz"))
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"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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(define_insn_reservation "octeon_imul3_o2" 6
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "imul3,pop,clz"))
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"octeon_pipe1 + octeon_mult")
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(define_insn_reservation "octeon_imul_o1" 2
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "imul,mthilo"))
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"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
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(define_insn_reservation "octeon_imul_o2" 1
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "imul,mthilo"))
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"octeon_pipe1 + octeon_mult")
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(define_insn_reservation "octeon_mfhilo_o1" 5
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "mfhilo"))
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"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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(define_insn_reservation "octeon_mfhilo_o2" 6
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "mfhilo"))
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"octeon_pipe1 + octeon_mult")
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(define_insn_reservation "octeon_imadd_o1" 4
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "imadd"))
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"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
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(define_insn_reservation "octeon_imadd_o2" 1
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "type" "imadd"))
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"octeon_pipe1 + octeon_mult")
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(define_insn_reservation "octeon_idiv_o1" 72
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(and (eq_attr "cpu" "octeon")
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(eq_attr "type" "idiv"))
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"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
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(define_insn_reservation "octeon_idiv_o2_si" 18
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "mode" "SI")
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(eq_attr "type" "idiv"))
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"octeon_pipe1 + octeon_mult, octeon_mult*17")
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(define_insn_reservation "octeon_idiv_o2_di" 35
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(and (eq_attr "cpu" "octeon2")
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(eq_attr "mode" "DI")
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(eq_attr "type" "idiv"))
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"octeon_pipe1 + octeon_mult, octeon_mult*34")
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;; Assume both pipes are needed for unknown and multiple-instruction
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;; patterns.
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(define_insn_reservation "octeon_unknown" 1
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(and (eq_attr "cpu" "octeon,octeon2")
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(eq_attr "type" "unknown,multi"))
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"octeon_pipe0 + octeon_pipe1")
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