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Line No. Rev Author Line
1 709 jeremybenn 
;;  Machine Description for MIPS based processor synchronization
2 
;;  instructions.
3 
;;  Copyright (C) 2007, 2008, 2009, 2010
4 
;;  Free Software Foundation, Inc.
5 
 
6 
;; This file is part of GCC.
7 
 
8 
;; GCC is free software; you can redistribute it and/or modify
9 
;; it under the terms of the GNU General Public License as published by
10 
;; the Free Software Foundation; either version 3, or (at your option)
11 
;; any later version.
12 
 
13 
;; GCC is distributed in the hope that it will be useful,
14 
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 
;; GNU General Public License for more details.
17 
 
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
(define_c_enum "unspec" [
23 
  UNSPEC_COMPARE_AND_SWAP
24 
  UNSPEC_COMPARE_AND_SWAP_12
25 
  UNSPEC_SYNC_OLD_OP
26 
  UNSPEC_SYNC_NEW_OP
27 
  UNSPEC_SYNC_NEW_OP_12
28 
  UNSPEC_SYNC_OLD_OP_12
29 
  UNSPEC_SYNC_EXCHANGE
30 
  UNSPEC_SYNC_EXCHANGE_12
31 
  UNSPEC_MEMORY_BARRIER
32 
])
33 
 
34 
;; Atomic fetch bitwise operations.
35 
(define_code_iterator fetchop_bit [ior xor and])
36 
 
37 
;; Atomic HI and QI operations
38 
(define_code_iterator atomic_hiqi_op [plus minus ior xor and])
39 
 
40 
;; Atomic memory operations.
41 
 
42 
(define_expand "memory_barrier"
43 
  [(set (match_dup 0)
44 
        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
45 
  "GENERATE_SYNC"
46 
{
47 
  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
48 
  MEM_VOLATILE_P (operands[0]) = 1;
49 
})
50 
 
51 
(define_insn "*memory_barrier"
52 
  [(set (match_operand:BLK 0 "" "")
53 
        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
54 
  "GENERATE_SYNC"
55 
  { return mips_output_sync (); })
56 
 
57 
(define_insn "sync_compare_and_swap"
58 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
59 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
60 
   (set (match_dup 1)
61 
        (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
62 
                              (match_operand:GPR 3 "arith_operand" "I,d")]
63 
         UNSPEC_COMPARE_AND_SWAP))]
64 
  "GENERATE_LL_SC"
65 
  { return mips_output_sync_loop (insn, operands); }
66 
  [(set_attr "sync_insn1" "li,move")
67 
   (set_attr "sync_oldval" "0")
68 
   (set_attr "sync_mem" "1")
69 
   (set_attr "sync_required_oldval" "2")
70 
   (set_attr "sync_insn1_op2" "3")])
71 
 
72 
(define_expand "sync_compare_and_swap"
73 
  [(match_operand:SHORT 0 "register_operand")
74 
   (match_operand:SHORT 1 "memory_operand")
75 
   (match_operand:SHORT 2 "general_operand")
76 
   (match_operand:SHORT 3 "general_operand")]
77 
  "GENERATE_LL_SC"
78 
{
79 
  union mips_gen_fn_ptrs generator;
80 
  generator.fn_6 = gen_compare_and_swap_12;
81 
  mips_expand_atomic_qihi (generator,
82 
                           operands[0], operands[1], operands[2], operands[3]);
83 
  DONE;
84 
})
85 
 
86 
;; Helper insn for mips_expand_atomic_qihi.
87 
(define_insn "compare_and_swap_12"
88 
  [(set (match_operand:SI 0 "register_operand" "=&d,&d")
89 
        (match_operand:SI 1 "memory_operand" "+R,R"))
90 
   (set (match_dup 1)
91 
        (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
92 
                             (match_operand:SI 3 "register_operand" "d,d")
93 
                             (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
94 
                             (match_operand:SI 5 "reg_or_0_operand" "d,J")]
95 
                            UNSPEC_COMPARE_AND_SWAP_12))]
96 
  "GENERATE_LL_SC"
97 
  { return mips_output_sync_loop (insn, operands); }
98 
  [(set_attr "sync_oldval" "0")
99 
   (set_attr "sync_mem" "1")
100 
   (set_attr "sync_inclusive_mask" "2")
101 
   (set_attr "sync_exclusive_mask" "3")
102 
   (set_attr "sync_required_oldval" "4")
103 
   (set_attr "sync_insn1_op2" "5")])
104 
 
105 
(define_insn "sync_add"
106 
  [(set (match_operand:GPR 0 "memory_operand" "+R,R")
107 
        (unspec_volatile:GPR
108 
          [(plus:GPR (match_dup 0)
109 
                     (match_operand:GPR 1 "arith_operand" "I,d"))]
110 
          UNSPEC_SYNC_OLD_OP))]
111 
  "GENERATE_LL_SC"
112 
  { return mips_output_sync_loop (insn, operands); }
113 
  [(set_attr "sync_insn1" "addiu,addu")
114 
   (set_attr "sync_mem" "0")
115 
   (set_attr "sync_insn1_op2" "1")])
116 
 
117 
(define_expand "sync_"
118 
  [(set (match_operand:SHORT 0 "memory_operand")
119 
        (unspec_volatile:SHORT
120 
          [(atomic_hiqi_op:SHORT (match_dup 0)
121 
                                 (match_operand:SHORT 1 "general_operand"))]
122 
          UNSPEC_SYNC_OLD_OP))]
123 
  "GENERATE_LL_SC"
124 
{
125 
  union mips_gen_fn_ptrs generator;
126 
  generator.fn_4 = gen_sync__12;
127 
  mips_expand_atomic_qihi (generator,
128 
                           NULL, operands[0], operands[1], NULL);
129 
  DONE;
130 
})
131 
 
132 
;; Helper insn for sync_
133 
(define_insn "sync__12"
134 
  [(set (match_operand:SI 0 "memory_operand" "+R")
135 
        (unspec_volatile:SI
136 
          [(match_operand:SI 1 "register_operand" "d")
137 
           (match_operand:SI 2 "register_operand" "d")
138 
           (atomic_hiqi_op:SI (match_dup 0)
139 
                              (match_operand:SI 3 "reg_or_0_operand" "dJ"))]
140 
          UNSPEC_SYNC_OLD_OP_12))
141 
   (clobber (match_scratch:SI 4 "=&d"))]
142 
  "GENERATE_LL_SC"
143 
  { return mips_output_sync_loop (insn, operands); }
144 
  [(set_attr "sync_insn1" "")
145 
   (set_attr "sync_insn2" "and")
146 
   (set_attr "sync_mem" "0")
147 
   (set_attr "sync_inclusive_mask" "1")
148 
   (set_attr "sync_exclusive_mask" "2")
149 
   (set_attr "sync_insn1_op2" "3")
150 
   (set_attr "sync_oldval" "4")
151 
   (set_attr "sync_newval" "4")])
152 
 
153 
(define_expand "sync_old_"
154 
  [(parallel [
155 
     (set (match_operand:SHORT 0 "register_operand")
156 
          (match_operand:SHORT 1 "memory_operand"))
157 
     (set (match_dup 1)
158 
          (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
159 
                                    (match_dup 1)
160 
                                    (match_operand:SHORT 2 "general_operand"))]
161 
            UNSPEC_SYNC_OLD_OP))])]
162 
  "GENERATE_LL_SC"
163 
{
164 
  union mips_gen_fn_ptrs generator;
165 
  generator.fn_5 = gen_sync_old__12;
166 
  mips_expand_atomic_qihi (generator,
167 
                           operands[0], operands[1], operands[2], NULL);
168 
  DONE;
169 
})
170 
 
171 
;; Helper insn for sync_old_
172 
(define_insn "sync_old__12"
173 
  [(set (match_operand:SI 0 "register_operand" "=&d")
174 
        (match_operand:SI 1 "memory_operand" "+R"))
175 
   (set (match_dup 1)
176 
        (unspec_volatile:SI
177 
          [(match_operand:SI 2 "register_operand" "d")
178 
           (match_operand:SI 3 "register_operand" "d")
179 
           (atomic_hiqi_op:SI (match_dup 0)
180 
                              (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
181 
          UNSPEC_SYNC_OLD_OP_12))
182 
   (clobber (match_scratch:SI 5 "=&d"))]
183 
  "GENERATE_LL_SC"
184 
  { return mips_output_sync_loop (insn, operands); }
185 
  [(set_attr "sync_insn1" "")
186 
   (set_attr "sync_insn2" "and")
187 
   (set_attr "sync_oldval" "0")
188 
   (set_attr "sync_mem" "1")
189 
   (set_attr "sync_inclusive_mask" "2")
190 
   (set_attr "sync_exclusive_mask" "3")
191 
   (set_attr "sync_insn1_op2" "4")
192 
   (set_attr "sync_newval" "5")])
193 
 
194 
(define_expand "sync_new_"
195 
  [(parallel [
196 
     (set (match_operand:SHORT 0 "register_operand")
197 
          (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
198 
                                    (match_operand:SHORT 1 "memory_operand")
199 
                                    (match_operand:SHORT 2 "general_operand"))]
200 
            UNSPEC_SYNC_NEW_OP))
201 
     (set (match_dup 1)
202 
          (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
203 
            UNSPEC_SYNC_NEW_OP))])]
204 
  "GENERATE_LL_SC"
205 
{
206 
  union mips_gen_fn_ptrs generator;
207 
  generator.fn_5 = gen_sync_new__12;
208 
  mips_expand_atomic_qihi (generator,
209 
                           operands[0], operands[1], operands[2], NULL);
210 
  DONE;
211 
})
212 
 
213 
;; Helper insn for sync_new_
214 
(define_insn "sync_new__12"
215 
  [(set (match_operand:SI 0 "register_operand" "=&d")
216 
        (unspec_volatile:SI
217 
          [(match_operand:SI 1 "memory_operand" "+R")
218 
           (match_operand:SI 2 "register_operand" "d")
219 
           (match_operand:SI 3 "register_operand" "d")
220 
           (atomic_hiqi_op:SI (match_dup 0)
221 
                              (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
222 
          UNSPEC_SYNC_NEW_OP_12))
223 
   (set (match_dup 1)
224 
        (unspec_volatile:SI
225 
          [(match_dup 1)
226 
           (match_dup 2)
227 
           (match_dup 3)
228 
           (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
229 
  "GENERATE_LL_SC"
230 
  { return mips_output_sync_loop (insn, operands); }
231 
  [(set_attr "sync_insn1" "")
232 
   (set_attr "sync_insn2" "and")
233 
   (set_attr "sync_oldval" "0")
234 
   (set_attr "sync_newval" "0")
235 
   (set_attr "sync_mem" "1")
236 
   (set_attr "sync_inclusive_mask" "2")
237 
   (set_attr "sync_exclusive_mask" "3")
238 
   (set_attr "sync_insn1_op2" "4")])
239 
 
240 
(define_expand "sync_nand"
241 
  [(set (match_operand:SHORT 0 "memory_operand")
242 
        (unspec_volatile:SHORT
243 
          [(match_dup 0)
244 
           (match_operand:SHORT 1 "general_operand")]
245 
          UNSPEC_SYNC_OLD_OP))]
246 
  "GENERATE_LL_SC"
247 
{
248 
  union mips_gen_fn_ptrs generator;
249 
  generator.fn_4 = gen_sync_nand_12;
250 
  mips_expand_atomic_qihi (generator,
251 
                           NULL, operands[0], operands[1], NULL);
252 
  DONE;
253 
})
254 
 
255 
;; Helper insn for sync_nand
256 
(define_insn "sync_nand_12"
257 
  [(set (match_operand:SI 0 "memory_operand" "+R")
258 
        (unspec_volatile:SI
259 
          [(match_operand:SI 1 "register_operand" "d")
260 
           (match_operand:SI 2 "register_operand" "d")
261 
           (match_dup 0)
262 
           (match_operand:SI 3 "reg_or_0_operand" "dJ")]
263 
          UNSPEC_SYNC_OLD_OP_12))
264 
   (clobber (match_scratch:SI 4 "=&d"))]
265 
  "GENERATE_LL_SC"
266 
  { return mips_output_sync_loop (insn, operands); }
267 
  [(set_attr "sync_insn1" "and")
268 
   (set_attr "sync_insn2" "xor")
269 
   (set_attr "sync_mem" "0")
270 
   (set_attr "sync_inclusive_mask" "1")
271 
   (set_attr "sync_exclusive_mask" "2")
272 
   (set_attr "sync_insn1_op2" "3")
273 
   (set_attr "sync_oldval" "4")
274 
   (set_attr "sync_newval" "4")])
275 
 
276 
(define_expand "sync_old_nand"
277 
  [(parallel [
278 
     (set (match_operand:SHORT 0 "register_operand")
279 
          (match_operand:SHORT 1 "memory_operand"))
280 
     (set (match_dup 1)
281 
          (unspec_volatile:SHORT [(match_dup 1)
282 
                                  (match_operand:SHORT 2 "general_operand")]
283 
            UNSPEC_SYNC_OLD_OP))])]
284 
  "GENERATE_LL_SC"
285 
{
286 
  union mips_gen_fn_ptrs generator;
287 
  generator.fn_5 = gen_sync_old_nand_12;
288 
  mips_expand_atomic_qihi (generator,
289 
                           operands[0], operands[1], operands[2], NULL);
290 
  DONE;
291 
})
292 
 
293 
;; Helper insn for sync_old_nand
294 
(define_insn "sync_old_nand_12"
295 
  [(set (match_operand:SI 0 "register_operand" "=&d")
296 
        (match_operand:SI 1 "memory_operand" "+R"))
297 
   (set (match_dup 1)
298 
        (unspec_volatile:SI
299 
          [(match_operand:SI 2 "register_operand" "d")
300 
           (match_operand:SI 3 "register_operand" "d")
301 
           (match_operand:SI 4 "reg_or_0_operand" "dJ")]
302 
          UNSPEC_SYNC_OLD_OP_12))
303 
   (clobber (match_scratch:SI 5 "=&d"))]
304 
  "GENERATE_LL_SC"
305 
  { return mips_output_sync_loop (insn, operands); }
306 
  [(set_attr "sync_insn1" "and")
307 
   (set_attr "sync_insn2" "xor")
308 
   (set_attr "sync_oldval" "0")
309 
   (set_attr "sync_mem" "1")
310 
   (set_attr "sync_inclusive_mask" "2")
311 
   (set_attr "sync_exclusive_mask" "3")
312 
   (set_attr "sync_insn1_op2" "4")
313 
   (set_attr "sync_newval" "5")])
314 
 
315 
(define_expand "sync_new_nand"
316 
  [(parallel [
317 
     (set (match_operand:SHORT 0 "register_operand")
318 
          (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
319 
                                  (match_operand:SHORT 2 "general_operand")]
320 
            UNSPEC_SYNC_NEW_OP))
321 
     (set (match_dup 1)
322 
          (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
323 
            UNSPEC_SYNC_NEW_OP))])]
324 
  "GENERATE_LL_SC"
325 
{
326 
  union mips_gen_fn_ptrs generator;
327 
  generator.fn_5 = gen_sync_new_nand_12;
328 
  mips_expand_atomic_qihi (generator,
329 
                           operands[0], operands[1], operands[2], NULL);
330 
  DONE;
331 
})
332 
 
333 
;; Helper insn for sync_new_nand
334 
(define_insn "sync_new_nand_12"
335 
  [(set (match_operand:SI 0 "register_operand" "=&d")
336 
        (unspec_volatile:SI
337 
          [(match_operand:SI 1 "memory_operand" "+R")
338 
           (match_operand:SI 2 "register_operand" "d")
339 
           (match_operand:SI 3 "register_operand" "d")
340 
           (match_operand:SI 4 "reg_or_0_operand" "dJ")]
341 
          UNSPEC_SYNC_NEW_OP_12))
342 
   (set (match_dup 1)
343 
        (unspec_volatile:SI
344 
          [(match_dup 1)
345 
           (match_dup 2)
346 
           (match_dup 3)
347 
           (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
348 
  "GENERATE_LL_SC"
349 
  { return mips_output_sync_loop (insn, operands); }
350 
  [(set_attr "sync_insn1" "and")
351 
   (set_attr "sync_insn2" "xor")
352 
   (set_attr "sync_oldval" "0")
353 
   (set_attr "sync_newval" "0")
354 
   (set_attr "sync_mem" "1")
355 
   (set_attr "sync_inclusive_mask" "2")
356 
   (set_attr "sync_exclusive_mask" "3")
357 
   (set_attr "sync_insn1_op2" "4")])
358 
 
359 
(define_insn "sync_sub"
360 
  [(set (match_operand:GPR 0 "memory_operand" "+R")
361 
        (unspec_volatile:GPR
362 
          [(minus:GPR (match_dup 0)
363 
                      (match_operand:GPR 1 "register_operand" "d"))]
364 
         UNSPEC_SYNC_OLD_OP))]
365 
  "GENERATE_LL_SC"
366 
  { return mips_output_sync_loop (insn, operands); }
367 
  [(set_attr "sync_insn1" "subu")
368 
   (set_attr "sync_mem" "0")
369 
   (set_attr "sync_insn1_op2" "1")])
370 
 
371 
(define_insn "sync_old_add"
372 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
373 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
374 
   (set (match_dup 1)
375 
        (unspec_volatile:GPR
376 
          [(plus:GPR (match_dup 1)
377 
                     (match_operand:GPR 2 "arith_operand" "I,d"))]
378 
         UNSPEC_SYNC_OLD_OP))]
379 
  "GENERATE_LL_SC"
380 
  { return mips_output_sync_loop (insn, operands); }
381 
  [(set_attr "sync_insn1" "addiu,addu")
382 
   (set_attr "sync_oldval" "0")
383 
   (set_attr "sync_mem" "1")
384 
   (set_attr "sync_insn1_op2" "2")])
385 
 
386 
(define_insn "sync_old_sub"
387 
  [(set (match_operand:GPR 0 "register_operand" "=&d")
388 
        (match_operand:GPR 1 "memory_operand" "+R"))
389 
   (set (match_dup 1)
390 
        (unspec_volatile:GPR
391 
          [(minus:GPR (match_dup 1)
392 
                      (match_operand:GPR 2 "register_operand" "d"))]
393 
         UNSPEC_SYNC_OLD_OP))]
394 
  "GENERATE_LL_SC"
395 
  { return mips_output_sync_loop (insn, operands); }
396 
  [(set_attr "sync_insn1" "subu")
397 
   (set_attr "sync_oldval" "0")
398 
   (set_attr "sync_mem" "1")
399 
   (set_attr "sync_insn1_op2" "2")])
400 
 
401 
(define_insn "sync_new_add"
402 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
403 
        (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
404 
                  (match_operand:GPR 2 "arith_operand" "I,d")))
405 
   (set (match_dup 1)
406 
        (unspec_volatile:GPR
407 
          [(plus:GPR (match_dup 1) (match_dup 2))]
408 
         UNSPEC_SYNC_NEW_OP))]
409 
  "GENERATE_LL_SC"
410 
  { return mips_output_sync_loop (insn, operands); }
411 
  [(set_attr "sync_insn1" "addiu,addu")
412 
   (set_attr "sync_oldval" "0")
413 
   (set_attr "sync_newval" "0")
414 
   (set_attr "sync_mem" "1")
415 
   (set_attr "sync_insn1_op2" "2")])
416 
 
417 
(define_insn "sync_new_sub"
418 
  [(set (match_operand:GPR 0 "register_operand" "=&d")
419 
        (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
420 
                   (match_operand:GPR 2 "register_operand" "d")))
421 
   (set (match_dup 1)
422 
        (unspec_volatile:GPR
423 
          [(minus:GPR (match_dup 1) (match_dup 2))]
424 
         UNSPEC_SYNC_NEW_OP))]
425 
  "GENERATE_LL_SC"
426 
  { return mips_output_sync_loop (insn, operands); }
427 
  [(set_attr "sync_insn1" "subu")
428 
   (set_attr "sync_oldval" "0")
429 
   (set_attr "sync_newval" "0")
430 
   (set_attr "sync_mem" "1")
431 
   (set_attr "sync_insn1_op2" "2")])
432 
 
433 
(define_insn "sync_"
434 
  [(set (match_operand:GPR 0 "memory_operand" "+R,R")
435 
        (unspec_volatile:GPR
436 
          [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
437 
                              (match_dup 0))]
438 
         UNSPEC_SYNC_OLD_OP))]
439 
  "GENERATE_LL_SC"
440 
  { return mips_output_sync_loop (insn, operands); }
441 
  [(set_attr "sync_insn1" ",")
442 
   (set_attr "sync_mem" "0")
443 
   (set_attr "sync_insn1_op2" "1")])
444 
 
445 
(define_insn "sync_old_"
446 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
447 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
448 
   (set (match_dup 1)
449 
        (unspec_volatile:GPR
450 
          [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
451 
                            (match_dup 1))]
452 
         UNSPEC_SYNC_OLD_OP))]
453 
  "GENERATE_LL_SC"
454 
  { return mips_output_sync_loop (insn, operands); }
455 
  [(set_attr "sync_insn1" ",")
456 
   (set_attr "sync_oldval" "0")
457 
   (set_attr "sync_mem" "1")
458 
   (set_attr "sync_insn1_op2" "2")])
459 
 
460 
(define_insn "sync_new_"
461 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
462 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
463 
   (set (match_dup 1)
464 
        (unspec_volatile:GPR
465 
          [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
466 
                            (match_dup 1))]
467 
         UNSPEC_SYNC_NEW_OP))]
468 
  "GENERATE_LL_SC"
469 
  { return mips_output_sync_loop (insn, operands); }
470 
  [(set_attr "sync_insn1" ",")
471 
   (set_attr "sync_oldval" "0")
472 
   (set_attr "sync_newval" "0")
473 
   (set_attr "sync_mem" "1")
474 
   (set_attr "sync_insn1_op2" "2")])
475 
 
476 
(define_insn "sync_nand"
477 
  [(set (match_operand:GPR 0 "memory_operand" "+R,R")
478 
        (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
479 
         UNSPEC_SYNC_OLD_OP))]
480 
  "GENERATE_LL_SC"
481 
  { return mips_output_sync_loop (insn, operands); }
482 
  [(set_attr "sync_insn1" "andi,and")
483 
   (set_attr "sync_insn2" "not")
484 
   (set_attr "sync_mem" "0")
485 
   (set_attr "sync_insn1_op2" "1")])
486 
 
487 
(define_insn "sync_old_nand"
488 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
489 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
490 
   (set (match_dup 1)
491 
        (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
492 
         UNSPEC_SYNC_OLD_OP))]
493 
  "GENERATE_LL_SC"
494 
  { return mips_output_sync_loop (insn, operands); }
495 
  [(set_attr "sync_insn1" "andi,and")
496 
   (set_attr "sync_insn2" "not")
497 
   (set_attr "sync_oldval" "0")
498 
   (set_attr "sync_mem" "1")
499 
   (set_attr "sync_insn1_op2" "2")])
500 
 
501 
(define_insn "sync_new_nand"
502 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
503 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
504 
   (set (match_dup 1)
505 
        (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
506 
         UNSPEC_SYNC_NEW_OP))]
507 
  "GENERATE_LL_SC"
508 
  { return mips_output_sync_loop (insn, operands); }
509 
  [(set_attr "sync_insn1" "andi,and")
510 
   (set_attr "sync_insn2" "not")
511 
   (set_attr "sync_oldval" "0")
512 
   (set_attr "sync_newval" "0")
513 
   (set_attr "sync_mem" "1")
514 
   (set_attr "sync_insn1_op2" "2")])
515 
 
516 
(define_insn "sync_lock_test_and_set"
517 
  [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
518 
        (match_operand:GPR 1 "memory_operand" "+R,R"))
519 
   (set (match_dup 1)
520 
        (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
521 
         UNSPEC_SYNC_EXCHANGE))]
522 
  "GENERATE_LL_SC"
523 
  { return mips_output_sync_loop (insn, operands); }
524 
  [(set_attr "sync_release_barrier" "no")
525 
   (set_attr "sync_insn1" "li,move")
526 
   (set_attr "sync_oldval" "0")
527 
   (set_attr "sync_mem" "1")
528 
   (set_attr "sync_insn1_op2" "2")])
529 
 
530 
(define_expand "sync_lock_test_and_set"
531 
  [(match_operand:SHORT 0 "register_operand")
532 
   (match_operand:SHORT 1 "memory_operand")
533 
   (match_operand:SHORT 2 "general_operand")]
534 
  "GENERATE_LL_SC"
535 
{
536 
  union mips_gen_fn_ptrs generator;
537 
  generator.fn_5 = gen_test_and_set_12;
538 
  mips_expand_atomic_qihi (generator,
539 
                           operands[0], operands[1], operands[2], NULL);
540 
  DONE;
541 
})
542 
 
543 
(define_insn "test_and_set_12"
544 
  [(set (match_operand:SI 0 "register_operand" "=&d")
545 
        (match_operand:SI 1 "memory_operand" "+R"))
546 
   (set (match_dup 1)
547 
        (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
548 
                             (match_operand:SI 3 "register_operand" "d")
549 
                             (match_operand:SI 4 "reg_or_0_operand" "dJ")]
550 
          UNSPEC_SYNC_EXCHANGE_12))]
551 
  "GENERATE_LL_SC"
552 
  { return mips_output_sync_loop (insn, operands); }
553 
  [(set_attr "sync_release_barrier" "no")
554 
   (set_attr "sync_oldval" "0")
555 
   (set_attr "sync_mem" "1")
556 
   ;; Unused, but needed to give the number of operands expected by
557 
   ;; the expander.
558 
   (set_attr "sync_inclusive_mask" "2")
559 
   (set_attr "sync_exclusive_mask" "3")
560 
   (set_attr "sync_insn1_op2" "4")])

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