OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mn10300/] [constraints.md] - Blame information for rev 709

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
;; Constraint definitions for the MN10300.
2
;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
3
;;
4
;; This file is part of GCC.
5
;;
6
;; GCC is free software; you can redistribute it and/or modify
7
;; it under the terms of the GNU General Public License as published by
8
;; the Free Software Foundation; either version 3, or (at your option)
9
;; any later version.
10
;;
11
;; GCC is distributed in the hope that it will be useful,
12
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
;; GNU General Public License for more details.
15
;;
16
;; You should have received a copy of the GNU General Public License
17
;; along with GCC; see the file COPYING3.  If not see
18
;; .
19
 
20
(define_register_constraint "d" "DATA_REGS"
21
  "A data register.")
22
 
23
(define_register_constraint "a" "ADDRESS_REGS"
24
  "An address register.")
25
 
26
;; This can be used for QI/HImode memory operations, and most arithmetic.
27
;; AM33 supports these on all registers, where MN103 needs DATA_REGS.
28
(define_register_constraint "D" "TARGET_AM33 ? GENERAL_REGS : DATA_REGS"
29
  "A general register for AM33, and a data register otherwise.")
30
 
31
;; Similarly for ADDRESS_REGS vs GENERAL_REGS.
32
(define_register_constraint "A" "TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS"
33
  "A general register for AM33, and an address register otherwise.")
34
 
35
(define_register_constraint "y" "SP_REGS"
36
  "An SP register (if available).")
37
 
38
(define_register_constraint "z" "MDR_REGS"
39
  "The MDR register.")
40
 
41
(define_register_constraint "x" "TARGET_AM33 ? EXTENDED_REGS : NO_REGS"
42
  "An extended register.")
43
 
44
(define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS"
45
  "A floating point register.")
46
 
47
(define_register_constraint "c" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS"
48
  "A floating point accumulator register.")
49
 
50
(define_memory_constraint "Q"
51
  "@internal"
52
  (and (match_code "mem")
53
       (match_test "!CONSTANT_ADDRESS_P (XEXP (op, 0))")))
54
 
55
(define_constraint "S"
56
  "@internal"
57
  (if_then_else (match_test "flag_pic")
58
        (and (match_test "GET_CODE (op) == UNSPEC")
59
             (ior (match_test "XINT (op, 1) == UNSPEC_PLT")
60
                  (match_test "XINT (op, 1) == UNSPEC_PIC")
61
                  (match_test "XINT (op, 1) == UNSPEC_GOTSYM_OFF")))
62
        (match_test "GET_CODE (op) == SYMBOL_REF")))
63
 
64
;; Integer constraints
65
 
66
(define_constraint "I"
67
  "An integer zero."
68
  (and (match_code "const_int")
69
       (match_test "ival == 0")))
70
 
71
(define_constraint "J"
72
  "An integer one."
73
  (and (match_code "const_int")
74
       (match_test "ival == 1")))
75
 
76
(define_constraint "K"
77
  "An integer two."
78
  (and (match_code "const_int")
79
       (match_test "ival == 2")))
80
 
81
(define_constraint "L"
82
  "An integer four."
83
  (and (match_code "const_int")
84
       (match_test "ival == 4")))
85
 
86
(define_constraint "M"
87
  "An integer three."
88
  (and (match_code "const_int")
89
       (match_test "ival == 3")))
90
 
91
(define_constraint "N"
92
  "An integer of either 255 or 65535."
93
  (and (match_code "const_int")
94
       (ior (match_test "ival == 255")
95
            (match_test "ival == 65535"))))
96
 
97
(define_constraint "O"
98
  "An integer between -8 and +7 inclusive."
99
  (and (match_code "const_int")
100
       (and (match_test "ival >= -8")
101
            (match_test "ival <=  7"))))
102
 
103
;; Floating-point constraints
104
(define_constraint "G"
105
  "Floating-point zero."
106
  (and (match_code "const_double")
107
       (match_test "op == CONST0_RTX (mode)")))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.