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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [pa/] [pa64-regs.h] - Blame information for rev 709

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1 709 jeremybenn
/* Configuration for GCC-compiler for PA-RISC.
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   Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2010
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   Free Software Foundation, Inc.
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This file is part of GCC.
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7
GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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17
You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3.  If not see
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<http://www.gnu.org/licenses/>.  */
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/* Standard register usage.
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   It is safe to refer to actual register numbers in this file.  */
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/* Number of actual hardware registers.
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   The hardware registers are assigned numbers for the compiler
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   from 0 to just below FIRST_PSEUDO_REGISTER.
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   All registers that the compiler knows about must be given numbers,
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   even those that are not normally considered general registers.
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   HP-PA 2.0w has 32 fullword registers and 32 floating point
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   registers. However, the floating point registers behave
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   differently: the left and right halves of registers are addressable
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   as 32-bit registers.
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36
   Due to limitations within GCC itself, we do not expose the left/right
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   half addressability when in wide mode.  This is not a major performance
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   issue as using the halves independently triggers false dependency stalls
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   anyway.  */
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#define FIRST_PSEUDO_REGISTER 62  /* 32 general regs + 28 fp regs +
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                                     + 1 shift reg + frame pointer */
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/* 1 for registers that have pervasive standard uses
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   and are not available for the register allocator.
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   On the HP-PA, these are:
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   Reg 0        = 0 (hardware). However, 0 is used for condition code,
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                  so is not fixed.
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   Reg 1        = ADDIL target/Temporary (hardware).
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   Reg 2        = Return Pointer
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   Reg 3        = Frame Pointer
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   Reg 4        = Frame Pointer (>8k varying frame with HP compilers only)
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   Reg 4-18     = Preserved Registers
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   Reg 19       = Linkage Table Register in HPUX 8.0 shared library scheme.
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   Reg 20-22    = Temporary Registers
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   Reg 23-26    = Temporary/Parameter Registers
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   Reg 27       = Global Data Pointer (hp)
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   Reg 28       = Temporary/Return Value register
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   Reg 29       = Temporary/Static Chain/Return Value register #2
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   Reg 30       = stack pointer
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   Reg 31       = Temporary/Millicode Return Pointer (hp)
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64
   Freg 0-3     = Status Registers      -- Not known to the compiler.
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   Freg 4-7     = Arguments/Return Value
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   Freg 8-11    = Temporary Registers
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   Freg 12-21   = Preserved Registers
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   Freg 22-31 = Temporary Registers
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70
*/
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#define FIXED_REGISTERS  \
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 {0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 1, 0, 0, 1, 0, \
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  /* fp registers */      \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0,                 \
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  /* shift register and soft frame pointer */     \
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  0, 1}
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/* 1 for registers not available across function calls.
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   These must include the FIXED_REGISTERS and also any
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   registers that can be used without being saved.
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   The latter must include the registers where values are returned
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   and the register where structure-value addresses are passed.
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   Aside from that, you can include as many other registers as you like.  */
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#define CALL_USED_REGISTERS  \
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 {1, 1, 1, 0, 0, 0, 0, 0, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 0, 1, 1, 1, 1, 1, \
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  1, 1, 1, 1, 1, 1, 1, 1, \
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  /* fp registers */      \
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  1, 1, 1, 1, 1, 1, 1, 1, \
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  0, 0, 0, 0, 0, 0, 0, 0, \
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  0, 0, 1, 1, 1, 1, 1, 1, \
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  1, 1, 1, 1,             \
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  /* shift register and soft frame pointer */    \
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  1, 1}
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/* Allocate the call used registers first.  This should minimize
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   the number of registers that need to be saved (as call used
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   registers will generally not be allocated across a call).
107
 
108
   Experimentation has shown slightly better results by allocating
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   FP registers first.  We allocate the caller-saved registers more
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   or less in reverse order to their allocation as arguments.  */
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#define REG_ALLOC_ORDER \
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 {                                      \
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  /* caller-saved fp regs.  */          \
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  50, 51, 52, 53, 54, 55, 56, 57,       \
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  58, 59, 39, 38, 37, 36, 35, 34,       \
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  33, 32,                               \
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  /* caller-saved general regs.  */     \
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  28, 31, 19, 20, 21, 22, 23, 24,       \
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  25, 26, 29,  2,                       \
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  /* callee-saved fp regs.  */          \
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  40, 41, 42, 43, 44, 45, 46, 47,       \
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  48, 49,                               \
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  /* callee-saved general regs.  */     \
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   3,  4,  5,  6,  7,  8,  9, 10,       \
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  11, 12, 13, 14, 15, 16, 17, 18,       \
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  /* special registers.  */             \
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   1, 27, 30,  0, 60, 61}
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/* Return number of consecutive hard regs needed starting at reg REGNO
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   to hold something of mode MODE.
133
   This is ordinarily the length in words of a value of mode MODE
134
   but can be less for certain modes in special long registers.
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136
   For PA64, GPRs and FPRs hold 64 bits worth.  We ignore the 32-bit
137
   addressability of the FPRs and pretend each register holds precisely
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   WORD_SIZE bits.  Note that SCmode values are placed in a single FPR.
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   Thus, any patterns defined to operate on these values would have to
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   use the 32-bit addressability of the FPR registers.  */
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#define HARD_REGNO_NREGS(REGNO, MODE)                                   \
142
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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144
/* These are the valid FP modes.  */
145
#define VALID_FP_MODE_P(MODE)                                           \
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  ((MODE) == SFmode || (MODE) == DFmode                                 \
147
   || (MODE) == SCmode || (MODE) == DCmode                              \
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   || (MODE) == SImode || (MODE) == DImode)
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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   On the HP-PA, the cpu registers can hold any mode.  We
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   force this to be an even register if it cannot hold the full mode.  */
153
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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  ((REGNO) == 0                                                          \
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   ? (MODE) == CCmode || (MODE) == CCFPmode                             \
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   : (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE)                           \
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   /* Make wide modes be in aligned registers.  */                      \
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   : FP_REGNO_P (REGNO)                                                 \
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     ? (VALID_FP_MODE_P (MODE)                                          \
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        && (GET_MODE_SIZE (MODE) <= 8                                   \
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            || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0)        \
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            || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0)))      \
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   : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD                            \
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      || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD                    \
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          && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))  \
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      || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD                    \
167
          && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
168
 
169
/* How to renumber registers for dbx and gdb.
170
 
171
   Registers 0  - 31 remain unchanged.
172
 
173
   Registers 32 - 59 are mapped to 72, 74, 76 ...
174
 
175
   Register 60 is mapped to 32.  */
176
#define DBX_REGISTER_NUMBER(REGNO) \
177
  ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
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179
/* We must not use the DBX register numbers for the DWARF 2 CFA column
180
   numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
181
   Instead use the identity mapping.  */
182
#define DWARF_FRAME_REGNUM(REG) REG
183
 
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/* Define the classes of registers for register constraints in the
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   machine description.  Also define ranges of constants.
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   One of the classes must always be named ALL_REGS and include all hard regs.
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   If there is more than one class, another class must be named NO_REGS
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   and contain no registers.
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191
   The name GENERAL_REGS must be the name of a class (or an alias for
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   another name such as ALL_REGS).  This is the class of registers
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   that is allowed by "g" or "r" in a register constraint.
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   Also, registers outside this class are allocated only when
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   instructions express preferences for them.
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   The classes must be numbered in nondecreasing order; that is,
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   a larger-numbered class must never be contained completely
199
   in a smaller-numbered class.
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   For any two classes, it is very desirable that there be another
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   class that represents their union.  */
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  /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
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     1.1 fp regs, and the high 1.1 fp regs, to which the operands of
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     fmpyadd and fmpysub are restricted.  */
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enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
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                 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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211
#define N_REG_CLASSES (int) LIM_REG_CLASSES
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213
/* Give names of register classes as strings for dump file.  */
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215
#define REG_CLASS_NAMES \
216
  {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
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   "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
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/* Define which registers fit in which classes.
220
   This is an initializer for a vector of HARD_REG_SET
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   of length N_REG_CLASSES. Register 0, the "condition code" register,
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   is in no class.  */
223
 
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#define REG_CLASS_CONTENTS      \
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 {{0x00000000, 0x00000000},     /* NO_REGS */                   \
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  {0x00000002, 0x00000000},     /* R1_REGS */                   \
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  {0xfffffffe, 0x20000000},     /* GENERAL_REGS */              \
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  {0x00000000, 0x00000000},     /* FPUPPER_REGS */              \
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  {0x00000000, 0x0fffffff},     /* FP_REGS */                   \
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  {0xfffffffe, 0x2fffffff},     /* GENERAL_OR_FP_REGS */        \
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  {0x00000000, 0x10000000},     /* SHIFT_REGS */                \
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  {0xfffffffe, 0x3fffffff}}     /* ALL_REGS */
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/* Defines invalid mode changes.  */
235
 
236
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
237
  pa_cannot_change_mode_class (FROM, TO, CLASS)
238
 
239
/* Return the class number of the smallest class containing
240
   reg number REGNO.  This could be a conditional expression
241
   or could index an array.  */
242
 
243
#define REGNO_REG_CLASS(REGNO)                                          \
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  ((REGNO) == 0 ? NO_REGS                                                \
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   : (REGNO) == 1 ? R1_REGS                                             \
246
   : (REGNO) < 32 || (REGNO) == 61 ? GENERAL_REGS                       \
247
   : (REGNO) < 60 ? FP_REGS                                             \
248
   : SHIFT_REGS)
249
 
250
/* Return the maximum number of consecutive registers
251
   needed to represent mode MODE in a register of class CLASS.  */
252
#define CLASS_MAX_NREGS(CLASS, MODE)                                    \
253
  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
254
 
255
/* 1 if N is a possible register number for function argument passing.  */
256
 
257
#define FUNCTION_ARG_REGNO_P(N) \
258
  ((((N) >= 19) && (N) <= 26) \
259
   || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
260
 
261
/* How to refer to registers in assembler output.
262
   This sequence is indexed by compiler's hard-register-number (see above).  */
263
 
264
#define REGISTER_NAMES \
265
{"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
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 "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
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 "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
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 "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
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 "%fr4",  "%fr5",   "%fr6",  "%fr7",   "%fr8",  "%fr9",   "%fr10", "%fr11",  \
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 "%fr12", "%fr13",  "%fr14", "%fr15",  "%fr16", "%fr17",  "%fr18", "%fr19",  \
271
 "%fr20", "%fr21",  "%fr22", "%fr23",  "%fr24", "%fr25",  "%fr26", "%fr27",  \
272
 "%fr28", "%fr29",  "%fr30", "%fr31",  "SAR",   "sfp"}
273
 
274
#define ADDITIONAL_REGISTER_NAMES \
275
 {{"%cr11",60}}
276
 
277
#define FP_SAVED_REG_LAST 49
278
#define FP_SAVED_REG_FIRST 40
279
#define FP_REG_STEP 1
280
#define FP_REG_FIRST 32
281
#define FP_REG_LAST 59

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