OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [pdp11/] [predicates.md] - Blame information for rev 749

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
;;- Predicate definitions for the pdp11 for GNU C compiler
2
;; Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2004, 2005
3
;; 2007, 2008, 2010 Free Software Foundation, Inc.
4
;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5
 
6
;; This file is part of GCC.
7
 
8
;; GCC is free software; you can redistribute it and/or modify
9
;; it under the terms of the GNU General Public License as published by
10
;; the Free Software Foundation; either version 3, or (at your option)
11
;; any later version.
12
 
13
;; GCC is distributed in the hope that it will be useful,
14
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
;; GNU General Public License for more details.
17
 
18
;; You should have received a copy of the GNU General Public License
19
;; along with GCC; see the file COPYING3.  If not see
20
;; .
21
 
22
;; Match CONST_DOUBLE zero for tstd/tstf.
23
(define_predicate "register_or_const0_operand"
24
  (ior (match_operand 0 "register_operand")
25
       (match_test "op == CONST0_RTX (GET_MODE (op))")))
26
 
27
;; Accept integer arguments in the range -4..-2 and 2..4, which are the
28
;; shift counts for which we unroll a shift.  This matches the rule for
29
;; the "O" constraint.
30
(define_predicate "expand_shift_operand"
31
  (match_code "const_int")
32
{
33
  int sh;
34
 
35
  sh = INTVAL (op);
36
  return (abs (sh) > 1 && abs (sh) <= 4);
37
})
38
 
39
;; Accept anything general_operand accepts, except that registers must
40
;; be FPU registers.
41
(define_predicate "float_operand"
42
  (if_then_else (match_code "reg")
43
                (ior
44
                 (match_test "REGNO_REG_CLASS (REGNO (op)) == LOAD_FPU_REGS")
45
                 (match_test "REGNO_REG_CLASS (REGNO (op)) == NO_LOAD_FPU_REGS"))
46
                (match_test "general_operand (op, mode)")))
47
 
48
;; Accept anything nonimmediate_operand accepts, except that registers must
49
;; be FPU registers.
50
(define_predicate "float_nonimm_operand"
51
  (if_then_else (match_code "reg")
52
                (ior
53
                 (match_test "REGNO_REG_CLASS (REGNO (op)) == LOAD_FPU_REGS")
54
                 (match_test "REGNO_REG_CLASS (REGNO (op)) == NO_LOAD_FPU_REGS"))
55
                (match_test "nonimmediate_operand (op, mode)")))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.