| 1 |
709 |
jeremybenn |
;; Machine Description for Renesas RL78 processors
|
| 2 |
|
|
;; Copyright (C) 2011 Free Software Foundation, Inc.
|
| 3 |
|
|
;; Contributed by Red Hat.
|
| 4 |
|
|
|
| 5 |
|
|
;; This file is part of GCC.
|
| 6 |
|
|
|
| 7 |
|
|
;; GCC is free software; you can redistribute it and/or modify
|
| 8 |
|
|
;; it under the terms of the GNU General Public License as published by
|
| 9 |
|
|
;; the Free Software Foundation; either version 3, or (at your option)
|
| 10 |
|
|
;; any later version.
|
| 11 |
|
|
|
| 12 |
|
|
;; GCC is distributed in the hope that it will be useful,
|
| 13 |
|
|
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 14 |
|
|
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 15 |
|
|
;; GNU General Public License for more details.
|
| 16 |
|
|
|
| 17 |
|
|
;; You should have received a copy of the GNU General Public License
|
| 18 |
|
|
;; along with GCC; see the file COPYING3. If not see
|
| 19 |
|
|
;; .
|
| 20 |
|
|
|
| 21 |
|
|
;; The insns in this file correspond to the actual opcodes the RL78
|
| 22 |
|
|
;; can issue with real registers. All insns in here should be
|
| 23 |
|
|
;; conditional on rl78_real_insns_ok() returning true, and should
|
| 24 |
|
|
;; allow virtual registers in their predicates - the reorg pass that
|
| 25 |
|
|
;; allocates physical registers uses the constraints to select
|
| 26 |
|
|
;; registers, but insns with virtual registers MUST match one of these
|
| 27 |
|
|
;; patterns - other than the constraints - so that the operand info is
|
| 28 |
|
|
;; properly set up for the alloc pass.
|
| 29 |
|
|
|
| 30 |
|
|
;;---------- Moving ------------------------
|
| 31 |
|
|
|
| 32 |
|
|
(define_insn "movqi_es"
|
| 33 |
|
|
[(set (reg:QI ES_REG)
|
| 34 |
|
|
(match_operand:QI 0 "register_operand" "a"))]
|
| 35 |
|
|
""
|
| 36 |
|
|
"mov\tes, %0"
|
| 37 |
|
|
)
|
| 38 |
|
|
|
| 39 |
|
|
(define_insn "movqi_cs"
|
| 40 |
|
|
[(set (reg:QI CS_REG)
|
| 41 |
|
|
(match_operand:QI 0 "register_operand" "a"))]
|
| 42 |
|
|
""
|
| 43 |
|
|
"mov\tcs, %0"
|
| 44 |
|
|
)
|
| 45 |
|
|
|
| 46 |
|
|
(define_insn "*movqi_real"
|
| 47 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=g,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx")
|
| 48 |
|
|
(match_operand 1 "general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R"))]
|
| 49 |
|
|
"rl78_real_insns_ok ()"
|
| 50 |
|
|
"@
|
| 51 |
|
|
; mov\t%0, %1
|
| 52 |
|
|
oneb\t%0
|
| 53 |
|
|
clrb\t%0
|
| 54 |
|
|
mov\t%0, %1
|
| 55 |
|
|
mov\t%0, %1
|
| 56 |
|
|
mov\t%0, %1
|
| 57 |
|
|
mov\t%0, %1
|
| 58 |
|
|
mov\t%0, %S1"
|
| 59 |
|
|
)
|
| 60 |
|
|
|
| 61 |
|
|
(define_insn "*movhi_real"
|
| 62 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=g,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
|
| 63 |
|
|
(match_operand:HI 1 "general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))]
|
| 64 |
|
|
"rl78_real_insns_ok ()"
|
| 65 |
|
|
"@
|
| 66 |
|
|
; movw\t%0, %1
|
| 67 |
|
|
onew\t%0
|
| 68 |
|
|
clrw\t%0
|
| 69 |
|
|
movw\t%0, %1
|
| 70 |
|
|
movw\t%0, %1
|
| 71 |
|
|
movw\t%0, %1
|
| 72 |
|
|
movw\t%0, %S1
|
| 73 |
|
|
movw\t%0, %1
|
| 74 |
|
|
movw\t%0, %1"
|
| 75 |
|
|
)
|
| 76 |
|
|
|
| 77 |
|
|
;;---------- Conversions ------------------------
|
| 78 |
|
|
|
| 79 |
|
|
(define_insn "*zero_extendqihi2_real"
|
| 80 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=rv,A")
|
| 81 |
|
|
(zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
|
| 82 |
|
|
"rl78_real_insns_ok ()"
|
| 83 |
|
|
"@
|
| 84 |
|
|
mov\t%Q0, #0
|
| 85 |
|
|
mov\tx, a \;mov\ta, #0"
|
| 86 |
|
|
)
|
| 87 |
|
|
|
| 88 |
|
|
(define_insn "*extendqihi2_real"
|
| 89 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=A,A")
|
| 90 |
|
|
(sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
|
| 91 |
|
|
"rl78_real_insns_ok ()"
|
| 92 |
|
|
"@
|
| 93 |
|
|
shlw\t%0, 8 \;sarw\t%0, 8
|
| 94 |
|
|
sarw\t%0, 8"
|
| 95 |
|
|
)
|
| 96 |
|
|
|
| 97 |
|
|
;;---------- Arithmetic ------------------------
|
| 98 |
|
|
|
| 99 |
|
|
(define_insn "*addqi3_real"
|
| 100 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=rvWabWhlWh1,rvWabWhlWh1,a,*bcdehl")
|
| 101 |
|
|
(plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
|
| 102 |
|
|
(match_operand:QI 2 "general_operand" "K,L,RWhlWh1i,a")))
|
| 103 |
|
|
]
|
| 104 |
|
|
"rl78_real_insns_ok ()"
|
| 105 |
|
|
"@
|
| 106 |
|
|
inc\t%0
|
| 107 |
|
|
dec\t%0
|
| 108 |
|
|
add\t%0, %2
|
| 109 |
|
|
add\t%0, %2"
|
| 110 |
|
|
)
|
| 111 |
|
|
|
| 112 |
|
|
(define_insn "*addhi3_real"
|
| 113 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=vABDTWh1Wab,vABDTWh1Wab,v,v,A,S,S,A")
|
| 114 |
|
|
(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0,0,S")
|
| 115 |
|
|
(match_operand:HI 2 "general_operand" "K,L,N,O,RWh1WhlWabiv,Int8,J,Ri")))
|
| 116 |
|
|
]
|
| 117 |
|
|
"rl78_real_insns_ok ()"
|
| 118 |
|
|
"@
|
| 119 |
|
|
incw\t%0
|
| 120 |
|
|
decw\t%0
|
| 121 |
|
|
incw\t%0 \;incw\t%0
|
| 122 |
|
|
decw\t%0 \;decw\t%0
|
| 123 |
|
|
addw\t%0, %p2
|
| 124 |
|
|
addw\t%0, %2
|
| 125 |
|
|
subw\t%0, %m2
|
| 126 |
|
|
movw\t%0, %1 \;addw\t%0, %2"
|
| 127 |
|
|
)
|
| 128 |
|
|
|
| 129 |
|
|
(define_insn "*addqihi3a_real"
|
| 130 |
|
|
[(set (match_operand:HI 0 "register_operand" "=r")
|
| 131 |
|
|
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%r"))
|
| 132 |
|
|
(match_operand:HI 2 "register_operand" "r")))
|
| 133 |
|
|
]
|
| 134 |
|
|
"rl78_real_insns_ok ()"
|
| 135 |
|
|
"add\t%q0, %q1 \;addc\t%Q0, #0"
|
| 136 |
|
|
)
|
| 137 |
|
|
|
| 138 |
|
|
(define_insn "*subqi3_real"
|
| 139 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v")
|
| 140 |
|
|
(minus:QI (match_operand:QI 1 "general_operand" "0,0,0")
|
| 141 |
|
|
(match_operand:QI 2 "general_operand" "RiWabWhbWh1Whl,a,i")))
|
| 142 |
|
|
]
|
| 143 |
|
|
"rl78_real_insns_ok ()"
|
| 144 |
|
|
"sub\t%0, %2"
|
| 145 |
|
|
)
|
| 146 |
|
|
|
| 147 |
|
|
(define_insn "*subhi3_real"
|
| 148 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=A,S")
|
| 149 |
|
|
(minus:HI (match_operand:HI 1 "general_operand" "0,0")
|
| 150 |
|
|
(match_operand:HI 2 "general_operand" "iBDTWabWh1v,i")))
|
| 151 |
|
|
]
|
| 152 |
|
|
"rl78_real_insns_ok ()"
|
| 153 |
|
|
"subw\t%0, %2"
|
| 154 |
|
|
)
|
| 155 |
|
|
|
| 156 |
|
|
(define_insn "*umulhi3_shift_real"
|
| 157 |
|
|
[(set (match_operand:HI 0 "register_operand" "=A,A")
|
| 158 |
|
|
(mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
|
| 159 |
|
|
(match_operand:HI 2 "rl78_24_operand" "N,i")))]
|
| 160 |
|
|
"rl78_real_insns_ok ()"
|
| 161 |
|
|
"@
|
| 162 |
|
|
shlw\t%0, 1
|
| 163 |
|
|
shlw\t%0, 2"
|
| 164 |
|
|
)
|
| 165 |
|
|
|
| 166 |
|
|
(define_insn "*umulqihi3_real"
|
| 167 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=A")
|
| 168 |
|
|
(mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
|
| 169 |
|
|
(zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
|
| 170 |
|
|
"rl78_real_insns_ok ()"
|
| 171 |
|
|
"mulu\t%2"
|
| 172 |
|
|
)
|
| 173 |
|
|
|
| 174 |
|
|
(define_insn "*andqi3_real"
|
| 175 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
|
| 176 |
|
|
(and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
|
| 177 |
|
|
(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
|
| 178 |
|
|
]
|
| 179 |
|
|
"rl78_real_insns_ok ()"
|
| 180 |
|
|
"and\t%0, %2"
|
| 181 |
|
|
)
|
| 182 |
|
|
|
| 183 |
|
|
(define_insn "*iorqi3_real"
|
| 184 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
|
| 185 |
|
|
(ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
|
| 186 |
|
|
(match_operand:QI 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
|
| 187 |
|
|
]
|
| 188 |
|
|
"rl78_real_insns_ok ()"
|
| 189 |
|
|
"or\t%0, %2"
|
| 190 |
|
|
)
|
| 191 |
|
|
|
| 192 |
|
|
(define_insn "*xorqi3_real"
|
| 193 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=A,R,v")
|
| 194 |
|
|
(xor:QI (match_operand:QI 1 "general_operand" "%0,0,0")
|
| 195 |
|
|
(match_operand 2 "general_operand" "iRvWabWhbWh1Whl,A,i")))
|
| 196 |
|
|
]
|
| 197 |
|
|
"rl78_real_insns_ok ()"
|
| 198 |
|
|
"xor\t%0, %2"
|
| 199 |
|
|
)
|
| 200 |
|
|
|
| 201 |
|
|
;;---------- Shifts ------------------------
|
| 202 |
|
|
|
| 203 |
|
|
(define_insn "*ashlqi3_real"
|
| 204 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
|
| 205 |
|
|
(ashift:QI (match_operand:QI 1 "general_operand" "0,0,0")
|
| 206 |
|
|
(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
|
| 207 |
|
|
]
|
| 208 |
|
|
"rl78_real_insns_ok ()"
|
| 209 |
|
|
"@
|
| 210 |
|
|
shl\t%0, %u2
|
| 211 |
|
|
cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 212 |
|
|
inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
|
| 213 |
|
|
)
|
| 214 |
|
|
|
| 215 |
|
|
(define_insn "*ashlhi3_real"
|
| 216 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
|
| 217 |
|
|
(ashift:HI (match_operand:HI 1 "general_operand" "0,0,0")
|
| 218 |
|
|
(match_operand:QI 2 "general_operand" "P,bc,dehl")))
|
| 219 |
|
|
]
|
| 220 |
|
|
"rl78_real_insns_ok ()"
|
| 221 |
|
|
"@
|
| 222 |
|
|
shlw\t%0, %u2
|
| 223 |
|
|
cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 224 |
|
|
inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
|
| 225 |
|
|
)
|
| 226 |
|
|
|
| 227 |
|
|
;;----------
|
| 228 |
|
|
|
| 229 |
|
|
(define_insn "*ashrqi3_real"
|
| 230 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
|
| 231 |
|
|
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
|
| 232 |
|
|
(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
|
| 233 |
|
|
]
|
| 234 |
|
|
"rl78_real_insns_ok ()"
|
| 235 |
|
|
"@
|
| 236 |
|
|
sar\t%0, %u2
|
| 237 |
|
|
cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 238 |
|
|
inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
|
| 239 |
|
|
)
|
| 240 |
|
|
|
| 241 |
|
|
(define_insn "*ashrhi3_real"
|
| 242 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
|
| 243 |
|
|
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
|
| 244 |
|
|
(match_operand:QI 2 "general_operand" "P,bc,dehl")))
|
| 245 |
|
|
]
|
| 246 |
|
|
"rl78_real_insns_ok ()"
|
| 247 |
|
|
"@
|
| 248 |
|
|
sarw\t%0, %u2
|
| 249 |
|
|
cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 250 |
|
|
inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
|
| 251 |
|
|
)
|
| 252 |
|
|
|
| 253 |
|
|
;;----------
|
| 254 |
|
|
|
| 255 |
|
|
(define_insn "*lshrqi3_real"
|
| 256 |
|
|
[(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
|
| 257 |
|
|
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
|
| 258 |
|
|
(match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
|
| 259 |
|
|
]
|
| 260 |
|
|
"rl78_real_insns_ok ()"
|
| 261 |
|
|
"@
|
| 262 |
|
|
shr\t%0, %u2
|
| 263 |
|
|
cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 264 |
|
|
inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
|
| 265 |
|
|
)
|
| 266 |
|
|
|
| 267 |
|
|
(define_insn "*lshrhi3_real"
|
| 268 |
|
|
[(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
|
| 269 |
|
|
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
|
| 270 |
|
|
(match_operand:QI 2 "general_operand" "P,bc,dehl")))
|
| 271 |
|
|
]
|
| 272 |
|
|
"rl78_real_insns_ok ()"
|
| 273 |
|
|
"@
|
| 274 |
|
|
shrw\t%0, %u2
|
| 275 |
|
|
cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
|
| 276 |
|
|
inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
|
| 277 |
|
|
)
|
| 278 |
|
|
|
| 279 |
|
|
;;---------- Branching ------------------------
|
| 280 |
|
|
|
| 281 |
|
|
(define_insn "*indirect_jump_real"
|
| 282 |
|
|
[(set (pc)
|
| 283 |
|
|
(match_operand:HI 0 "nonimmediate_operand" "A"))]
|
| 284 |
|
|
"rl78_real_insns_ok ()"
|
| 285 |
|
|
"br\t%0"
|
| 286 |
|
|
)
|
| 287 |
|
|
|
| 288 |
|
|
(define_insn "jump"
|
| 289 |
|
|
[(set (pc)
|
| 290 |
|
|
(label_ref (match_operand 0 "" "")))]
|
| 291 |
|
|
""
|
| 292 |
|
|
;; $rel8, $!rel16, !abs16, !!abs20
|
| 293 |
|
|
"br\t!!%0"
|
| 294 |
|
|
)
|
| 295 |
|
|
|
| 296 |
|
|
(define_insn "*call_real"
|
| 297 |
|
|
[(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
|
| 298 |
|
|
(match_operand 1 "" ""))]
|
| 299 |
|
|
"rl78_real_insns_ok ()"
|
| 300 |
|
|
"@
|
| 301 |
|
|
call\t!!%A0
|
| 302 |
|
|
call\t%A0"
|
| 303 |
|
|
)
|
| 304 |
|
|
|
| 305 |
|
|
(define_insn "*call_value_real"
|
| 306 |
|
|
[(set (match_operand 0 "register_operand" "=v,v")
|
| 307 |
|
|
(call (match_operand:HI 1 "memory_operand" "Wab,Wca")
|
| 308 |
|
|
(match_operand 2 "" "")))]
|
| 309 |
|
|
"rl78_real_insns_ok ()"
|
| 310 |
|
|
"@
|
| 311 |
|
|
call\t!!%A1
|
| 312 |
|
|
call\t%A1"
|
| 313 |
|
|
)
|
| 314 |
|
|
|
| 315 |
|
|
(define_insn "*cbranchqi4_real"
|
| 316 |
|
|
[(set (pc) (if_then_else
|
| 317 |
|
|
(match_operator 0 "rl78_cmp_operator_real"
|
| 318 |
|
|
[(match_operand:QI 1 "general_operand" "Wabvaxbc,a, v,bcdehl")
|
| 319 |
|
|
(match_operand:QI 2 "general_operand" "M, irWhlWh1Whb,i,a")])
|
| 320 |
|
|
(label_ref (match_operand 3 "" ""))
|
| 321 |
|
|
(pc)))]
|
| 322 |
|
|
"rl78_real_insns_ok ()"
|
| 323 |
|
|
"@
|
| 324 |
|
|
cmp0\t%1 \;sk%c0 \;br\t!!%3
|
| 325 |
|
|
cmp\t%1, %2 \;sk%c0 \;br\t!!%3
|
| 326 |
|
|
cmp\t%1, %2 \;sk%c0 \;br\t!!%3
|
| 327 |
|
|
cmp\t%1, %2 \;sk%c0 \;br\t!!%3"
|
| 328 |
|
|
)
|
| 329 |
|
|
|
| 330 |
|
|
(define_insn "*cbranchhi4_real"
|
| 331 |
|
|
[(set (pc) (if_then_else
|
| 332 |
|
|
(match_operator 0 "rl78_cmp_operator_real"
|
| 333 |
|
|
[(match_operand:HI 1 "general_operand" "A")
|
| 334 |
|
|
(match_operand:HI 2 "general_operand" "iBDTWhlWh1")])
|
| 335 |
|
|
(label_ref (match_operand 3 "" ""))
|
| 336 |
|
|
(pc)))]
|
| 337 |
|
|
"rl78_real_insns_ok ()"
|
| 338 |
|
|
"cmpw\t%1, %2 \;sk%c0 \;br\t!!%3"
|
| 339 |
|
|
)
|
