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1 709 jeremybenn
;;  Machine Description for Renesas RL78 processors
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;;  Copyright (C) 2011 Free Software Foundation, Inc.
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;;  Contributed by Red Hat.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; In this MD file, we define those insn patterns that involve
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;; registers, where such registers are virtual until allocated to a
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;; physical register.  All of these insns need to be conditional on
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;; rl78_virt_insns_ok () being true.
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;; This tells the physical register allocator what method to use to
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;; allocate registers.  Basically, this defines the template of the
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;; instruction - op1 is of the form "a = op(b)", op2 is "a = b op c"
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;; etc.
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(define_attr "valloc" "op1,op2,ro1,cmp,umul,macax"
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  (const_string "op2"))
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;;---------- Moving ------------------------
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(define_insn "*movqi_virt"
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  [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,Wfr")
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        (match_operand    1 "general_operand" "vInt8JY,Wfr,vInt8J"))]
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  "rl78_virt_insns_ok ()"
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  "v.mov %0, %1"
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  [(set_attr "valloc" "op1")]
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)
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(define_insn "*movhi_virt"
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  [(set (match_operand:HI 0 "nonimmediate_operand" "=vYS,v,Wfr")
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        (match_operand:HI 1 "general_operand" "viYS,Wfr,v"))]
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  "rl78_virt_insns_ok ()"
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  "v.movw %0, %1"
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  [(set_attr "valloc" "op1")]
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)
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;;---------- Conversions ------------------------
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(define_insn "*zero_extendqihi2_virt"
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  [(set (match_operand:HI                 0 "rl78_nonfar_nonimm_operand" "=vm")
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        (zero_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
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  "rl78_virt_insns_ok ()"
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  "v.zero_extend\t%0, %1"
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  [(set_attr "valloc" "op1")]
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  )
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(define_insn "*extendqihi2_virt"
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  [(set (match_operand:HI                 0 "rl78_nonfar_nonimm_operand" "=vm")
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        (sign_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
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  "rl78_virt_insns_ok ()"
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  "v.sign_extend\t%0, %1"
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  [(set_attr "valloc" "op1")]
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  )
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;;---------- Arithmetic ------------------------
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(define_insn "*add3_virt"
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  [(set (match_operand:QHI           0 "rl78_nonfar_nonimm_operand" "=vY,S")
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        (plus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "viY,0")
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                  (match_operand:QHI 2 "general_operand" "vim,i")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.add\t%0, %1, %2"
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)
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(define_insn "*sub3_virt"
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  [(set (match_operand:QHI            0 "rl78_nonfar_nonimm_operand" "=vm,S")
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        (minus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim,0")
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                   (match_operand:QHI 2 "general_operand" "vim,i")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.sub\t%0, %1, %2"
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)
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(define_insn "*umulhi3_shift_virt"
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  [(set (match_operand:HI 0 "register_operand" "=vm")
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        (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "%vim")
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                 (match_operand:HI 2 "rl78_24_operand" "Ni")))]
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  "rl78_virt_insns_ok ()"
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  "v.mulu\t%0, %1, %2"
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  [(set_attr "valloc" "umul")]
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)
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(define_insn "*umulqihi3_virt"
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  [(set (match_operand:HI 0 "register_operand" "=vm")
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        (mult:HI (zero_extend:HI (match_operand:QI 1 "rl78_nonfar_operand" "%vim"))
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                 (zero_extend:HI (match_operand:QI 2 "general_operand" "vim"))))]
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  "rl78_virt_insns_ok ()"
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  "v.mulu\t%0, %2"
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  [(set_attr "valloc" "umul")]
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)
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(define_insn "*andqi3_virt"
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  [(set (match_operand:QI         0 "rl78_nonfar_nonimm_operand" "=vm")
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        (and:QI (match_operand:QI 1 "rl78_nonfar_operand" "vim")
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                (match_operand:QI 2 "general_operand" "vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.and\t%0, %1, %2"
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)
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(define_insn "*iorqi3_virt"
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  [(set (match_operand:QI         0 "rl78_nonfar_nonimm_operand" "=vm")
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        (ior:QI (match_operand:QI 1 "rl78_nonfar_operand" "vim")
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                (match_operand:QI 2 "general_operand" "vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.or\t%0, %1, %2"
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)
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(define_insn "*xor3_virt"
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  [(set (match_operand:QI         0 "rl78_nonfar_nonimm_operand" "=v,vm,m")
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        (xor:QI (match_operand:QI 1 "rl78_nonfar_operand" "%0,vm,vm")
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                (match_operand    2 "general_operand" "i,vm,vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.xor\t%0, %1, %2"
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)
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;;---------- Shifts ------------------------
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(define_insn "*ashl3_virt"
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  [(set (match_operand:QHI             0 "rl78_nonfar_nonimm_operand" "=vm")
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        (ashift:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
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                    (match_operand:QI  2 "general_operand" "vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.shl\t%0, %1, %2"
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)
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(define_insn "*ashr3_virt"
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  [(set (match_operand:QHI               0 "rl78_nonfar_nonimm_operand" "=vm")
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        (ashiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
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                      (match_operand:QI  2 "general_operand" "vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.sar\t%0, %1, %2"
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)
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(define_insn "*lshr3_virt"
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  [(set (match_operand:QHI               0 "rl78_nonfar_nonimm_operand" "=vm")
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        (lshiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
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                      (match_operand:QI  2 "general_operand" "vim")))
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   ]
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  "rl78_virt_insns_ok ()"
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  "v.shr\t%0, %1, %2"
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)
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;; really a macro
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(define_insn "*ashrsi3_virt"
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  [(set (match_operand:SI               0 "register_operand" "=v,v,v")
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        (ashiftrt:SI (match_operand:SI  1 "register_operand" "0,v,0")
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                      (match_operand:SI 2 "immediate_operand" "M,K,i")))
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   ]
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  ""
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  "@
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   ; ashrsi %0, 0
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   movw\tax,%H1\;sarw\tax,1\;movw\t%H0,ax\;mov\ta,%Q1\;rorc\ta,1\;mov\t%Q0,a\;mov\ta,%q1\;rorc\ta,1\;mov\t%q0,a
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   mov\tb,%2\;1:\;movw\tax,%H1\;sarw\tax,1\;movw\t%H0,ax\;mov\ta,%Q1\;rorc\ta,1\;mov\t%Q0,a\;mov\ta,%q1\;rorc\ta,1\;mov\t%q0,a\;dec\tb\;bnz $1b"
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  [(set_attr "valloc" "macax")]
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)
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;;---------- Branching ------------------------
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(define_insn "*indirect_jump_virt"
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  [(set (pc)
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        (match_operand:HI 0 "nonimmediate_operand" "vm"))]
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  "rl78_virt_insns_ok ()"
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  "v.br\t%0"
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  [(set_attr "valloc" "ro1")]
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)
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(define_insn "*call_virt"
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  [(call (match_operand:HI 0 "memory_operand" "Wab,Wcv")
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         (match_operand 1 "" ""))]
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  "rl78_virt_insns_ok ()"
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  "v.call\t%0"
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  [(set_attr "valloc" "ro1")]
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  )
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(define_insn "*call_value_virt"
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  [(set (match_operand 0 "register_operand" "=v,v")
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        (call (match_operand:HI 1 "memory_operand" "Wab,Wcv")
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              (match_operand 2 "" "")))]
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  "rl78_virt_insns_ok ()"
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  "v.call\t%1"
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  [(set_attr "valloc" "op1")]
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  )
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(define_insn "*cbranchqi4_virt"
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  [(set (pc) (if_then_else
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              (match_operator 0 "rl78_cmp_operator_real"
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                              [(match_operand:QI 1 "general_operand" "vim")
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                               (match_operand:QI 2 "general_operand" "vim")])
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              (label_ref (match_operand 3 "" ""))
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              (pc)))]
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  "rl78_virt_insns_ok ()"
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  "v.cmp\t%1, %2\\n\tv.b%c0\t%3"
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  [(set_attr "valloc" "cmp")]
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  )
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(define_insn "*cbranchhi4_virt"
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  [(set (pc) (if_then_else
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              (match_operator 0 "rl78_cmp_operator_real"
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                              [(match_operand:HI 1 "general_operand" "vim")
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                               (match_operand:HI 2 "general_operand" "vim")])
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              (label_ref (match_operand 3 "" ""))
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              (pc)))]
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  "rl78_virt_insns_ok ()"
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  "v.cmpw\t%1, %2\\n\tv.b%c0\t%3"
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  [(set_attr "valloc" "cmp")]
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  )
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;;---------- Peepholes ------------------------
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(define_peephole2
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  [(set (match_operand:QI 0 "" "")
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        (match_operand:QI 1 "" ""))
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   (set (match_operand:QI 2 "" "")
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        (match_operand:QI 3 "" ""))]
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  "rl78_peep_movhi_p (operands)"
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  [(set (match_dup 4)
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        (match_dup 5))]
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  "rl78_setup_peep_movhi (operands);"
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  )
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(define_peephole2
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  [(set (reg:QI A_REG)
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        (match_operand:QI 1 "" ""))
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   (set (match_operand:QI 0 "" "")
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        (reg:QI A_REG))
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   (set (reg:QI A_REG)
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        (match_operand:QI 3 "" ""))
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   (set (match_operand:QI 2 "" "")
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        (reg:QI A_REG))
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   ]
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  "rl78_peep_movhi_p (operands)"
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  [(set (reg:HI AX_REG)
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        (match_dup 5))
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   (set (match_dup 4)
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        (reg:HI AX_REG))
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   ]
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  "rl78_setup_peep_movhi (operands);"
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  )

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