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jeremybenn |
/* GCC backend definitions for the Renesas RL78 processor.
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Copyright (C) 2011 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
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#define RL78_MUL_RL78 (rl78_mul_type == MUL_RL78)
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#define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define ("__RL78__"); \
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builtin_assert ("cpu=RL78"); \
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if (RL78_MUL_RL78) \
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builtin_define ("__RL78_MUL_RL78__"); \
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if (RL78_MUL_G13) \
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builtin_define ("__RL78_MUL_G13__"); \
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} \
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while (0)
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
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#undef LIB_SPEC
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#define LIB_SPEC " \
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--start-group \
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-lc \
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-lsim \
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%{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
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--end-group \
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%{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
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"
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#ifdef IN_LIBGCC2
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/* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
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#define UNITS_PER_WORD 4
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/* We have a problem with libgcc2. It only defines two versions of
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each function, one for "int" and one for "long long". Ie it assumes
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that "sizeof (int) == sizeof (long)". For the RL78 this is not true
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and we need a third set of functions. We explicitly define
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LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
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to get the SI and DI versions from the libgcc2.c sources, and we
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provide our own set of HI functions, which is why this
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definition is surrounded by #ifndef..#endif. */
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#ifndef LIBGCC2_UNITS_PER_WORD
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#define LIBGCC2_UNITS_PER_WORD 4
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#endif
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#else
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/* Actual width of a word, in units (bytes). */
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#define UNITS_PER_WORD 1
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#endif
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#define SHORT_TYPE_SIZE 16
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#define INT_TYPE_SIZE 16
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#define LONG_TYPE_SIZE 32
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#define LONG_LONG_TYPE_SIZE 64
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 32 /*64*/
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#define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
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#define LIBGCC2_HAS_DF_MODE 1
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#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
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#define DEFAULT_SIGNED_CHAR 0
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#define STRICT_ALIGNMENT 1
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#define FUNCTION_BOUNDARY 8
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#define BIGGEST_ALIGNMENT 16
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#define STACK_BOUNDARY 16
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#define PARM_BOUNDARY 16
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#define STACK_GROWS_DOWNWARD 1
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#define FRAME_GROWS_DOWNWARD 1
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#define FIRST_PARM_OFFSET(FNDECL) 0
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#define MAX_REGS_PER_ADDRESS 1
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#define Pmode HImode
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#define POINTER_SIZE 16
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#undef SIZE_TYPE
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#define SIZE_TYPE "unsigned int"
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#undef PTRDIFF_TYPE
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#define PTRDIFF_TYPE "int"
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#undef WCHAR_TYPE
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#define WCHAR_TYPE "long int"
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#undef WCHAR_TYPE_SIZE
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#define WCHAR_TYPE_SIZE BITS_PER_WORD
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#define POINTERS_EXTEND_UNSIGNED 1
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#define FUNCTION_MODE HImode
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#define CASE_VECTOR_MODE Pmode
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#define WORD_REGISTER_OPERATIONS 0
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#define HAS_LONG_COND_BRANCH 0
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#define HAS_LONG_UNCOND_BRANCH 0
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#define MOVE_MAX 2
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#define STARTING_FRAME_OFFSET 0
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#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
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#define ADDR_SPACE_FAR 1
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#define HAVE_PRE_DECCREMENT 0
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#define HAVE_POST_INCREMENT 0
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#define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
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#define SLOW_BYTE_ACCESS 0
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#define STORE_FLAG_VALUE 1
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#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
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#define SHORT_IMMEDIATES_SIGN_EXTEND 0
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/* The RL78 has four register banks. Normal operation uses RB0 as
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real registers, RB1 and RB2 as "virtual" registers (because we know
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they'll be there, and not used as variables), and RB3 is reserved
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for interrupt handlers. The virtual registers are accessed as
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SADDRs:
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FFEE0-FFEE7 RB0
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FFEE8-FFEEF RB1
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FFEF0-FFEF7 RB2
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FFEF8-FFEFF RB3
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*/
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#define REGISTER_NAMES \
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{ \
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"x", "a", "c", "b", "e", "d", "l", "h", \
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
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"sp", "ap", "psw", "es", "cs" \
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}
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#define ADDITIONAL_REGISTER_NAMES \
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{ \
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{ "ax", 0 }, \
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{ "bc", 2 }, \
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{ "de", 4 }, \
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{ "hl", 6 }, \
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{ "rp0", 0 }, \
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{ "rp1", 2 }, \
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{ "rp2", 4 }, \
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{ "rp3", 6 }, \
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{ "r0", 0 }, \
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{ "r1", 1 }, \
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{ "r2", 2 }, \
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{ "r3", 3 }, \
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{ "r4", 4 }, \
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{ "r5", 5 }, \
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{ "r6", 6 }, \
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{ "r7", 7 }, \
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}
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enum reg_class
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{
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NO_REGS, /* No registers in set. */
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XREG,
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AREG,
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AXREG,
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CREG,
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BREG,
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BCREG,
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EREG,
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DREG,
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DEREG,
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LREG,
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HREG,
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HLREG,
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IDX_REGS,
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QI_REGS,
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SPREG,
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R8W_REGS,
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R10W_REGS,
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INT_REGS,
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V_REGS, /* Virtual registers. */
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GR_REGS, /* Integer registers. */
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PSWREG,
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ALL_REGS, /* All registers. */
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LIM_REG_CLASSES /* Max value + 1. */
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};
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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"XREG", \
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"AREG", \
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"AXREG", \
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"CREG", \
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"BREG", \
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"BCREG", \
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"EREG", \
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"DREG", \
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"DEREG", \
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"LREG", \
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"HREG", \
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"HLREG", \
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"IDX_REGS", \
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"QI_REGS", \
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"SPREG", \
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"R8W_REGS", \
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"R10W_REGS", \
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"INT_REGS", \
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"V_REGS", \
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"GR_REGS", \
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"PSWREG", \
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"ALL_REGS" \
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}
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000 }, /* No registers, */ \
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{ 0x00000001, 0x00000000 }, \
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{ 0x00000002, 0x00000000 }, \
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{ 0x00000003, 0x00000000 }, \
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{ 0x00000004, 0x00000000 }, \
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{ 0x00000008, 0x00000000 }, \
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{ 0x0000000c, 0x00000000 }, \
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{ 0x00000010, 0x00000000 }, \
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{ 0x00000020, 0x00000000 }, \
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{ 0x00000030, 0x00000000 }, \
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{ 0x00000040, 0x00000000 }, \
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{ 0x00000080, 0x00000000 }, \
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{ 0x000000c0, 0x00000000 }, \
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{ 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
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{ 0x000000ff, 0x00000000 }, /* all real registers. */ \
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{ 0x00000000, 0x00000001 }, /* SP */ \
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{ 0x00000300, 0x00000000 }, /* R8 - HImode */ \
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{ 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
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{ 0xff000000, 0x00000000 }, /* INT - HImode */ \
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{ 0x007fff00, 0x00000000 }, /* Virtual registers. */ \
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{ 0xff7fffff, 0x00000002 }, /* General registers. */ \
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{ 0x04000000, 0x00000004 }, /* PSW. */ \
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{ 0xff7fffff, 0x0000001f } /* All registers. */ \
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}
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#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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#define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
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+ UNITS_PER_WORD - 1) \
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/ UNITS_PER_WORD)
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| 267 |
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#define GENERAL_REGS GR_REGS
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#define BASE_REG_CLASS V_REGS
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#define INDEX_REG_CLASS V_REGS
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| 270 |
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| 271 |
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#define FIRST_PSEUDO_REGISTER 37
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| 273 |
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#define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
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| 274 |
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? GR_REGS : NO_REGS)
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| 275 |
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| 276 |
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#define FRAME_POINTER_REGNUM 22
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| 277 |
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#define STACK_POINTER_REGNUM 32
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| 278 |
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#define ARG_POINTER_REGNUM 33
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| 279 |
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#define CC_REGNUM 34
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| 280 |
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#define FUNC_RETURN_REGNUM 8
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| 281 |
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#define STATIC_CHAIN_REGNUM 14
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| 282 |
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| 283 |
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/* Trampolines are implemented with a separate data stack. The memory
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| 284 |
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on stack only holds the function pointer for the chosen stub.
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| 285 |
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*/
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| 286 |
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| 287 |
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#define TRAMPOLINE_SIZE 4
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| 288 |
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#define TRAMPOLINE_ALIGNMENT 16
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| 289 |
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| 290 |
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#define ELIMINABLE_REGS \
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| 291 |
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{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
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| 292 |
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{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
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| 293 |
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{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
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| 294 |
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| 295 |
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#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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| 296 |
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(OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
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| 297 |
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| 298 |
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| 299 |
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#define FUNCTION_ARG_REGNO_P(N) 0
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| 300 |
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#define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
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| 301 |
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#define DEFAULT_PCC_STRUCT_RETURN 0
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| 302 |
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| 303 |
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#define FIXED_REGISTERS \
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| 304 |
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{ \
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| 305 |
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1,1,1,1, 1,1,1,1, \
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0,0,0,0, 0,0,0,0, \
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0,0,0,0, 0,0,1,1, \
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1,1,1,1, 1,1,1,1, \
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0, 1, 0, 1, 1 \
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}
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| 311 |
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| 312 |
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#define CALL_USED_REGISTERS \
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| 313 |
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{ \
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| 314 |
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1,1,1,1, 1,1,1,1, \
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| 315 |
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1,1,1,1, 1,1,1,1, \
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0,0,0,0, 0,0,1,1, \
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1,1,1,1, 1,1,1,1, \
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0, 1, 1, 1, 1 \
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}
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| 320 |
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| 321 |
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#define LIBCALL_VALUE(MODE) \
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| 322 |
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gen_rtx_REG ((MODE), \
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| 323 |
|
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FUNC_RETURN_REGNUM)
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| 324 |
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| 325 |
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/* Order of allocation of registers. */
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| 326 |
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| 327 |
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#define REG_ALLOC_ORDER \
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| 328 |
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{ 8, 9, 10, 11, 12, 13, 14, 15, \
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| 329 |
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16, 17, 18, 19, 20, 21, 22, 23, \
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| 330 |
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0, 1, 6, 7, 2, 3, 4, 5, \
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24, 25, 26, 27, 28, 29, 30, 31, \
|
| 332 |
|
|
32, 33, 34 \
|
| 333 |
|
|
}
|
| 334 |
|
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|
| 335 |
|
|
#define REGNO_IN_RANGE(REGNO, MIN, MAX) \
|
| 336 |
|
|
(IN_RANGE ((REGNO), (MIN), (MAX)) \
|
| 337 |
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|
|| (reg_renumber != NULL \
|
| 338 |
|
|
&& reg_renumber[(REGNO)] >= (MIN) \
|
| 339 |
|
|
&& reg_renumber[(REGNO)] <= (MAX)))
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| 340 |
|
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|
| 341 |
|
|
#ifdef REG_OK_STRICT
|
| 342 |
|
|
#define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 23)
|
| 343 |
|
|
#else
|
| 344 |
|
|
#define REGNO_OK_FOR_BASE_P(regno) 1
|
| 345 |
|
|
#endif
|
| 346 |
|
|
|
| 347 |
|
|
#define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
|
| 348 |
|
|
|
| 349 |
|
|
#define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
|
| 350 |
|
|
rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
|
| 351 |
|
|
|
| 352 |
|
|
#define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
|
| 353 |
|
|
rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
|
| 354 |
|
|
|
| 355 |
|
|
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
|
| 356 |
|
|
((COUNT) == 0 \
|
| 357 |
|
|
? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
|
| 358 |
|
|
: NULL_RTX)
|
| 359 |
|
|
|
| 360 |
|
|
#define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
|
| 361 |
|
|
|
| 362 |
|
|
#define ACCUMULATE_OUTGOING_ARGS 1
|
| 363 |
|
|
|
| 364 |
|
|
typedef unsigned int CUMULATIVE_ARGS;
|
| 365 |
|
|
|
| 366 |
|
|
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
| 367 |
|
|
(CUM) = 0
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
/* FIXME */
|
| 371 |
|
|
#define NO_PROFILE_COUNTERS 1
|
| 372 |
|
|
#define PROFILE_BEFORE_PROLOGUE 1
|
| 373 |
|
|
|
| 374 |
|
|
#define FUNCTION_PROFILER(FILE, LABELNO) \
|
| 375 |
|
|
fprintf (FILE, "\tbsr\t__mcount\n");
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
| 379 |
|
|
rl78_hard_regno_nregs (REGNO, MODE)
|
| 380 |
|
|
|
| 381 |
|
|
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
| 382 |
|
|
rl78_hard_regno_mode_ok (REGNO, MODE)
|
| 383 |
|
|
|
| 384 |
|
|
#define MODES_TIEABLE_P(MODE1, MODE2) \
|
| 385 |
|
|
( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|
| 386 |
|
|
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
|
| 387 |
|
|
== ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
|
| 388 |
|
|
|| GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
|
| 389 |
|
|
|
| 390 |
|
|
|
| 391 |
|
|
#define TEXT_SECTION_ASM_OP ".text"
|
| 392 |
|
|
#define DATA_SECTION_ASM_OP ".data"
|
| 393 |
|
|
#define BSS_SECTION_ASM_OP ".bss"
|
| 394 |
|
|
#define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
|
| 395 |
|
|
#define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
|
| 396 |
|
|
|
| 397 |
|
|
#define ASM_COMMENT_START " ;"
|
| 398 |
|
|
#define ASM_APP_ON ""
|
| 399 |
|
|
#define ASM_APP_OFF ""
|
| 400 |
|
|
#define LOCAL_LABEL_PREFIX ".L"
|
| 401 |
|
|
#undef USER_LABEL_PREFIX
|
| 402 |
|
|
#define USER_LABEL_PREFIX "_"
|
| 403 |
|
|
|
| 404 |
|
|
#define GLOBAL_ASM_OP "\t.global\t"
|
| 405 |
|
|
|
| 406 |
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
| 407 |
|
|
fprintf (FILE, "\t.long .L%d\n", VALUE)
|
| 408 |
|
|
|
| 409 |
|
|
/* This is how to output an element of a case-vector that is relative.
|
| 410 |
|
|
Note: The local label referenced by the "3b" below is emitted by
|
| 411 |
|
|
the tablejump insn. */
|
| 412 |
|
|
|
| 413 |
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
| 414 |
|
|
fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
#define ASM_OUTPUT_ALIGN(STREAM, LOG) \
|
| 418 |
|
|
do \
|
| 419 |
|
|
{ \
|
| 420 |
|
|
if ((LOG) == 0) \
|
| 421 |
|
|
break; \
|
| 422 |
|
|
fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
|
| 423 |
|
|
} \
|
| 424 |
|
|
while (0)
|
| 425 |
|
|
|
| 426 |
|
|
/* For PIC put jump tables into the text section so that the offsets that
|
| 427 |
|
|
they contain are always computed between two same-section symbols. */
|
| 428 |
|
|
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
|
| 429 |
|
|
|
| 430 |
|
|
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
|
| 431 |
|
|
#define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
|
| 432 |
|
|
|
| 433 |
|
|
/* Like REG_P except that this macro is true for SET expressions. */
|
| 434 |
|
|
#define SET_P(rtl) (GET_CODE (rtl) == SET)
|
| 435 |
|
|
|
| 436 |
|
|
#undef PREFERRED_DEBUGGING_TYPE
|
| 437 |
|
|
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
| 438 |
|
|
|
| 439 |
|
|
#undef DWARF2_ADDR_SIZE
|
| 440 |
|
|
#define DWARF2_ADDR_SIZE 4
|
| 441 |
|
|
|
| 442 |
|
|
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
| 443 |
|
|
|
| 444 |
|
|
#define EXIT_IGNORE_STACK 0
|
| 445 |
|
|
#define INCOMING_FRAME_SP_OFFSET 4
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
#define BRANCH_COST(SPEED,PREDICT) 1
|
| 449 |
|
|
#define REGISTER_MOVE_COST(MODE,FROM,TO) 2
|
| 450 |
|
|
|
| 451 |
|
|
#define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
|
| 452 |
|
|
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
|
| 453 |
|
|
|
| 454 |
|
|
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
|
| 455 |
|
|
|
| 456 |
|
|
/* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
|
| 457 |
|
|
#define DWARF2_UNWIND_INFO 0
|
| 458 |
|
|
/*#define DONT_USE_BUILTIN_SETJMP 1*/
|
| 459 |
|
|
#undef DONT_USE_BUILTIN_SETJMP
|
| 460 |
|
|
#define JMP_BUF_SIZE (8*3+8)
|
| 461 |
|
|
|
| 462 |
|
|
#define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
|
