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jeremybenn |
;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
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;; and PowerPC 630 processors.
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;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
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(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
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(define_cpu_unit "fpu_6xx" "ppc6xxfp")
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(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
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(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
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;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
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;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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;; MCIU used for imul/idiv and moves from/to spr
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;; LSU 2 stage pipelined
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;; FPU 3 stage pipelined
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;; Max issue 4 insns/clock cycle
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;; PPC604e is PPC604 with larger caches and a CRU. In the 604
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;; the CR logical operations are handled in the BPU.
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;; In the 604e, the CRU shares bus with BPU so only one condition
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;; register or branch insn can be issued per clock. Not modelled.
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;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
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;; Max issue 4 insns/clock cycle
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;; Out-of-order execution, in-order completion
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;; No following instruction can dispatch in the same cycle as a branch
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;; instruction. Not modelled. This is no problem if RCSP is not
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;; enabled since the scheduler stops a schedule when it gets to a branch.
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;; Four insns can be dispatched per cycle.
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(define_insn_reservation "ppc604-load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"lsu_6xx")
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(define_insn_reservation "ppc604-fpload" 3
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"lsu_6xx")
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(define_insn_reservation "ppc604-store" 3
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(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"lsu_6xx")
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(define_insn_reservation "ppc604-llsc" 3
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(and (eq_attr "type" "load_l,store_c")
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(eq_attr "cpu" "ppc604,ppc604e"))
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"lsu_6xx")
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(define_insn_reservation "ppc630-llsc" 4
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(and (eq_attr "type" "load_l,store_c")
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(eq_attr "cpu" "ppc620,ppc630"))
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"lsu_6xx")
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(define_insn_reservation "ppc604-integer" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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var_shift_rotate,cntlz,exts,isel")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"iu1_6xx|iu2_6xx")
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(define_insn_reservation "ppc604-two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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(define_insn_reservation "ppc604-three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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(define_insn_reservation "ppc604-imul" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppc604"))
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"mciu_6xx*2")
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(define_insn_reservation "ppc604e-imul" 2
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppc604e"))
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"mciu_6xx")
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(define_insn_reservation "ppc620-imul" 5
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(and (eq_attr "type" "imul,imul_compare")
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(eq_attr "cpu" "ppc620,ppc630"))
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"mciu_6xx*3")
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(define_insn_reservation "ppc620-imul2" 4
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(and (eq_attr "type" "imul2")
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(eq_attr "cpu" "ppc620,ppc630"))
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"mciu_6xx*3")
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(define_insn_reservation "ppc620-imul3" 3
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(and (eq_attr "type" "imul3")
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(eq_attr "cpu" "ppc620,ppc630"))
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"mciu_6xx*3")
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(define_insn_reservation "ppc620-lmul" 7
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(and (eq_attr "type" "lmul,lmul_compare")
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(eq_attr "cpu" "ppc620,ppc630"))
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"mciu_6xx*5")
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(define_insn_reservation "ppc604-idiv" 20
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc604,ppc604e"))
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"mciu_6xx*19")
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(define_insn_reservation "ppc620-idiv" 37
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc620"))
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"mciu_6xx*36")
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(define_insn_reservation "ppc630-idiv" 21
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc630"))
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"mciu_6xx*20")
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(define_insn_reservation "ppc620-ldiv" 37
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(and (eq_attr "type" "ldiv")
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(eq_attr "cpu" "ppc620,ppc630"))
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"mciu_6xx*36")
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(define_insn_reservation "ppc604-compare" 3
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(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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var_delayed_compare")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"(iu1_6xx|iu2_6xx)")
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; FPU PPC604{,e},PPC620
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(define_insn_reservation "ppc604-fpcompare" 5
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"fpu_6xx")
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(define_insn_reservation "ppc604-fp" 3
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"fpu_6xx")
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(define_insn_reservation "ppc604-dmul" 3
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"fpu_6xx")
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; Divides are not pipelined
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(define_insn_reservation "ppc604-sdiv" 18
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"fpu_6xx*18")
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(define_insn_reservation "ppc604-ddiv" 32
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"fpu_6xx*32")
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(define_insn_reservation "ppc620-ssqrt" 31
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(and (eq_attr "type" "ssqrt")
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(eq_attr "cpu" "ppc620"))
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"fpu_6xx*31")
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(define_insn_reservation "ppc620-dsqrt" 31
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(and (eq_attr "type" "dsqrt")
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(eq_attr "cpu" "ppc620"))
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"fpu_6xx*31")
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; 2xFPU PPC630
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(define_insn_reservation "ppc630-fpcompare" 5
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx|fpu2_6xx")
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(define_insn_reservation "ppc630-fp" 3
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(and (eq_attr "type" "fp,dmul")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx|fpu2_6xx")
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(define_insn_reservation "ppc630-sdiv" 17
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx*17|fpu2_6xx*17")
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(define_insn_reservation "ppc630-ddiv" 21
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx*21|fpu2_6xx*21")
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(define_insn_reservation "ppc630-ssqrt" 18
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(and (eq_attr "type" "ssqrt")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx*18|fpu2_6xx*18")
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(define_insn_reservation "ppc630-dsqrt" 25
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(and (eq_attr "type" "dsqrt")
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(eq_attr "cpu" "ppc630"))
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"fpu1_6xx*25|fpu2_6xx*25")
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(define_insn_reservation "ppc604-mfcr" 3
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"mciu_6xx")
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(define_insn_reservation "ppc604-mtcr" 2
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"iu1_6xx|iu2_6xx")
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(define_insn_reservation "ppc604-crlogical" 2
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc604"))
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"bpu_6xx")
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(define_insn_reservation "ppc604e-crlogical" 2
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppc604e,ppc620,ppc630"))
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"cru_6xx")
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(define_insn_reservation "ppc604-mtjmpr" 2
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"mciu_6xx")
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(define_insn_reservation "ppc604-mfjmpr" 3
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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"mciu_6xx")
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(define_insn_reservation "ppc630-mfjmpr" 2
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(and (eq_attr "type" "mfjmpr")
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(eq_attr "cpu" "ppc630"))
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"mciu_6xx")
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(define_insn_reservation "ppc604-jmpreg" 1
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(and (eq_attr "type" "jmpreg,branch")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"bpu_6xx")
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(define_insn_reservation "ppc604-isync" 0
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(and (eq_attr "type" "isync")
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(eq_attr "cpu" "ppc604,ppc604e"))
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"bpu_6xx")
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(define_insn_reservation "ppc630-isync" 6
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(and (eq_attr "type" "isync")
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(eq_attr "cpu" "ppc620,ppc630"))
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"bpu_6xx")
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(define_insn_reservation "ppc604-sync" 35
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(and (eq_attr "type" "sync")
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(eq_attr "cpu" "ppc604,ppc604e"))
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"lsu_6xx")
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(define_insn_reservation "ppc630-sync" 26
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(and (eq_attr "type" "sync")
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(eq_attr "cpu" "ppc620,ppc630"))
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"lsu_6xx")
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