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jeremybenn |
;; Pipeline description for Motorola PowerPC e300c3 core.
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;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
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(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
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;; We don't simulate general issue queue (GIC). If we have SU insn
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;; and then SU1 insn, they can not be issued on the same cycle
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;; (although SU1 insn and then SU insn can be issued) because the SU
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;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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;; multipass insn scheduling will find the situation and issue the SU1
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;; insn and then the SU insn.
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(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
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;; We could describe completion buffers slots in combination with the
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;; retirement units and the order of completion but the result
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;; automaton would behave in the same way because we can not describe
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;; real latency time with taking in order completion into account.
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;; Actually we could define the real latency time by querying reserved
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;; automaton units but the current scheduler uses latency time before
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;; issuing insns and making any reservations.
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;;
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;; So our description is aimed to achieve a insn schedule in which the
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;; insns would not wait in the completion buffer.
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(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
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;; Branch unit:
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(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
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;; IU:
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(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
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;; IU: This used to describe non-pipelined division.
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(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
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;; SRU:
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(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
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;; Here we simplified LSU unit description not describing the stages.
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(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
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;; FPU:
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(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
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;; The following units are used to make automata deterministic
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(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
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(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
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(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
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(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
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(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
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(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
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(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
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;; Some useful abbreviations.
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(define_reservation "ppce300c3_decode"
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"ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
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(define_reservation "ppce300c3_issue"
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"ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
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(define_reservation "ppce300c3_retire"
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"ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
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(define_reservation "ppce300c3_iu_stage0"
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"ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
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;; Compares can be executed either one of the IU or SRU
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(define_insn_reservation "ppce300c3_cmp" 1
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(and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
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+ppce300c3_retire")
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;; Other one cycle IU insns
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(define_insn_reservation "ppce300c3_iu" 1
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(and (eq_attr "type" "integer,insert_word,isel")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
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;; Branch. Actually this latency time is not used by the scheduler.
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(define_insn_reservation "ppce300c3_branch" 1
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(and (eq_attr "type" "jmpreg,branch")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
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;; Multiply is non-pipelined but can be executed in any IU
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(define_insn_reservation "ppce300c3_multiply" 2
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
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ppce300c3_iu_stage0+ppce300c3_retire")
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;; Divide. We use the average latency time here. We omit reserving a
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;; retire unit because of the result automata will be huge.
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(define_insn_reservation "ppce300c3_divide" 20
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(and (eq_attr "type" "idiv")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
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ppce300c3_mu_div*19")
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;; CR logical
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(define_insn_reservation "ppce300c3_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mfcr
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(define_insn_reservation "ppce300c3_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mtcrf
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(define_insn_reservation "ppce300c3_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Mtjmpr
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(define_insn_reservation "ppce300c3_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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;; Float point instructions
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(define_insn_reservation "ppce300c3_fpcompare" 3
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fp" 3
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_dmul" 4
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
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; Divides are not pipelined
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(define_insn_reservation "ppce300c3_sdiv" 18
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
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(define_insn_reservation "ppce300c3_ddiv" 33
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
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;; Loads
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(define_insn_reservation "ppce300c3_load" 2
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fpload" 2
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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;; Stores.
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(define_insn_reservation "ppce300c3_store" 2
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(and (eq_attr "type" "store,store_ux,store_u")
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(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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(define_insn_reservation "ppce300c3_fpstore" 2
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(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppce300c3"))
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"ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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