OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rs6000/] [e500.h] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
/* Enable E500 support.
2
   Copyright (C) 2003, 2004, 2006, 2007, 2008, 2009, 2010 Free Software
3
   Foundation, Inc.
4
   This file is part of GCC.
5
 
6
   GCC is free software; you can redistribute it and/or modify it
7
   under the terms of the GNU General Public License as published
8
   by the Free Software Foundation; either version 3, or (at your
9
   option) any later version.
10
 
11
   GCC is distributed in the hope that it will be useful, but WITHOUT
12
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14
   License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with GCC; see the file COPYING3.  If not see
18
   <http://www.gnu.org/licenses/>.  */
19
 
20
#undef TARGET_SPE_ABI
21
#undef TARGET_SPE
22
#undef TARGET_E500
23
#undef TARGET_FPRS
24
#undef TARGET_E500_SINGLE
25
#undef TARGET_E500_DOUBLE
26
#undef CHECK_E500_OPTIONS
27
 
28
#define TARGET_SPE_ABI rs6000_spe_abi
29
#define TARGET_SPE rs6000_spe
30
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
31
#define TARGET_FPRS (rs6000_float_gprs == 0)
32
#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
33
#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
34
#define CHECK_E500_OPTIONS                                              \
35
  do {                                                                  \
36
    if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI                     \
37
        || TARGET_E500_SINGLE || TARGET_E500_DOUBLE)                    \
38
      {                                                                 \
39
        if (TARGET_ALTIVEC)                                             \
40
          error ("AltiVec and E500 instructions cannot coexist");       \
41
        if (TARGET_VSX)                                                 \
42
          error ("VSX and E500 instructions cannot coexist");           \
43
        if (TARGET_64BIT)                                               \
44
          error ("64-bit E500 not supported");                          \
45
        if (TARGET_HARD_FLOAT && TARGET_FPRS)                           \
46
          error ("E500 and FPRs not supported");                        \
47
      }                                                                 \
48
  } while (0)
49
 
50
/* Override rs6000.h definition.  */
51
#undef HARD_REGNO_CALLER_SAVE_MODE
52
/* When setting up caller-save slots (MODE == VOIDmode) ensure we
53
   allocate space for DFmode.  Save gprs in the correct mode too.  */
54
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
55
  (TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode)       \
56
   ? DFmode                                                             \
57
   : choose_hard_reg_mode ((REGNO), (NREGS), false))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.