OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rs6000/] [power5.md] - Blame information for rev 718

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; Scheduling description for IBM POWER5 processor.
2 
;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
3 
;;
4 
;; This file is part of GCC.
5 
;;
6 
;; GCC is free software; you can redistribute it and/or modify it
7 
;; under the terms of the GNU General Public License as published
8 
;; by the Free Software Foundation; either version 3, or (at your
9 
;; option) any later version.
10 
;;
11 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
12 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14 
;; License for more details.
15 
;;
16 
;; You should have received a copy of the GNU General Public License
17 
;; along with GCC; see the file COPYING3.  If not see
18 
;; .
19 
 
20 
;; Sources: IBM Red Book and White Paper on POWER5
21 
 
22 
;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
23 
;; Instructions that update more than one register get broken into two
24 
;; (split) or more internal ops.  The chip can issue up to 5
25 
;; internal ops per cycle.
26 
 
27 
(define_automaton "power5iu,power5fpu,power5misc")
28 
 
29 
(define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
30 
(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
31 
(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
32 
(define_cpu_unit "bpu_power5,cru_power5" "power5misc")
33 
(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
34 
                 "power5misc")
35 
 
36 
(define_reservation "lsq_power5"
37 
                    "(du1_power5,lsu1_power5)\
38 
                    |(du2_power5,lsu2_power5)\
39 
                    |(du3_power5,lsu2_power5)\
40 
                    |(du4_power5,lsu1_power5)")
41 
 
42 
(define_reservation "iq_power5"
43 
                    "(du1_power5|du2_power5|du3_power5|du4_power5),\
44 
                     (iu1_power5|iu2_power5)")
45 
 
46 
(define_reservation "fpq_power5"
47 
                    "(du1_power5|du2_power5|du3_power5|du4_power5),\
48 
                     (fpu1_power5|fpu2_power5)")
49 
 
50 
; Dispatch slots are allocated in order conforming to program order.
51 
(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
52 
(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
53 
(absence_set "du3_power5" "du4_power5,du5_power5")
54 
(absence_set "du4_power5" "du5_power5")
55 
 
56 
 
57 
; Load/store
58 
(define_insn_reservation "power5-load" 4 ; 3
59 
  (and (eq_attr "type" "load")
60 
       (eq_attr "cpu" "power5"))
61 
  "lsq_power5")
62 
 
63 
(define_insn_reservation "power5-load-ext" 5
64 
  (and (eq_attr "type" "load_ext")
65 
       (eq_attr "cpu" "power5"))
66 
  "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
67 
 
68 
(define_insn_reservation "power5-load-ext-update" 5
69 
  (and (eq_attr "type" "load_ext_u")
70 
       (eq_attr "cpu" "power5"))
71 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
72 
   lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
73 
 
74 
(define_insn_reservation "power5-load-ext-update-indexed" 5
75 
  (and (eq_attr "type" "load_ext_ux")
76 
       (eq_attr "cpu" "power5"))
77 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
78 
   iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
79 
 
80 
(define_insn_reservation "power5-load-update-indexed" 3
81 
  (and (eq_attr "type" "load_ux")
82 
       (eq_attr "cpu" "power5"))
83 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
84 
   iu1_power5,lsu2_power5+iu2_power5")
85 
 
86 
(define_insn_reservation "power5-load-update" 4 ; 3
87 
  (and (eq_attr "type" "load_u")
88 
       (eq_attr "cpu" "power5"))
89 
  "du1_power5+du2_power5,lsu1_power5+iu2_power5")
90 
 
91 
(define_insn_reservation "power5-fpload" 6 ; 5
92 
  (and (eq_attr "type" "fpload")
93 
       (eq_attr "cpu" "power5"))
94 
  "lsq_power5")
95 
 
96 
(define_insn_reservation "power5-fpload-update" 6 ; 5
97 
  (and (eq_attr "type" "fpload_u,fpload_ux")
98 
       (eq_attr "cpu" "power5"))
99 
  "du1_power5+du2_power5,lsu1_power5+iu2_power5")
100 
 
101 
(define_insn_reservation "power5-store" 12
102 
  (and (eq_attr "type" "store")
103 
       (eq_attr "cpu" "power5"))
104 
  "((du1_power5,lsu1_power5)\
105 
    |(du2_power5,lsu2_power5)\
106 
    |(du3_power5,lsu2_power5)\
107 
    |(du4_power5,lsu1_power5)),\
108 
    (iu1_power5|iu2_power5)")
109 
 
110 
(define_insn_reservation "power5-store-update" 12
111 
  (and (eq_attr "type" "store_u")
112 
       (eq_attr "cpu" "power5"))
113 
  "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
114 
 
115 
(define_insn_reservation "power5-store-update-indexed" 12
116 
  (and (eq_attr "type" "store_ux")
117 
       (eq_attr "cpu" "power5"))
118 
   "du1_power5+du2_power5+du3_power5+du4_power5,\
119 
    iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
120 
 
121 
(define_insn_reservation "power5-fpstore" 12
122 
  (and (eq_attr "type" "fpstore")
123 
       (eq_attr "cpu" "power5"))
124 
  "((du1_power5,lsu1_power5)\
125 
    |(du2_power5,lsu2_power5)\
126 
    |(du3_power5,lsu2_power5)\
127 
    |(du4_power5,lsu1_power5)),\
128 
    (fpu1_power5|fpu2_power5)")
129 
 
130 
(define_insn_reservation "power5-fpstore-update" 12
131 
  (and (eq_attr "type" "fpstore_u,fpstore_ux")
132 
       (eq_attr "cpu" "power5"))
133 
  "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
134 
 
135 
(define_insn_reservation "power5-llsc" 11
136 
  (and (eq_attr "type" "load_l,store_c,sync")
137 
       (eq_attr "cpu" "power5"))
138 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
139 
  lsu1_power5")
140 
 
141 
 
142 
; Integer latency is 2 cycles
143 
(define_insn_reservation "power5-integer" 2
144 
  (and (eq_attr "type" "integer,insert_dword,shift,trap,\
145 
                        var_shift_rotate,cntlz,exts,isel")
146 
       (eq_attr "cpu" "power5"))
147 
  "iq_power5")
148 
 
149 
(define_insn_reservation "power5-two" 2
150 
  (and (eq_attr "type" "two")
151 
       (eq_attr "cpu" "power5"))
152 
  "((du1_power5+du2_power5)\
153 
    |(du2_power5+du3_power5)\
154 
    |(du3_power5+du4_power5)\
155 
    |(du4_power5+du1_power5)),\
156 
    ((iu1_power5,nothing,iu2_power5)\
157 
     |(iu2_power5,nothing,iu2_power5)\
158 
     |(iu2_power5,nothing,iu1_power5)\
159 
     |(iu1_power5,nothing,iu1_power5))")
160 
 
161 
(define_insn_reservation "power5-three" 2
162 
  (and (eq_attr "type" "three")
163 
       (eq_attr "cpu" "power5"))
164 
  "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
165 
    |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
166 
   ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
167 
    |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
168 
    |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
169 
    |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
170 
 
171 
(define_insn_reservation "power5-insert" 4
172 
  (and (eq_attr "type" "insert_word")
173 
       (eq_attr "cpu" "power5"))
174 
  "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
175 
 
176 
(define_insn_reservation "power5-cmp" 3
177 
  (and (eq_attr "type" "cmp,fast_compare")
178 
       (eq_attr "cpu" "power5"))
179 
  "iq_power5")
180 
 
181 
(define_insn_reservation "power5-compare" 2
182 
  (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
183 
       (eq_attr "cpu" "power5"))
184 
  "du1_power5+du2_power5,iu1_power5,iu2_power5")
185 
 
186 
(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
187 
 
188 
(define_insn_reservation "power5-lmul-cmp" 7
189 
  (and (eq_attr "type" "lmul_compare")
190 
       (eq_attr "cpu" "power5"))
191 
  "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
192 
 
193 
(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
194 
 
195 
(define_insn_reservation "power5-imul-cmp" 5
196 
  (and (eq_attr "type" "imul_compare")
197 
       (eq_attr "cpu" "power5"))
198 
  "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
199 
 
200 
(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
201 
 
202 
(define_insn_reservation "power5-lmul" 7
203 
  (and (eq_attr "type" "lmul")
204 
       (eq_attr "cpu" "power5"))
205 
  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
206 
 
207 
(define_insn_reservation "power5-imul" 5
208 
  (and (eq_attr "type" "imul")
209 
       (eq_attr "cpu" "power5"))
210 
  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
211 
 
212 
(define_insn_reservation "power5-imul3" 4
213 
  (and (eq_attr "type" "imul2,imul3")
214 
       (eq_attr "cpu" "power5"))
215 
  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
216 
 
217 
 
218 
; SPR move only executes in first IU.
219 
; Integer division only executes in second IU.
220 
(define_insn_reservation "power5-idiv" 36
221 
  (and (eq_attr "type" "idiv")
222 
       (eq_attr "cpu" "power5"))
223 
  "du1_power5+du2_power5,iu2_power5*35")
224 
 
225 
(define_insn_reservation "power5-ldiv" 68
226 
  (and (eq_attr "type" "ldiv")
227 
       (eq_attr "cpu" "power5"))
228 
  "du1_power5+du2_power5,iu2_power5*67")
229 
 
230 
 
231 
(define_insn_reservation "power5-mtjmpr" 3
232 
  (and (eq_attr "type" "mtjmpr,mfjmpr")
233 
       (eq_attr "cpu" "power5"))
234 
  "du1_power5,bpu_power5")
235 
 
236 
 
237 
; Branches take dispatch Slot 4.  The presence_sets prevent other insn from
238 
; grabbing previous dispatch slots once this is assigned.
239 
(define_insn_reservation "power5-branch" 2
240 
  (and (eq_attr "type" "jmpreg,branch")
241 
       (eq_attr "cpu" "power5"))
242 
  "(du5_power5\
243 
   |du4_power5+du5_power5\
244 
   |du3_power5+du4_power5+du5_power5\
245 
   |du2_power5+du3_power5+du4_power5+du5_power5\
246 
   |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
247 
 
248 
 
249 
; Condition Register logical ops are split if non-destructive (RT != RB)
250 
(define_insn_reservation "power5-crlogical" 2
251 
  (and (eq_attr "type" "cr_logical")
252 
       (eq_attr "cpu" "power5"))
253 
  "du1_power5,cru_power5")
254 
 
255 
(define_insn_reservation "power5-delayedcr" 4
256 
  (and (eq_attr "type" "delayed_cr")
257 
       (eq_attr "cpu" "power5"))
258 
  "du1_power5+du2_power5,cru_power5,cru_power5")
259 
 
260 
; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
261 
(define_insn_reservation "power5-mfcr" 6
262 
  (and (eq_attr "type" "mfcr")
263 
       (eq_attr "cpu" "power5"))
264 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
265 
   du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
266 
   cru_power5,cru_power5,cru_power5")
267 
 
268 
; mfcrf (1 field)
269 
(define_insn_reservation "power5-mfcrf" 3
270 
  (and (eq_attr "type" "mfcrf")
271 
       (eq_attr "cpu" "power5"))
272 
  "du1_power5,cru_power5")
273 
 
274 
; mtcrf (1 field)
275 
(define_insn_reservation "power5-mtcr" 4
276 
  (and (eq_attr "type" "mtcr")
277 
       (eq_attr "cpu" "power5"))
278 
  "du1_power5,iu1_power5")
279 
 
280 
; Basic FP latency is 6 cycles
281 
(define_insn_reservation "power5-fp" 6
282 
  (and (eq_attr "type" "fp,dmul")
283 
       (eq_attr "cpu" "power5"))
284 
  "fpq_power5")
285 
 
286 
(define_insn_reservation "power5-fpcompare" 5
287 
  (and (eq_attr "type" "fpcompare")
288 
       (eq_attr "cpu" "power5"))
289 
  "fpq_power5")
290 
 
291 
(define_insn_reservation "power5-sdiv" 33
292 
  (and (eq_attr "type" "sdiv,ddiv")
293 
       (eq_attr "cpu" "power5"))
294 
  "(du1_power5|du2_power5|du3_power5|du4_power5),\
295 
   (fpu1_power5*28|fpu2_power5*28)")
296 
 
297 
(define_insn_reservation "power5-sqrt" 40
298 
  (and (eq_attr "type" "ssqrt,dsqrt")
299 
       (eq_attr "cpu" "power5"))
300 
  "(du1_power5|du2_power5|du3_power5|du4_power5),\
301 
   (fpu1_power5*35|fpu2_power5*35)")
302 
 
303 
(define_insn_reservation "power5-isync" 2
304 
  (and (eq_attr "type" "isync")
305 
       (eq_attr "cpu" "power5"))
306 
  "du1_power5+du2_power5+du3_power5+du4_power5,\
307 
  lsu1_power5")
308 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.