OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rs6000/] [power6.md] - Blame information for rev 749

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; Scheduling description for IBM POWER6 processor.
2 
;;   Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc.
3 
;;   Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
4 
;;
5 
;; This file is part of GCC.
6 
;;
7 
;; GCC is free software; you can redistribute it and/or modify it
8 
;; under the terms of the GNU General Public License as published
9 
;; by the Free Software Foundation; either version 3, or (at your
10 
;; option) any later version.
11 
;;
12 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 
;; License for more details.
16 
;;
17 
;; You should have received a copy of the GNU General Public License
18 
;; along with GCC; see the file COPYING3.  If not see
19 
;; .
20 
 
21 
;; Sources:
22 
 
23 
;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
24 
;; (2 engines per chip).  The chip can issue up to 5 internal ops
25 
;; per cycle.
26 
 
27 
(define_automaton "power6iu,power6lsu,power6fpu,power6bu")
28 
 
29 
(define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
30 
(define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
31 
(define_cpu_unit "bpu_power6" "power6bu")
32 
(define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
33 
 
34 
(define_reservation "LS2_power6"
35 
                    "lsu1_power6+lsu2_power6")
36 
 
37 
(define_reservation "FPU_power6"
38 
                    "fpu1_power6|fpu2_power6")
39 
 
40 
(define_reservation "BRU_power6"
41 
                    "bpu_power6")
42 
 
43 
(define_reservation "LSU_power6"
44 
                    "lsu1_power6|lsu2_power6")
45 
 
46 
(define_reservation "LSF_power6"
47 
                    "(lsu1_power6+fpu1_power6)\
48 
                    |(lsu1_power6+fpu2_power6)\
49 
                    |(lsu2_power6+fpu1_power6)\
50 
                    |(lsu2_power6+fpu2_power6)")
51 
 
52 
(define_reservation "LX2_power6"
53 
                    "(iu1_power6+iu2_power6+lsu1_power6)\
54 
                    |(iu1_power6+iu2_power6+lsu2_power6)")
55 
 
56 
(define_reservation "FX2_power6"
57 
                    "iu1_power6+iu2_power6")
58 
 
59 
(define_reservation "X2F_power6"
60 
                    "(iu1_power6+iu2_power6+fpu1_power6)\
61 
                    |(iu1_power6+iu2_power6+fpu2_power6)")
62 
 
63 
(define_reservation "BX2_power6"
64 
                    "iu1_power6+iu2_power6+bpu_power6")
65 
 
66 
(define_reservation "LSX_power6"
67 
                    "(iu1_power6+lsu1_power6)\
68 
                    |(iu1_power6+lsu2_power6)\
69 
                    |(iu2_power6+lsu1_power6)\
70 
                    |(iu2_power6+lsu2_power6)")
71 
 
72 
(define_reservation "FXU_power6"
73 
                    "iu1_power6|iu2_power6")
74 
 
75 
(define_reservation "XLF_power6"
76 
                    "(iu1_power6+lsu1_power6+fpu1_power6)\
77 
                    |(iu1_power6+lsu1_power6+fpu2_power6)\
78 
                    |(iu1_power6+lsu2_power6+fpu1_power6)\
79 
                    |(iu1_power6+lsu2_power6+fpu2_power6)\
80 
                    |(iu2_power6+lsu1_power6+fpu1_power6)\
81 
                    |(iu2_power6+lsu1_power6+fpu2_power6)\
82 
                    |(iu2_power6+lsu2_power6+fpu1_power6)\
83 
                    |(iu2_power6+lsu2_power6+fpu2_power6)")
84 
 
85 
(define_reservation "BRX_power6"
86 
                    "(bpu_power6+iu1_power6)\
87 
                    |(bpu_power6+iu2_power6)")
88 
 
89 
; Load/store
90 
 
91 
; The default for a value written by a fixed point load
92 
; that is read/written by a subsequent fixed point op.
93 
(define_insn_reservation "power6-load" 2 ; fx
94 
  (and (eq_attr "type" "load")
95 
       (eq_attr "cpu" "power6"))
96 
  "LSU_power6")
97 
 
98 
; define the bypass for the case where the value written
99 
; by a fixed point load is used as the source value on
100 
; a store.
101 
(define_bypass 1 "power6-load,\
102 
                  power6-load-update,\
103 
                  power6-load-update-indexed"
104 
                 "power6-store,\
105 
                  power6-store-update,\
106 
                  power6-store-update-indexed,\
107 
                  power6-fpstore,\
108 
                  power6-fpstore-update"
109 
  "store_data_bypass_p")
110 
 
111 
(define_insn_reservation "power6-load-ext" 4 ; fx
112 
  (and (eq_attr "type" "load_ext")
113 
       (eq_attr "cpu" "power6"))
114 
  "LSU_power6")
115 
 
116 
; define the bypass for the case where the value written
117 
; by a fixed point load ext is used as the source value on
118 
; a store.
119 
(define_bypass 1 "power6-load-ext,\
120 
                  power6-load-ext-update,\
121 
                  power6-load-ext-update-indexed"
122 
                 "power6-store,\
123 
                  power6-store-update,\
124 
                  power6-store-update-indexed,\
125 
                  power6-fpstore,\
126 
                  power6-fpstore-update"
127 
  "store_data_bypass_p")
128 
 
129 
(define_insn_reservation "power6-load-update" 2 ; fx
130 
  (and (eq_attr "type" "load_u")
131 
       (eq_attr "cpu" "power6"))
132 
  "LSX_power6")
133 
 
134 
(define_insn_reservation "power6-load-update-indexed" 2 ; fx
135 
  (and (eq_attr "type" "load_ux")
136 
       (eq_attr "cpu" "power6"))
137 
  "LSX_power6")
138 
 
139 
(define_insn_reservation "power6-load-ext-update" 4 ; fx
140 
  (and (eq_attr "type" "load_ext_u")
141 
       (eq_attr "cpu" "power6"))
142 
  "LSX_power6")
143 
 
144 
(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
145 
  (and (eq_attr "type" "load_ext_ux")
146 
       (eq_attr "cpu" "power6"))
147 
  "LSX_power6")
148 
 
149 
(define_insn_reservation "power6-fpload" 1
150 
  (and (eq_attr "type" "fpload")
151 
       (eq_attr "cpu" "power6"))
152 
  "LSU_power6")
153 
 
154 
(define_insn_reservation "power6-fpload-update" 1
155 
  (and (eq_attr "type" "fpload_u,fpload_ux")
156 
       (eq_attr "cpu" "power6"))
157 
  "LSX_power6")
158 
 
159 
(define_insn_reservation "power6-store" 14
160 
  (and (eq_attr "type" "store")
161 
       (eq_attr "cpu" "power6"))
162 
  "LSU_power6")
163 
 
164 
(define_insn_reservation "power6-store-update" 14
165 
  (and (eq_attr "type" "store_u")
166 
       (eq_attr "cpu" "power6"))
167 
  "LSX_power6")
168 
 
169 
(define_insn_reservation "power6-store-update-indexed" 14
170 
  (and (eq_attr "type" "store_ux")
171 
       (eq_attr "cpu" "power6"))
172 
  "LX2_power6")
173 
 
174 
(define_insn_reservation "power6-fpstore" 14
175 
  (and (eq_attr "type" "fpstore")
176 
       (eq_attr "cpu" "power6"))
177 
  "LSF_power6")
178 
 
179 
(define_insn_reservation "power6-fpstore-update" 14
180 
  (and (eq_attr "type" "fpstore_u,fpstore_ux")
181 
       (eq_attr "cpu" "power6"))
182 
  "XLF_power6")
183 
 
184 
(define_insn_reservation "power6-larx" 3
185 
  (and (eq_attr "type" "load_l")
186 
       (eq_attr "cpu" "power6"))
187 
  "LS2_power6")
188 
 
189 
(define_insn_reservation "power6-stcx" 10 ; best case
190 
  (and (eq_attr "type" "store_c")
191 
       (eq_attr "cpu" "power6"))
192 
  "LSX_power6")
193 
 
194 
(define_insn_reservation "power6-sync" 11 ; N/A
195 
  (and (eq_attr "type" "sync")
196 
       (eq_attr "cpu" "power6"))
197 
  "LSU_power6")
198 
 
199 
(define_insn_reservation "power6-integer" 1
200 
  (and (eq_attr "type" "integer")
201 
       (eq_attr "cpu" "power6"))
202 
  "FXU_power6")
203 
 
204 
(define_insn_reservation "power6-isel" 1
205 
  (and (eq_attr "type" "isel")
206 
       (eq_attr "cpu" "power6"))
207 
  "FXU_power6")
208 
 
209 
(define_insn_reservation "power6-exts" 1
210 
  (and (eq_attr "type" "exts")
211 
       (eq_attr "cpu" "power6"))
212 
  "FXU_power6")
213 
 
214 
(define_insn_reservation "power6-shift" 1
215 
  (and (eq_attr "type" "shift")
216 
       (eq_attr "cpu" "power6"))
217 
  "FXU_power6")
218 
 
219 
(define_insn_reservation "power6-insert" 1
220 
  (and (eq_attr "type" "insert_word")
221 
       (eq_attr "cpu" "power6"))
222 
  "FX2_power6")
223 
 
224 
(define_insn_reservation "power6-insert-dword" 1
225 
  (and (eq_attr "type" "insert_dword")
226 
       (eq_attr "cpu" "power6"))
227 
  "FX2_power6")
228 
 
229 
; define the bypass for the case where the value written
230 
; by a fixed point op is used as the source value on a
231 
; store.
232 
(define_bypass 1 "power6-integer,\
233 
                  power6-exts,\
234 
                  power6-shift,\
235 
                  power6-insert,\
236 
                  power6-insert-dword"
237 
                 "power6-store,\
238 
                  power6-store-update,\
239 
                  power6-store-update-indexed,\
240 
                  power6-fpstore,\
241 
                  power6-fpstore-update"
242 
  "store_data_bypass_p")
243 
 
244 
(define_insn_reservation "power6-cntlz" 2
245 
  (and (eq_attr "type" "cntlz")
246 
       (eq_attr "cpu" "power6"))
247 
  "FXU_power6")
248 
 
249 
(define_bypass 1 "power6-cntlz"
250 
                 "power6-store,\
251 
                  power6-store-update,\
252 
                  power6-store-update-indexed,\
253 
                  power6-fpstore,\
254 
                  power6-fpstore-update"
255 
  "store_data_bypass_p")
256 
 
257 
(define_insn_reservation "power6-var-rotate" 4
258 
  (and (eq_attr "type" "var_shift_rotate")
259 
       (eq_attr "cpu" "power6"))
260 
  "FXU_power6")
261 
 
262 
(define_insn_reservation "power6-trap" 1 ; N/A
263 
  (and (eq_attr "type" "trap")
264 
       (eq_attr "cpu" "power6"))
265 
  "BRX_power6")
266 
 
267 
(define_insn_reservation "power6-two" 1
268 
  (and (eq_attr "type" "two")
269 
       (eq_attr "cpu" "power6"))
270 
  "(iu1_power6,iu1_power6)\
271 
  |(iu1_power6+iu2_power6,nothing)\
272 
  |(iu1_power6,iu2_power6)\
273 
  |(iu2_power6,iu1_power6)\
274 
  |(iu2_power6,iu2_power6)")
275 
 
276 
(define_insn_reservation "power6-three" 1
277 
  (and (eq_attr "type" "three")
278 
       (eq_attr "cpu" "power6"))
279 
  "(iu1_power6,iu1_power6,iu1_power6)\
280 
  |(iu1_power6,iu1_power6,iu2_power6)\
281 
  |(iu1_power6,iu2_power6,iu1_power6)\
282 
  |(iu1_power6,iu2_power6,iu2_power6)\
283 
  |(iu2_power6,iu1_power6,iu1_power6)\
284 
  |(iu2_power6,iu1_power6,iu2_power6)\
285 
  |(iu2_power6,iu2_power6,iu1_power6)\
286 
  |(iu2_power6,iu2_power6,iu2_power6)\
287 
  |(iu1_power6+iu2_power6,iu1_power6)\
288 
  |(iu1_power6+iu2_power6,iu2_power6)\
289 
  |(iu1_power6,iu1_power6+iu2_power6)\
290 
  |(iu2_power6,iu1_power6+iu2_power6)")
291 
 
292 
(define_insn_reservation "power6-cmp" 1
293 
  (and (eq_attr "type" "cmp")
294 
       (eq_attr "cpu" "power6"))
295 
  "FXU_power6")
296 
 
297 
(define_insn_reservation "power6-compare" 1
298 
  (and (eq_attr "type" "compare")
299 
       (eq_attr "cpu" "power6"))
300 
  "FXU_power6")
301 
 
302 
(define_insn_reservation "power6-fast-compare" 1
303 
  (and (eq_attr "type" "fast_compare")
304 
       (eq_attr "cpu" "power6"))
305 
  "FXU_power6")
306 
 
307 
; define the bypass for the case where the value written
308 
; by a fixed point rec form op is used as the source value
309 
; on a store.
310 
(define_bypass 1 "power6-compare,\
311 
                  power6-fast-compare"
312 
                 "power6-store,\
313 
                  power6-store-update,\
314 
                  power6-store-update-indexed,\
315 
                  power6-fpstore,\
316 
                  power6-fpstore-update"
317 
  "store_data_bypass_p")
318 
 
319 
(define_insn_reservation "power6-delayed-compare" 2 ; N/A
320 
  (and (eq_attr "type" "delayed_compare")
321 
       (eq_attr "cpu" "power6"))
322 
  "FXU_power6")
323 
 
324 
(define_insn_reservation "power6-var-delayed-compare" 4
325 
  (and (eq_attr "type" "var_delayed_compare")
326 
       (eq_attr "cpu" "power6"))
327 
  "FXU_power6")
328 
 
329 
(define_insn_reservation "power6-lmul-cmp" 16
330 
  (and (eq_attr "type" "lmul_compare")
331 
       (eq_attr "cpu" "power6"))
332 
  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
333 
  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
334 
 
335 
(define_insn_reservation "power6-imul-cmp" 16
336 
  (and (eq_attr "type" "imul_compare")
337 
       (eq_attr "cpu" "power6"))
338 
  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
339 
  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
340 
 
341 
(define_insn_reservation "power6-lmul" 16
342 
  (and (eq_attr "type" "lmul")
343 
       (eq_attr "cpu" "power6"))
344 
  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
345 
  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
346 
 
347 
(define_insn_reservation "power6-imul" 16
348 
  (and (eq_attr "type" "imul")
349 
       (eq_attr "cpu" "power6"))
350 
  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
351 
  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
352 
 
353 
(define_insn_reservation "power6-imul3" 16
354 
  (and (eq_attr "type" "imul2,imul3")
355 
       (eq_attr "cpu" "power6"))
356 
  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
357 
  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
358 
 
359 
(define_bypass 9 "power6-imul,\
360 
                  power6-lmul,\
361 
                  power6-imul-cmp,\
362 
                  power6-lmul-cmp,\
363 
                  power6-imul3"
364 
                 "power6-store,\
365 
                  power6-store-update,\
366 
                  power6-store-update-indexed,\
367 
                  power6-fpstore,\
368 
                  power6-fpstore-update"
369 
  "store_data_bypass_p")
370 
 
371 
(define_insn_reservation "power6-idiv" 44
372 
  (and (eq_attr "type" "idiv")
373 
       (eq_attr "cpu" "power6"))
374 
  "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
375 
  |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
376 
 
377 
; The latency for this bypass is yet to be defined
378 
;(define_bypass ? "power6-idiv"
379 
;                 "power6-store,\
380 
;                  power6-store-update,\
381 
;                  power6-store-update-indexed,\
382 
;                  power6-fpstore,\
383 
;                  power6-fpstore-update"
384 
;  "store_data_bypass_p")
385 
 
386 
(define_insn_reservation "power6-ldiv" 56
387 
  (and (eq_attr "type" "ldiv")
388 
       (eq_attr "cpu" "power6"))
389 
  "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
390 
  |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
391 
 
392 
; The latency for this bypass is yet to be defined
393 
;(define_bypass ? "power6-ldiv"
394 
;                 "power6-store,\
395 
;                  power6-store-update,\
396 
;                  power6-store-update-indexed,\
397 
;                  power6-fpstore,\
398 
;                  power6-fpstore-update"
399 
;  "store_data_bypass_p")
400 
 
401 
(define_insn_reservation "power6-mtjmpr" 2
402 
  (and (eq_attr "type" "mtjmpr,mfjmpr")
403 
       (eq_attr "cpu" "power6"))
404 
  "BX2_power6")
405 
 
406 
(define_bypass 5 "power6-mtjmpr" "power6-branch")
407 
 
408 
(define_insn_reservation "power6-branch" 2
409 
  (and (eq_attr "type" "jmpreg,branch")
410 
       (eq_attr "cpu" "power6"))
411 
  "BRU_power6")
412 
 
413 
(define_bypass 5 "power6-branch" "power6-mtjmpr")
414 
 
415 
(define_insn_reservation "power6-crlogical" 3
416 
  (and (eq_attr "type" "cr_logical")
417 
       (eq_attr "cpu" "power6"))
418 
  "BRU_power6")
419 
 
420 
(define_bypass 3 "power6-crlogical" "power6-branch")
421 
 
422 
(define_insn_reservation "power6-delayedcr" 3
423 
  (and (eq_attr "type" "delayed_cr")
424 
       (eq_attr "cpu" "power6"))
425 
  "BRU_power6")
426 
 
427 
(define_insn_reservation "power6-mfcr" 6 ; N/A
428 
  (and (eq_attr "type" "mfcr")
429 
       (eq_attr "cpu" "power6"))
430 
  "BX2_power6")
431 
 
432 
; mfcrf (1 field)
433 
(define_insn_reservation "power6-mfcrf" 3 ; N/A
434 
  (and (eq_attr "type" "mfcrf")
435 
       (eq_attr "cpu" "power6"))
436 
  "BX2_power6") ;
437 
 
438 
; mtcrf (1 field)
439 
(define_insn_reservation "power6-mtcr" 4 ; N/A
440 
  (and (eq_attr "type" "mtcr")
441 
       (eq_attr "cpu" "power6"))
442 
  "BX2_power6")
443 
 
444 
(define_bypass 9 "power6-mtcr" "power6-branch")
445 
 
446 
(define_insn_reservation "power6-fp" 6
447 
  (and (eq_attr "type" "fp,dmul")
448 
       (eq_attr "cpu" "power6"))
449 
  "FPU_power6")
450 
 
451 
; Any fp instruction that updates a CR has a latency
452 
; of 6 to a dependent branch
453 
(define_bypass 6 "power6-fp" "power6-branch")
454 
 
455 
(define_bypass 1 "power6-fp"
456 
                 "power6-fpstore,power6-fpstore-update"
457 
  "store_data_bypass_p")
458 
 
459 
(define_insn_reservation "power6-fpcompare" 8
460 
  (and (eq_attr "type" "fpcompare")
461 
       (eq_attr "cpu" "power6"))
462 
  "FPU_power6")
463 
 
464 
(define_bypass 12 "power6-fpcompare"
465 
                  "power6-branch,power6-crlogical")
466 
 
467 
(define_insn_reservation "power6-sdiv" 26
468 
  (and (eq_attr "type" "sdiv")
469 
       (eq_attr "cpu" "power6"))
470 
  "FPU_power6")
471 
 
472 
(define_insn_reservation "power6-ddiv" 32
473 
  (and (eq_attr "type" "ddiv")
474 
       (eq_attr "cpu" "power6"))
475 
  "FPU_power6")
476 
 
477 
(define_insn_reservation "power6-sqrt" 30
478 
  (and (eq_attr "type" "ssqrt")
479 
       (eq_attr "cpu" "power6"))
480 
  "FPU_power6")
481 
 
482 
(define_insn_reservation "power6-dsqrt" 42
483 
  (and (eq_attr "type" "dsqrt")
484 
       (eq_attr "cpu" "power6"))
485 
  "FPU_power6")
486 
 
487 
(define_insn_reservation "power6-isync" 2 ; N/A
488 
  (and (eq_attr "type" "isync")
489 
       (eq_attr "cpu" "power6"))
490 
  "FXU_power6")
491 
 
492 
(define_insn_reservation "power6-vecload" 1
493 
  (and (eq_attr "type" "vecload")
494 
       (eq_attr "cpu" "power6"))
495 
  "LSU_power6")
496 
 
497 
(define_insn_reservation "power6-vecstore" 1
498 
  (and (eq_attr "type" "vecstore")
499 
       (eq_attr "cpu" "power6"))
500 
  "LSF_power6")
501 
 
502 
(define_insn_reservation "power6-vecsimple" 3
503 
  (and (eq_attr "type" "vecsimple")
504 
       (eq_attr "cpu" "power6"))
505 
  "FPU_power6")
506 
 
507 
(define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
508 
                                     power6-vecperm")
509 
 
510 
(define_bypass 5 "power6-vecsimple" "power6-vecfloat")
511 
 
512 
(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
513 
 
514 
(define_insn_reservation "power6-veccmp" 1
515 
  (and (eq_attr "type" "veccmp")
516 
       (eq_attr "cpu" "power6"))
517 
  "FPU_power6")
518 
 
519 
(define_bypass 10 "power6-veccmp" "power6-branch")
520 
 
521 
(define_insn_reservation "power6-vecfloat" 7
522 
  (and (eq_attr "type" "vecfloat")
523 
       (eq_attr "cpu" "power6"))
524 
  "FPU_power6")
525 
 
526 
(define_bypass 10 "power6-vecfloat" "power6-vecsimple")
527 
 
528 
(define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
529 
                                     power6-vecperm")
530 
 
531 
(define_bypass 9 "power6-vecfloat" "power6-vecstore" )
532 
 
533 
(define_insn_reservation "power6-veccomplex" 7
534 
  (and (eq_attr "type" "vecsimple")
535 
       (eq_attr "cpu" "power6"))
536 
  "FPU_power6")
537 
 
538 
(define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
539 
                                       power6-vecfloat" )
540 
 
541 
(define_bypass 9 "power6-veccomplex" "power6-vecperm" )
542 
 
543 
(define_bypass 8 "power6-veccomplex" "power6-vecstore" )
544 
 
545 
(define_insn_reservation "power6-vecperm" 4
546 
  (and (eq_attr "type" "vecperm")
547 
       (eq_attr "cpu" "power6"))
548 
  "FPU_power6")
549 
 
550 
(define_bypass 7 "power6-vecperm" "power6-vecsimple,\
551 
                                   power6-vecfloat" )
552 
 
553 
(define_bypass 6 "power6-vecperm" "power6-veccomplex" )
554 
 
555 
(define_bypass 5 "power6-vecperm" "power6-vecstore" )
556 
 
557 
(define_insn_reservation "power6-mftgpr" 8
558 
  (and (eq_attr "type" "mftgpr")
559 
       (eq_attr "cpu" "power6"))
560 
  "X2F_power6")
561 
 
562 
(define_insn_reservation "power6-mffgpr" 14
563 
  (and (eq_attr "type" "mffgpr")
564 
       (eq_attr "cpu" "power6"))
565 
  "LX2_power6")
566 
 
567 
(define_bypass 4 "power6-mftgpr" "power6-imul,\
568 
                                  power6-lmul,\
569 
                                  power6-imul-cmp,\
570 
                                  power6-lmul-cmp,\
571 
                                  power6-imul3,\
572 
                                  power6-idiv,\
573 
                                  power6-ldiv" )

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.