OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rs6000/] [spe.md] - Blame information for rev 748

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; e500 SPE description
2 
;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 
;; Free Software Foundation, Inc.
4 
;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 
 
6 
;; This file is part of GCC.
7 
 
8 
;; GCC is free software; you can redistribute it and/or modify it
9 
;; under the terms of the GNU General Public License as published
10 
;; by the Free Software Foundation; either version 3, or (at your
11 
;; option) any later version.
12 
 
13 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
;; License for more details.
17 
 
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
(define_constants
23 
  [(CMPDFEQ_GPR         1006)
24 
   (TSTDFEQ_GPR         1007)
25 
   (CMPDFGT_GPR         1008)
26 
   (TSTDFGT_GPR         1009)
27 
   (CMPDFLT_GPR         1010)
28 
   (TSTDFLT_GPR         1011)
29 
   (CMPTFEQ_GPR         1012)
30 
   (TSTTFEQ_GPR         1013)
31 
   (CMPTFGT_GPR         1014)
32 
   (TSTTFGT_GPR         1015)
33 
   (CMPTFLT_GPR         1016)
34 
   (TSTTFLT_GPR         1017)
35 
   (E500_CR_IOR_COMPARE 1018)
36 
   ])
37 
 
38 
;; Modes using a 64-bit register.
39 
(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
40 
 
41 
;; Likewise, but allow TFmode (two registers) as well.
42 
(define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
43 
 
44 
;; DImode and TImode.
45 
(define_mode_iterator DITI [DI TI])
46 
 
47 
(define_insn "*negsf2_gpr"
48 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
49 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
50 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
51 
  "efsneg %0,%1"
52 
  [(set_attr "type" "fpsimple")])
53 
 
54 
(define_insn "*abssf2_gpr"
55 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
56 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
57 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
58 
  "efsabs %0,%1"
59 
  [(set_attr "type" "fpsimple")])
60 
 
61 
(define_insn "*nabssf2_gpr"
62 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
63 
        (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
64 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
65 
  "efsnabs %0,%1"
66 
  [(set_attr "type" "fpsimple")])
67 
 
68 
(define_insn "*addsf3_gpr"
69 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
70 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
71 
                 (match_operand:SF 2 "gpc_reg_operand" "r")))]
72 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
73 
  "efsadd %0,%1,%2"
74 
  [(set_attr "type" "fp")])
75 
 
76 
(define_insn "*subsf3_gpr"
77 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
78 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
79 
                  (match_operand:SF 2 "gpc_reg_operand" "r")))]
80 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
81 
  "efssub %0,%1,%2"
82 
  [(set_attr "type" "fp")])
83 
 
84 
(define_insn "*mulsf3_gpr"
85 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
86 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
87 
                 (match_operand:SF 2 "gpc_reg_operand" "r")))]
88 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
89 
  "efsmul %0,%1,%2"
90 
  [(set_attr "type" "fp")])
91 
 
92 
(define_insn "*divsf3_gpr"
93 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
94 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
95 
                (match_operand:SF 2 "gpc_reg_operand" "r")))]
96 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
97 
  "efsdiv %0,%1,%2"
98 
  [(set_attr "type" "vecfdiv")])
99 
 
100 
;; Floating point conversion instructions.
101 
 
102 
(define_insn "spe_fixuns_truncdfsi2"
103 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
104 
        (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
105 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
106 
  "efdctuiz %0,%1"
107 
  [(set_attr "type" "fp")])
108 
 
109 
(define_insn "spe_extendsfdf2"
110 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
111 
        (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
112 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
113 
  "efdcfs %0,%1"
114 
  [(set_attr "type" "fp")])
115 
 
116 
(define_insn "spe_fixuns_truncsfsi2"
117 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
118 
        (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
119 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
120 
  "efsctuiz %0,%1"
121 
  [(set_attr "type" "fp")])
122 
 
123 
(define_insn "spe_fix_truncsfsi2"
124 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
125 
        (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
126 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
127 
  "efsctsiz %0,%1"
128 
  [(set_attr "type" "fp")])
129 
 
130 
(define_insn "spe_fix_truncdfsi2"
131 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
132 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
133 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
134 
  "efdctsiz %0,%1"
135 
  [(set_attr "type" "fp")])
136 
 
137 
(define_insn "spe_floatunssisf2"
138 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
139 
        (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
140 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
141 
  "efscfui %0,%1"
142 
  [(set_attr "type" "fp")])
143 
 
144 
(define_insn "spe_floatunssidf2"
145 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
146 
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
147 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
148 
  "efdcfui %0,%1"
149 
  [(set_attr "type" "fp")])
150 
 
151 
(define_insn "spe_floatsisf2"
152 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
153 
        (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
154 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
155 
  "efscfsi %0,%1"
156 
  [(set_attr "type" "fp")])
157 
 
158 
(define_insn "spe_floatsidf2"
159 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
160 
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
161 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
162 
  "efdcfsi %0,%1"
163 
  [(set_attr "type" "fp")])
164 
 
165 
;; SPE SIMD instructions
166 
 
167 
(define_insn "absv2si2"
168 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
169 
        (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
170 
  "TARGET_SPE"
171 
  "evabs %0,%1"
172 
  [(set_attr "type" "vecsimple")
173 
   (set_attr  "length" "4")])
174 
 
175 
(define_insn "spe_evandc"
176 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
177 
        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
178 
                  (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
179 
  "TARGET_SPE"
180 
  "evandc %0,%1,%2"
181 
  [(set_attr "type" "vecsimple")
182 
   (set_attr  "length" "4")])
183 
 
184 
(define_insn "andv2si3"
185 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
186 
        (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
187 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
188 
  "TARGET_SPE"
189 
  "evand %0,%1,%2"
190 
  [(set_attr "type" "vecsimple")
191 
   (set_attr  "length" "4")])
192 
 
193 
;; Vector compare instructions
194 
 
195 
(define_insn "spe_evcmpeq"
196 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
197 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
198 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
199 
  "TARGET_SPE"
200 
  "evcmpeq %0,%1,%2"
201 
  [(set_attr "type" "veccmp")
202 
   (set_attr  "length" "4")])
203 
 
204 
(define_insn "spe_evcmpgts"
205 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
206 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
207 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
208 
  "TARGET_SPE"
209 
  "evcmpgts %0,%1,%2"
210 
  [(set_attr "type" "veccmp")
211 
   (set_attr  "length" "4")])
212 
 
213 
(define_insn "spe_evcmpgtu"
214 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
215 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
216 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
217 
  "TARGET_SPE"
218 
  "evcmpgtu %0,%1,%2"
219 
  [(set_attr "type" "veccmp")
220 
   (set_attr  "length" "4")])
221 
 
222 
(define_insn "spe_evcmplts"
223 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
224 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
225 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
226 
  "TARGET_SPE"
227 
  "evcmplts %0,%1,%2"
228 
  [(set_attr "type" "veccmp")
229 
   (set_attr  "length" "4")])
230 
 
231 
(define_insn "spe_evcmpltu"
232 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
233 
        (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
234 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
235 
  "TARGET_SPE"
236 
  "evcmpltu %0,%1,%2"
237 
  [(set_attr "type" "veccmp")
238 
   (set_attr  "length" "4")])
239 
 
240 
;; Floating point vector compare instructions
241 
 
242 
(define_insn "spe_evfscmpeq"
243 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
244 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
245 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
246 
   (clobber (reg:SI SPEFSCR_REGNO))]
247 
  "TARGET_SPE"
248 
  "evfscmpeq %0,%1,%2"
249 
  [(set_attr "type" "veccmp")
250 
   (set_attr  "length" "4")])
251 
 
252 
(define_insn "spe_evfscmpgt"
253 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
254 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
255 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
256 
   (clobber (reg:SI SPEFSCR_REGNO))]
257 
  "TARGET_SPE"
258 
  "evfscmpgt %0,%1,%2"
259 
  [(set_attr "type" "veccmp")
260 
   (set_attr  "length" "4")])
261 
 
262 
(define_insn "spe_evfscmplt"
263 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
264 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
265 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
266 
   (clobber (reg:SI SPEFSCR_REGNO))]
267 
  "TARGET_SPE"
268 
  "evfscmplt %0,%1,%2"
269 
  [(set_attr "type" "veccmp")
270 
   (set_attr  "length" "4")])
271 
 
272 
(define_insn "spe_evfststeq"
273 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
274 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
275 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
276 
  "TARGET_SPE"
277 
  "evfststeq %0,%1,%2"
278 
  [(set_attr "type" "veccmp")
279 
   (set_attr  "length" "4")])
280 
 
281 
(define_insn "spe_evfststgt"
282 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
283 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
284 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
285 
  "TARGET_SPE"
286 
  "evfststgt %0,%1,%2"
287 
  [(set_attr "type" "veccmp")
288 
   (set_attr  "length" "4")])
289 
 
290 
(define_insn "spe_evfststlt"
291 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
292 
        (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
293 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
294 
  "TARGET_SPE"
295 
  "evfststlt %0,%1,%2"
296 
  [(set_attr "type" "veccmp")
297 
   (set_attr  "length" "4")])
298 
 
299 
;; End of vector compare instructions
300 
 
301 
(define_insn "spe_evcntlsw"
302 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
303 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
304 
  "TARGET_SPE"
305 
  "evcntlsw %0,%1"
306 
  [(set_attr "type" "vecsimple")
307 
   (set_attr  "length" "4")])
308 
 
309 
(define_insn "spe_evcntlzw"
310 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
311 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
312 
  "TARGET_SPE"
313 
  "evcntlzw %0,%1"
314 
  [(set_attr "type" "vecsimple")
315 
   (set_attr  "length" "4")])
316 
 
317 
(define_insn "spe_eveqv"
318 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
319 
        (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
320 
                            (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
321 
  "TARGET_SPE"
322 
  "eveqv %0,%1,%2"
323 
  [(set_attr "type" "vecsimple")
324 
   (set_attr  "length" "4")])
325 
 
326 
(define_insn "spe_evextsb"
327 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
328 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
329 
  "TARGET_SPE"
330 
  "evextsb %0,%1"
331 
  [(set_attr "type" "vecsimple")
332 
   (set_attr  "length" "4")])
333 
 
334 
(define_insn "spe_evextsh"
335 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
336 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
337 
  "TARGET_SPE"
338 
  "evextsh %0,%1"
339 
  [(set_attr "type" "vecsimple")
340 
   (set_attr  "length" "4")])
341 
 
342 
(define_insn "spe_evlhhesplat"
343 
  [(set (match_operand:V2SI 0 "gpc_reg_operand"  "=r")
344 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand"   "b")
345 
                           (match_operand:QI 2 "immediate_operand" "i"))))
346 
   (unspec [(const_int 0)] 509)]
347 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
348 
  "evlhhesplat %0,%2*2(%1)"
349 
  [(set_attr "type" "vecload")
350 
   (set_attr  "length" "4")])
351 
 
352 
(define_insn "spe_evlhhesplatx"
353 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
354 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
355 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
356 
   (unspec [(const_int 0)] 510)]
357 
  "TARGET_SPE"
358 
  "evlhhesplatx %0,%1,%2"
359 
  [(set_attr "type" "vecload")
360 
   (set_attr  "length" "4")])
361 
 
362 
(define_insn "spe_evlhhossplat"
363 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
364 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
365 
                           (match_operand:QI 2 "immediate_operand" "i"))))
366 
   (unspec [(const_int 0)] 511)]
367 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
368 
  "evlhhossplat %0,%2*2(%1)"
369 
  [(set_attr "type" "vecload")
370 
   (set_attr  "length" "4")])
371 
 
372 
(define_insn "spe_evlhhossplatx"
373 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
374 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
375 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
376 
   (unspec [(const_int 0)] 512)]
377 
  "TARGET_SPE"
378 
  "evlhhossplatx %0,%1,%2"
379 
  [(set_attr "type" "vecload")
380 
   (set_attr  "length" "4")])
381 
 
382 
(define_insn "spe_evlhhousplat"
383 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
384 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
385 
                           (match_operand:QI 2 "immediate_operand" "i"))))
386 
   (unspec [(const_int 0)] 513)]
387 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
388 
  "evlhhousplat %0,%2*2(%1)"
389 
  [(set_attr "type" "vecload")
390 
   (set_attr  "length" "4")])
391 
 
392 
(define_insn "spe_evlhhousplatx"
393 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
394 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
395 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
396 
   (unspec [(const_int 0)] 514)]
397 
  "TARGET_SPE"
398 
  "evlhhousplatx %0,%1,%2"
399 
  [(set_attr "type" "vecload")
400 
   (set_attr  "length" "4")])
401 
 
402 
(define_insn "spe_evlwhsplat"
403 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
404 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
405 
                           (match_operand:QI 2 "immediate_operand" "i"))))
406 
   (unspec [(const_int 0)] 515)]
407 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
408 
  "evlwhsplat %0,%2*4(%1)"
409 
  [(set_attr "type" "vecload")
410 
   (set_attr  "length" "4")])
411 
 
412 
(define_insn "spe_evlwhsplatx"
413 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
414 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
415 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
416 
   (unspec [(const_int 0)] 516)]
417 
  "TARGET_SPE"
418 
  "evlwhsplatx %0,%1,%2"
419 
  [(set_attr "type" "vecload")
420 
   (set_attr  "length" "4")])
421 
 
422 
(define_insn "spe_evlwwsplat"
423 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
424 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
425 
                           (match_operand:QI 2 "immediate_operand" "i"))))
426 
   (unspec [(const_int 0)] 517)]
427 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
428 
  "evlwwsplat %0,%2*4(%1)"
429 
  [(set_attr "type" "vecload")
430 
   (set_attr  "length" "4")])
431 
 
432 
(define_insn "spe_evlwwsplatx"
433 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
434 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
435 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
436 
   (unspec [(const_int 0)] 518)]
437 
  "TARGET_SPE"
438 
  "evlwwsplatx %0,%1,%2"
439 
  [(set_attr "type" "vecload")
440 
   (set_attr  "length" "4")])
441 
 
442 
(define_insn "spe_evmergehi"
443 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
444 
        (vec_select:V2SI
445 
          (vec_concat:V4SI
446 
            (match_operand:V2SI 1 "gpc_reg_operand" "r")
447 
            (match_operand:V2SI 2 "gpc_reg_operand" "r"))
448 
          (parallel [(const_int 0) (const_int 2)])))]
449 
  "TARGET_SPE"
450 
  "evmergehi %0,%1,%2"
451 
  [(set_attr "type" "vecsimple")
452 
   (set_attr  "length" "4")])
453 
 
454 
(define_insn "spe_evmergehilo"
455 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
456 
        (vec_select:V2SI
457 
          (vec_concat:V4SI
458 
            (match_operand:V2SI 1 "gpc_reg_operand" "r")
459 
            (match_operand:V2SI 2 "gpc_reg_operand" "r"))
460 
          (parallel [(const_int 0) (const_int 3)])))]
461 
  "TARGET_SPE"
462 
  "evmergehilo %0,%1,%2"
463 
  [(set_attr "type" "vecsimple")
464 
   (set_attr  "length" "4")])
465 
 
466 
(define_insn "spe_evmergelo"
467 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
468 
        (vec_select:V2SI
469 
          (vec_concat:V4SI
470 
            (match_operand:V2SI 1 "gpc_reg_operand" "r")
471 
            (match_operand:V2SI 2 "gpc_reg_operand" "r"))
472 
          (parallel [(const_int 1) (const_int 3)])))]
473 
  "TARGET_SPE"
474 
  "evmergelo %0,%1,%2"
475 
  [(set_attr "type" "vecsimple")
476 
   (set_attr  "length" "4")])
477 
 
478 
(define_insn "spe_evmergelohi"
479 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
480 
        (vec_select:V2SI
481 
          (vec_concat:V4SI
482 
            (match_operand:V2SI 1 "gpc_reg_operand" "r")
483 
            (match_operand:V2SI 2 "gpc_reg_operand" "r"))
484 
          (parallel [(const_int 1) (const_int 2)])))]
485 
  "TARGET_SPE"
486 
  "evmergelohi %0,%1,%2"
487 
  [(set_attr "type" "vecsimple")
488 
   (set_attr  "length" "4")])
489 
 
490 
(define_expand "vec_perm_constv2si"
491 
  [(match_operand:V2SI 0 "gpc_reg_operand" "")
492 
   (match_operand:V2SI 1 "gpc_reg_operand" "")
493 
   (match_operand:V2SI 2 "gpc_reg_operand" "")
494 
   (match_operand:V2SI 3 "" "")]
495 
  "TARGET_SPE"
496 
{
497 
  if (rs6000_expand_vec_perm_const (operands))
498 
    DONE;
499 
  else
500 
    FAIL;
501 
})
502 
 
503 
(define_insn "spe_evnand"
504 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
505 
        (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
506 
                            (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
507 
  "TARGET_SPE"
508 
  "evnand %0,%1,%2"
509 
  [(set_attr "type" "vecsimple")
510 
   (set_attr  "length" "4")])
511 
 
512 
(define_insn "negv2si2"
513 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
514 
        (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
515 
  "TARGET_SPE"
516 
  "evneg %0,%1"
517 
  [(set_attr "type" "vecsimple")
518 
   (set_attr  "length" "4")])
519 
 
520 
(define_insn "spe_evnor"
521 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
522 
        (not:V2SI  (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
523 
                             (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
524 
  "TARGET_SPE"
525 
  "evnor %0,%1,%2"
526 
  [(set_attr "type" "vecsimple")
527 
   (set_attr  "length" "4")])
528 
 
529 
(define_insn "spe_evorc"
530 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
531 
        (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
532 
                  (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
533 
  "TARGET_SPE"
534 
  "evorc %0,%1,%2"
535 
  [(set_attr "type" "vecsimple")
536 
   (set_attr  "length" "4")])
537 
 
538 
(define_insn "spe_evor"
539 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
540 
        (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
541 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
542 
  "TARGET_SPE"
543 
  "evor %0,%1,%2"
544 
  [(set_attr "type" "vecsimple")
545 
   (set_attr  "length" "4")])
546 
 
547 
(define_insn "spe_evrlwi"
548 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
549 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
550 
                      (match_operand:QI 2 "immediate_operand" "i")] 519))]
551 
  "TARGET_SPE"
552 
  "evrlwi %0,%1,%2"
553 
  [(set_attr "type" "vecsimple")
554 
   (set_attr  "length" "4")])
555 
 
556 
(define_insn "spe_evrlw"
557 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
558 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
559 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
560 
  "TARGET_SPE"
561 
  "evrlw %0,%1,%2"
562 
  [(set_attr "type" "veccomplex")
563 
   (set_attr  "length" "4")])
564 
 
565 
(define_insn "spe_evrndw"
566 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
567 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
568 
  "TARGET_SPE"
569 
  "evrndw %0,%1"
570 
  [(set_attr "type" "vecsimple")
571 
   (set_attr  "length" "4")])
572 
 
573 
(define_insn "spe_evsel"
574 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
575 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
576 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
577 
                      (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
578 
  "TARGET_SPE"
579 
  "evsel %0,%1,%2,%3"
580 
  [(set_attr "type" "veccmp")
581 
   (set_attr "length" "4")])
582 
 
583 
(define_insn "spe_evsel_fs"
584 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
585 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
586 
                      (match_operand:V2SF 2 "gpc_reg_operand" "r")
587 
                      (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
588 
  "TARGET_SPE"
589 
  "evsel %0,%1,%2,%3"
590 
  [(set_attr "type" "veccmp")
591 
   (set_attr "length" "4")])
592 
 
593 
(define_insn "spe_evslwi"
594 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
595 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
596 
                      (match_operand:QI 2 "immediate_operand" "i")]
597 
                     523))]
598 
  "TARGET_SPE"
599 
  "evslwi %0,%1,%2"
600 
  [(set_attr "type" "vecsimple")
601 
   (set_attr  "length" "4")])
602 
 
603 
(define_insn "spe_evslw"
604 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
605 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
606 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
607 
  "TARGET_SPE"
608 
  "evslw %0,%1,%2"
609 
  [(set_attr "type" "vecsimple")
610 
   (set_attr  "length" "4")])
611 
 
612 
(define_insn "spe_evsrwis"
613 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
614 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
615 
                      (match_operand:QI 2 "immediate_operand" "i")]
616 
                     525))]
617 
  "TARGET_SPE"
618 
  "evsrwis %0,%1,%2"
619 
  [(set_attr "type" "vecsimple")
620 
   (set_attr  "length" "4")])
621 
 
622 
(define_insn "spe_evsrwiu"
623 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
624 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
625 
                      (match_operand:QI 2 "immediate_operand" "i")]
626 
                     526))]
627 
  "TARGET_SPE"
628 
  "evsrwiu %0,%1,%2"
629 
  [(set_attr "type" "vecsimple")
630 
   (set_attr  "length" "4")])
631 
 
632 
(define_insn "spe_evsrws"
633 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
634 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
635 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
636 
  "TARGET_SPE"
637 
  "evsrws %0,%1,%2"
638 
  [(set_attr "type" "vecsimple")
639 
   (set_attr  "length" "4")])
640 
 
641 
(define_insn "spe_evsrwu"
642 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
643 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
644 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
645 
  "TARGET_SPE"
646 
  "evsrwu %0,%1,%2"
647 
  [(set_attr "type" "vecsimple")
648 
   (set_attr  "length" "4")])
649 
 
650 
;; vector xors
651 
 
652 
(define_insn "xorv2si3"
653 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
654 
        (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
655 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
656 
  "TARGET_SPE"
657 
  "evxor %0,%1,%2"
658 
  [(set_attr "type" "vecsimple")
659 
   (set_attr  "length" "4")])
660 
 
661 
(define_insn "xorv4hi3"
662 
  [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
663 
        (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
664 
                  (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
665 
  "TARGET_SPE"
666 
  "evxor %0,%1,%2"
667 
  [(set_attr "type" "vecsimple")
668 
   (set_attr  "length" "4")])
669 
 
670 
(define_insn "xorv1di3"
671 
  [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
672 
        (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
673 
                  (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
674 
  "TARGET_SPE"
675 
  "evxor %0,%1,%2"
676 
  [(set_attr "type" "vecsimple")
677 
   (set_attr  "length" "4")])
678 
 
679 
;; end of vector xors
680 
 
681 
(define_insn "spe_evfsabs"
682 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
683 
        (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
684 
  "TARGET_SPE"
685 
  "evfsabs %0,%1"
686 
  [(set_attr "type" "vecsimple")
687 
   (set_attr  "length" "4")])
688 
 
689 
(define_insn "spe_evfsadd"
690 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
691 
        (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
692 
                   (match_operand:V2SF 2 "gpc_reg_operand" "r")))
693 
   (clobber (reg:SI SPEFSCR_REGNO))]
694 
  "TARGET_SPE"
695 
  "evfsadd %0,%1,%2"
696 
  [(set_attr "type" "vecfloat")
697 
   (set_attr  "length" "4")])
698 
 
699 
(define_insn "spe_evfscfsf"
700 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
701 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
702 
  "TARGET_SPE"
703 
  "evfscfsf %0,%1"
704 
  [(set_attr "type" "vecfloat")
705 
   (set_attr  "length" "4")])
706 
 
707 
(define_insn "spe_evfscfsi"
708 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
709 
        (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
710 
  "TARGET_SPE"
711 
  "evfscfsi %0,%1"
712 
  [(set_attr "type" "vecfloat")
713 
   (set_attr  "length" "4")])
714 
 
715 
(define_insn "spe_evfscfuf"
716 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
717 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
718 
  "TARGET_SPE"
719 
  "evfscfuf %0,%1"
720 
  [(set_attr "type" "vecfloat")
721 
   (set_attr  "length" "4")])
722 
 
723 
(define_insn "spe_evfscfui"
724 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
725 
        (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
726 
  "TARGET_SPE"
727 
  "evfscfui %0,%1"
728 
  [(set_attr "type" "vecfloat")
729 
   (set_attr  "length" "4")])
730 
 
731 
(define_insn "spe_evfsctsf"
732 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
733 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
734 
  "TARGET_SPE"
735 
  "evfsctsf %0,%1"
736 
  [(set_attr "type" "vecfloat")
737 
   (set_attr  "length" "4")])
738 
 
739 
(define_insn "spe_evfsctsi"
740 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
741 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
742 
  "TARGET_SPE"
743 
  "evfsctsi %0,%1"
744 
  [(set_attr "type" "vecfloat")
745 
   (set_attr  "length" "4")])
746 
 
747 
(define_insn "spe_evfsctsiz"
748 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
749 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
750 
  "TARGET_SPE"
751 
  "evfsctsiz %0,%1"
752 
  [(set_attr "type" "vecfloat")
753 
   (set_attr  "length" "4")])
754 
 
755 
(define_insn "spe_evfsctuf"
756 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
757 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
758 
  "TARGET_SPE"
759 
  "evfsctuf %0,%1"
760 
  [(set_attr "type" "vecfloat")
761 
   (set_attr  "length" "4")])
762 
 
763 
(define_insn "spe_evfsctui"
764 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
765 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
766 
  "TARGET_SPE"
767 
  "evfsctui %0,%1"
768 
  [(set_attr "type" "vecfloat")
769 
   (set_attr  "length" "4")])
770 
 
771 
(define_insn "spe_evfsctuiz"
772 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
773 
        (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
774 
  "TARGET_SPE"
775 
  "evfsctuiz %0,%1"
776 
  [(set_attr "type" "vecfloat")
777 
   (set_attr  "length" "4")])
778 
 
779 
(define_insn "spe_evfsdiv"
780 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
781 
        (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
782 
                  (match_operand:V2SF 2 "gpc_reg_operand" "r")))
783 
   (clobber (reg:SI SPEFSCR_REGNO))]
784 
  "TARGET_SPE"
785 
  "evfsdiv %0,%1,%2"
786 
  [(set_attr "type" "vecfdiv")
787 
   (set_attr  "length" "4")])
788 
 
789 
(define_insn "spe_evfsmul"
790 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
791 
        (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
792 
                   (match_operand:V2SF 2 "gpc_reg_operand" "r")))
793 
   (clobber (reg:SI SPEFSCR_REGNO))]
794 
  "TARGET_SPE"
795 
  "evfsmul %0,%1,%2"
796 
  [(set_attr "type" "vecfloat")
797 
   (set_attr  "length" "4")])
798 
 
799 
(define_insn "spe_evfsnabs"
800 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
801 
        (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
802 
  "TARGET_SPE"
803 
  "evfsnabs %0,%1"
804 
  [(set_attr "type" "vecsimple")
805 
   (set_attr  "length" "4")])
806 
 
807 
(define_insn "spe_evfsneg"
808 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
809 
        (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
810 
  "TARGET_SPE"
811 
  "evfsneg %0,%1"
812 
  [(set_attr "type" "vecsimple")
813 
   (set_attr  "length" "4")])
814 
 
815 
(define_insn "spe_evfssub"
816 
  [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
817 
        (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
818 
                    (match_operand:V2SF 2 "gpc_reg_operand" "r")))
819 
   (clobber (reg:SI SPEFSCR_REGNO))]
820 
  "TARGET_SPE"
821 
  "evfssub %0,%1,%2"
822 
  [(set_attr "type" "vecfloat")
823 
   (set_attr  "length" "4")])
824 
 
825 
;; SPE SIMD load instructions.
826 
 
827 
;; Only the hardware engineer who designed the SPE understands the
828 
;; plethora of load and store instructions ;-).  We have no way of
829 
;; differentiating between them with RTL so use an unspec of const_int 0
830 
;; to avoid identical RTL.
831 
 
832 
(define_insn "spe_evldd"
833 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
834 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
835 
                           (match_operand:QI 2 "immediate_operand" "i"))))
836 
   (unspec [(const_int 0)] 544)]
837 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
838 
  "evldd %0,%2*8(%1)"
839 
  [(set_attr "type" "vecload")
840 
   (set_attr  "length" "4")])
841 
 
842 
(define_insn "spe_evlddx"
843 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
844 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
845 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
846 
   (unspec [(const_int 0)] 545)]
847 
  "TARGET_SPE"
848 
  "evlddx %0,%1,%2"
849 
  [(set_attr "type" "vecload")
850 
   (set_attr  "length" "4")])
851 
 
852 
(define_insn "spe_evldh"
853 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
854 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
855 
                           (match_operand:QI 2 "immediate_operand" "i"))))
856 
   (unspec [(const_int 0)] 546)]
857 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
858 
  "evldh %0,%2*8(%1)"
859 
  [(set_attr "type" "vecload")
860 
   (set_attr  "length" "4")])
861 
 
862 
(define_insn "spe_evldhx"
863 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
864 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
865 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
866 
   (unspec [(const_int 0)] 547)]
867 
  "TARGET_SPE"
868 
  "evldhx %0,%1,%2"
869 
  [(set_attr "type" "vecload")
870 
   (set_attr  "length" "4")])
871 
 
872 
(define_insn "spe_evldw"
873 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
874 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
875 
                           (match_operand:QI 2 "immediate_operand" "i"))))
876 
   (unspec [(const_int 0)] 548)]
877 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
878 
  "evldw %0,%2*8(%1)"
879 
  [(set_attr "type" "vecload")
880 
   (set_attr  "length" "4")])
881 
 
882 
(define_insn "spe_evldwx"
883 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
884 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
885 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
886 
   (unspec [(const_int 0)] 549)]
887 
  "TARGET_SPE"
888 
  "evldwx %0,%1,%2"
889 
  [(set_attr "type" "vecload")
890 
   (set_attr  "length" "4")])
891 
 
892 
(define_insn "spe_evlwhe"
893 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
894 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
895 
                           (match_operand:QI 2 "immediate_operand" "i"))))
896 
   (unspec [(const_int 0)] 550)]
897 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
898 
  "evlwhe %0,%2*4(%1)"
899 
  [(set_attr "type" "vecload")
900 
   (set_attr  "length" "4")])
901 
 
902 
(define_insn "spe_evlwhex"
903 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
904 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
905 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
906 
   (unspec [(const_int 0)] 551)]
907 
  "TARGET_SPE"
908 
  "evlwhex %0,%1,%2"
909 
  [(set_attr "type" "vecload")
910 
   (set_attr  "length" "4")])
911 
 
912 
(define_insn "spe_evlwhos"
913 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
914 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
915 
                           (match_operand:QI 2 "immediate_operand" "i"))))
916 
   (unspec [(const_int 0)] 552)]
917 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
918 
  "evlwhos %0,%2*4(%1)"
919 
  [(set_attr "type" "vecload")
920 
   (set_attr  "length" "4")])
921 
 
922 
(define_insn "spe_evlwhosx"
923 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
924 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
925 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
926 
   (unspec [(const_int 0)] 553)]
927 
  "TARGET_SPE"
928 
  "evlwhosx %0,%1,%2"
929 
  [(set_attr "type" "vecload")
930 
   (set_attr  "length" "4")])
931 
 
932 
(define_insn "spe_evlwhou"
933 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
934 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
935 
                           (match_operand:QI 2 "immediate_operand" "i"))))
936 
   (unspec [(const_int 0)] 554)]
937 
  "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
938 
  "evlwhou %0,%2*4(%1)"
939 
  [(set_attr "type" "vecload")
940 
   (set_attr  "length" "4")])
941 
 
942 
(define_insn "spe_evlwhoux"
943 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
944 
        (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
945 
                           (match_operand:SI 2 "gpc_reg_operand" "r"))))
946 
   (unspec [(const_int 0)] 555)]
947 
  "TARGET_SPE"
948 
  "evlwhoux %0,%1,%2"
949 
  [(set_attr "type" "vecload")
950 
   (set_attr  "length" "4")])
951 
 
952 
(define_insn "spe_brinc"
953 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
954 
        (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
955 
                    (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
956 
  "TARGET_SPE"
957 
  "brinc %0,%1,%2"
958 
  [(set_attr "type" "brinc")
959 
   (set_attr  "length" "4")])
960 
 
961 
(define_insn "spe_evmhegsmfaa"
962 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
963 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
964 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
965 
                      (reg:V2SI SPE_ACC_REGNO)] 557))
966 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
967 
  "TARGET_SPE"
968 
  "evmhegsmfaa %0,%1,%2"
969 
  [(set_attr "type" "veccomplex")
970 
   (set_attr  "length" "4")])
971 
 
972 
(define_insn "spe_evmhegsmfan"
973 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
974 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
975 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
976 
                      (reg:V2SI SPE_ACC_REGNO)] 558))
977 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
978 
  "TARGET_SPE"
979 
  "evmhegsmfan %0,%1,%2"
980 
  [(set_attr "type" "veccomplex")
981 
   (set_attr  "length" "4")])
982 
 
983 
(define_insn "spe_evmhegsmiaa"
984 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
985 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
986 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
987 
                      (reg:V2SI SPE_ACC_REGNO)] 559))
988 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
989 
  "TARGET_SPE"
990 
  "evmhegsmiaa %0,%1,%2"
991 
  [(set_attr "type" "veccomplex")
992 
   (set_attr  "length" "4")])
993 
 
994 
(define_insn "spe_evmhegsmian"
995 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
996 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
997 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
998 
                      (reg:V2SI SPE_ACC_REGNO)] 560))
999 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1000 
  "TARGET_SPE"
1001 
  "evmhegsmian %0,%1,%2"
1002 
  [(set_attr "type" "veccomplex")
1003 
   (set_attr  "length" "4")])
1004 
 
1005 
(define_insn "spe_evmhegumiaa"
1006 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1007 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1008 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1009 
                      (reg:V2SI SPE_ACC_REGNO)] 561))
1010 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1011 
  "TARGET_SPE"
1012 
  "evmhegumiaa %0,%1,%2"
1013 
  [(set_attr "type" "veccomplex")
1014 
   (set_attr  "length" "4")])
1015 
 
1016 
(define_insn "spe_evmhegumian"
1017 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1018 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1019 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1020 
                      (reg:V2SI SPE_ACC_REGNO)] 562))
1021 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1022 
  "TARGET_SPE"
1023 
  "evmhegumian %0,%1,%2"
1024 
  [(set_attr "type" "veccomplex")
1025 
   (set_attr  "length" "4")])
1026 
 
1027 
(define_insn "spe_evmhesmfaaw"
1028 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1029 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1030 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1031 
                      (reg:V2SI SPE_ACC_REGNO)] 563))
1032 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1033 
  "TARGET_SPE"
1034 
  "evmhesmfaaw %0,%1,%2"
1035 
  [(set_attr "type" "veccomplex")
1036 
   (set_attr  "length" "4")])
1037 
 
1038 
(define_insn "spe_evmhesmfanw"
1039 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1040 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1041 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1042 
                      (reg:V2SI SPE_ACC_REGNO)] 564))
1043 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1044 
  "TARGET_SPE"
1045 
  "evmhesmfanw %0,%1,%2"
1046 
  [(set_attr "type" "veccomplex")
1047 
   (set_attr  "length" "4")])
1048 
 
1049 
(define_insn "spe_evmhesmfa"
1050 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1051 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1052 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
1053 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1054 
  "TARGET_SPE"
1055 
  "evmhesmfa %0,%1,%2"
1056 
  [(set_attr "type" "veccomplex")
1057 
   (set_attr  "length" "4")])
1058 
 
1059 
(define_insn "spe_evmhesmf"
1060 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1061 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1062 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1063 
  "TARGET_SPE"
1064 
  "evmhesmf %0,%1,%2"
1065 
  [(set_attr "type" "veccomplex")
1066 
   (set_attr  "length" "4")])
1067 
 
1068 
(define_insn "spe_evmhesmiaaw"
1069 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1070 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1071 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1072 
                      (reg:V2SI SPE_ACC_REGNO)] 567))
1073 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1074 
  "TARGET_SPE"
1075 
  "evmhesmiaaw %0,%1,%2"
1076 
  [(set_attr "type" "veccomplex")
1077 
   (set_attr  "length" "4")])
1078 
 
1079 
(define_insn "spe_evmhesmianw"
1080 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1081 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1082 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1083 
                      (reg:V2SI SPE_ACC_REGNO)] 568))
1084 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1085 
  "TARGET_SPE"
1086 
  "evmhesmianw %0,%1,%2"
1087 
  [(set_attr "type" "veccomplex")
1088 
   (set_attr  "length" "4")])
1089 
 
1090 
(define_insn "spe_evmhesmia"
1091 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1092 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1093 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
1094 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1095 
  "TARGET_SPE"
1096 
  "evmhesmia %0,%1,%2"
1097 
  [(set_attr "type" "veccomplex")
1098 
   (set_attr  "length" "4")])
1099 
 
1100 
(define_insn "spe_evmhesmi"
1101 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1102 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1103 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1104 
  "TARGET_SPE"
1105 
  "evmhesmi %0,%1,%2"
1106 
  [(set_attr "type" "veccomplex")
1107 
   (set_attr  "length" "4")])
1108 
 
1109 
(define_insn "spe_evmhessfaaw"
1110 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1111 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1112 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1113 
                      (reg:V2SI SPE_ACC_REGNO)] 571))
1114 
   (clobber (reg:SI SPEFSCR_REGNO))
1115 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1116 
  "TARGET_SPE"
1117 
  "evmhessfaaw %0,%1,%2"
1118 
  [(set_attr "type" "veccomplex")
1119 
   (set_attr  "length" "4")])
1120 
 
1121 
(define_insn "spe_evmhessfanw"
1122 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1123 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1124 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1125 
                      (reg:V2SI SPE_ACC_REGNO)] 572))
1126 
   (clobber (reg:SI SPEFSCR_REGNO))
1127 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1128 
  "TARGET_SPE"
1129 
  "evmhessfanw %0,%1,%2"
1130 
  [(set_attr "type" "veccomplex")
1131 
   (set_attr  "length" "4")])
1132 
 
1133 
(define_insn "spe_evmhessfa"
1134 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1135 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1136 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1137 
   (clobber (reg:SI SPEFSCR_REGNO))
1138 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1139 
  "TARGET_SPE"
1140 
  "evmhessfa %0,%1,%2"
1141 
  [(set_attr "type" "veccomplex")
1142 
   (set_attr  "length" "4")])
1143 
 
1144 
(define_insn "spe_evmhessf"
1145 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1146 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1147 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1148 
   (clobber (reg:SI SPEFSCR_REGNO))]
1149 
  "TARGET_SPE"
1150 
  "evmhessf %0,%1,%2"
1151 
  [(set_attr "type" "veccomplex")
1152 
   (set_attr  "length" "4")])
1153 
 
1154 
(define_insn "spe_evmhessiaaw"
1155 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1156 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1157 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1158 
                      (reg:V2SI SPE_ACC_REGNO)] 575))
1159 
   (clobber (reg:SI SPEFSCR_REGNO))
1160 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1161 
  "TARGET_SPE"
1162 
  "evmhessiaaw %0,%1,%2"
1163 
  [(set_attr "type" "veccomplex")
1164 
   (set_attr  "length" "4")])
1165 
 
1166 
(define_insn "spe_evmhessianw"
1167 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1168 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1169 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1170 
                      (reg:V2SI SPE_ACC_REGNO)] 576))
1171 
   (clobber (reg:SI SPEFSCR_REGNO))
1172 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1173 
  "TARGET_SPE"
1174 
  "evmhessianw %0,%1,%2"
1175 
  [(set_attr "type" "veccomplex")
1176 
   (set_attr  "length" "4")])
1177 
 
1178 
(define_insn "spe_evmheumiaaw"
1179 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1180 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1181 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1182 
                      (reg:V2SI SPE_ACC_REGNO)] 577))
1183 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1184 
  "TARGET_SPE"
1185 
  "evmheumiaaw %0,%1,%2"
1186 
  [(set_attr "type" "veccomplex")
1187 
   (set_attr  "length" "4")])
1188 
 
1189 
(define_insn "spe_evmheumianw"
1190 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1191 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1192 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1193 
                      (reg:V2SI SPE_ACC_REGNO)] 578))
1194 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1195 
  "TARGET_SPE"
1196 
  "evmheumianw %0,%1,%2"
1197 
  [(set_attr "type" "veccomplex")
1198 
   (set_attr  "length" "4")])
1199 
 
1200 
(define_insn "spe_evmheumia"
1201 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1202 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1203 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
1204 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1205 
  "TARGET_SPE"
1206 
  "evmheumia %0,%1,%2"
1207 
  [(set_attr "type" "veccomplex")
1208 
   (set_attr  "length" "4")])
1209 
 
1210 
(define_insn "spe_evmheumi"
1211 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1212 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1213 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1214 
  "TARGET_SPE"
1215 
  "evmheumi %0,%1,%2"
1216 
  [(set_attr "type" "veccomplex")
1217 
   (set_attr  "length" "4")])
1218 
 
1219 
(define_insn "spe_evmheusiaaw"
1220 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1221 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1222 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1223 
                      (reg:V2SI SPE_ACC_REGNO)] 581))
1224 
   (clobber (reg:SI SPEFSCR_REGNO))
1225 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1226 
  "TARGET_SPE"
1227 
  "evmheusiaaw %0,%1,%2"
1228 
  [(set_attr "type" "veccomplex")
1229 
   (set_attr  "length" "4")])
1230 
 
1231 
(define_insn "spe_evmheusianw"
1232 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1233 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1234 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1235 
                      (reg:V2SI SPE_ACC_REGNO)] 582))
1236 
   (clobber (reg:SI SPEFSCR_REGNO))
1237 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1238 
  "TARGET_SPE"
1239 
  "evmheusianw %0,%1,%2"
1240 
  [(set_attr "type" "veccomplex")
1241 
   (set_attr  "length" "4")])
1242 
 
1243 
(define_insn "spe_evmhogsmfaa"
1244 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1245 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1246 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1247 
                      (reg:V2SI SPE_ACC_REGNO)] 583))
1248 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1249 
  "TARGET_SPE"
1250 
  "evmhogsmfaa %0,%1,%2"
1251 
  [(set_attr "type" "veccomplex")
1252 
   (set_attr  "length" "4")])
1253 
 
1254 
(define_insn "spe_evmhogsmfan"
1255 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1256 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1257 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1258 
                      (reg:V2SI SPE_ACC_REGNO)] 584))
1259 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1260 
  "TARGET_SPE"
1261 
  "evmhogsmfan %0,%1,%2"
1262 
  [(set_attr "type" "veccomplex")
1263 
   (set_attr  "length" "4")])
1264 
 
1265 
(define_insn "spe_evmhogsmiaa"
1266 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1267 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1268 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1269 
                      (reg:V2SI SPE_ACC_REGNO)] 585))
1270 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1271 
  "TARGET_SPE"
1272 
  "evmhogsmiaa %0,%1,%2"
1273 
  [(set_attr "type" "veccomplex")
1274 
   (set_attr  "length" "4")])
1275 
 
1276 
(define_insn "spe_evmhogsmian"
1277 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1278 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1279 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1280 
                      (reg:V2SI SPE_ACC_REGNO)] 586))
1281 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1282 
  "TARGET_SPE"
1283 
  "evmhogsmian %0,%1,%2"
1284 
  [(set_attr "type" "veccomplex")
1285 
   (set_attr  "length" "4")])
1286 
 
1287 
(define_insn "spe_evmhogumiaa"
1288 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1289 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1290 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1291 
                      (reg:V2SI SPE_ACC_REGNO)] 587))
1292 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1293 
  "TARGET_SPE"
1294 
  "evmhogumiaa %0,%1,%2"
1295 
  [(set_attr "type" "veccomplex")
1296 
   (set_attr  "length" "4")])
1297 
 
1298 
(define_insn "spe_evmhogumian"
1299 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1300 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1301 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1302 
                      (reg:V2SI SPE_ACC_REGNO)] 588))
1303 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1304 
  "TARGET_SPE"
1305 
  "evmhogumian %0,%1,%2"
1306 
  [(set_attr "type" "veccomplex")
1307 
   (set_attr  "length" "4")])
1308 
 
1309 
(define_insn "spe_evmhosmfaaw"
1310 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1311 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1312 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1313 
                      (reg:V2SI SPE_ACC_REGNO)] 589))
1314 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1315 
  "TARGET_SPE"
1316 
  "evmhosmfaaw %0,%1,%2"
1317 
  [(set_attr "type" "veccomplex")
1318 
   (set_attr  "length" "4")])
1319 
 
1320 
(define_insn "spe_evmhosmfanw"
1321 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1322 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1323 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1324 
                      (reg:V2SI SPE_ACC_REGNO)] 590))
1325 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1326 
  "TARGET_SPE"
1327 
  "evmhosmfanw %0,%1,%2"
1328 
  [(set_attr "type" "veccomplex")
1329 
   (set_attr  "length" "4")])
1330 
 
1331 
(define_insn "spe_evmhosmfa"
1332 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1333 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1334 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1335 
  "TARGET_SPE"
1336 
  "evmhosmfa %0,%1,%2"
1337 
  [(set_attr "type" "veccomplex")
1338 
   (set_attr  "length" "4")])
1339 
 
1340 
(define_insn "spe_evmhosmf"
1341 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1342 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1343 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
1344 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1345 
  "TARGET_SPE"
1346 
  "evmhosmf %0,%1,%2"
1347 
  [(set_attr "type" "veccomplex")
1348 
   (set_attr  "length" "4")])
1349 
 
1350 
(define_insn "spe_evmhosmiaaw"
1351 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1352 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1353 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1354 
                      (reg:V2SI SPE_ACC_REGNO)] 593))
1355 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1356 
  "TARGET_SPE"
1357 
  "evmhosmiaaw %0,%1,%2"
1358 
  [(set_attr "type" "veccomplex")
1359 
   (set_attr  "length" "4")])
1360 
 
1361 
(define_insn "spe_evmhosmianw"
1362 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1363 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1364 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1365 
                      (reg:V2SI SPE_ACC_REGNO)] 594))
1366 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1367 
  "TARGET_SPE"
1368 
  "evmhosmianw %0,%1,%2"
1369 
  [(set_attr "type" "veccomplex")
1370 
   (set_attr  "length" "4")])
1371 
 
1372 
(define_insn "spe_evmhosmia"
1373 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1374 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1375 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
1376 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1377 
  "TARGET_SPE"
1378 
  "evmhosmia %0,%1,%2"
1379 
  [(set_attr "type" "veccomplex")
1380 
   (set_attr  "length" "4")])
1381 
 
1382 
(define_insn "spe_evmhosmi"
1383 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1384 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1385 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1386 
  "TARGET_SPE"
1387 
  "evmhosmi %0,%1,%2"
1388 
  [(set_attr "type" "veccomplex")
1389 
   (set_attr  "length" "4")])
1390 
 
1391 
(define_insn "spe_evmhossfaaw"
1392 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1393 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1394 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1395 
                      (reg:V2SI SPE_ACC_REGNO)] 597))
1396 
   (clobber (reg:SI SPEFSCR_REGNO))
1397 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1398 
  "TARGET_SPE"
1399 
  "evmhossfaaw %0,%1,%2"
1400 
  [(set_attr "type" "veccomplex")
1401 
   (set_attr  "length" "4")])
1402 
 
1403 
(define_insn "spe_evmhossfanw"
1404 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1405 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1406 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1407 
                      (reg:V2SI SPE_ACC_REGNO)] 598))
1408 
   (clobber (reg:SI SPEFSCR_REGNO))
1409 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1410 
  "TARGET_SPE"
1411 
  "evmhossfanw %0,%1,%2"
1412 
  [(set_attr "type" "veccomplex")
1413 
   (set_attr  "length" "4")])
1414 
 
1415 
(define_insn "spe_evmhossfa"
1416 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1417 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1418 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1419 
                      (reg:V2SI SPE_ACC_REGNO)] 599))
1420 
   (clobber (reg:SI SPEFSCR_REGNO))
1421 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1422 
  "TARGET_SPE"
1423 
  "evmhossfa %0,%1,%2"
1424 
  [(set_attr "type" "veccomplex")
1425 
   (set_attr  "length" "4")])
1426 
 
1427 
(define_insn "spe_evmhossf"
1428 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1429 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1430 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1431 
   (clobber (reg:SI SPEFSCR_REGNO))]
1432 
  "TARGET_SPE"
1433 
  "evmhossf %0,%1,%2"
1434 
  [(set_attr "type" "veccomplex")
1435 
   (set_attr  "length" "4")])
1436 
 
1437 
(define_insn "spe_evmhossiaaw"
1438 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1439 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1440 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1441 
                      (reg:V2SI SPE_ACC_REGNO)] 601))
1442 
   (clobber (reg:SI SPEFSCR_REGNO))
1443 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1444 
  "TARGET_SPE"
1445 
  "evmhossiaaw %0,%1,%2"
1446 
  [(set_attr "type" "veccomplex")
1447 
   (set_attr  "length" "4")])
1448 
 
1449 
(define_insn "spe_evmhossianw"
1450 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1451 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1452 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1453 
                      (reg:V2SI SPE_ACC_REGNO)] 602))
1454 
   (clobber (reg:SI SPEFSCR_REGNO))
1455 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1456 
  "TARGET_SPE"
1457 
  "evmhossianw %0,%1,%2"
1458 
  [(set_attr "type" "veccomplex")
1459 
   (set_attr  "length" "4")])
1460 
 
1461 
(define_insn "spe_evmhoumiaaw"
1462 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1463 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1464 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1465 
                      (reg:V2SI SPE_ACC_REGNO)] 603))
1466 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1467 
  "TARGET_SPE"
1468 
  "evmhoumiaaw %0,%1,%2"
1469 
  [(set_attr "type" "veccomplex")
1470 
   (set_attr  "length" "4")])
1471 
 
1472 
(define_insn "spe_evmhoumianw"
1473 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1474 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1475 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1476 
                      (reg:V2SI SPE_ACC_REGNO)] 604))
1477 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1478 
  "TARGET_SPE"
1479 
  "evmhoumianw %0,%1,%2"
1480 
  [(set_attr "type" "veccomplex")
1481 
   (set_attr  "length" "4")])
1482 
 
1483 
(define_insn "spe_evmhoumia"
1484 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1485 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1486 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
1487 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1488 
  "TARGET_SPE"
1489 
  "evmhoumia %0,%1,%2"
1490 
  [(set_attr "type" "veccomplex")
1491 
   (set_attr  "length" "4")])
1492 
 
1493 
(define_insn "spe_evmhoumi"
1494 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1495 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1496 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1497 
  "TARGET_SPE"
1498 
  "evmhoumi %0,%1,%2"
1499 
  [(set_attr "type" "veccomplex")
1500 
   (set_attr  "length" "4")])
1501 
 
1502 
(define_insn "spe_evmhousiaaw"
1503 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1504 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1505 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1506 
                      (reg:V2SI SPE_ACC_REGNO)] 607))
1507 
   (clobber (reg:SI SPEFSCR_REGNO))
1508 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1509 
  "TARGET_SPE"
1510 
  "evmhousiaaw %0,%1,%2"
1511 
  [(set_attr "type" "veccomplex")
1512 
   (set_attr  "length" "4")])
1513 
 
1514 
(define_insn "spe_evmhousianw"
1515 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1516 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1517 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1518 
                      (reg:V2SI SPE_ACC_REGNO)] 608))
1519 
   (clobber (reg:SI SPEFSCR_REGNO))
1520 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1521 
  "TARGET_SPE"
1522 
  "evmhousianw %0,%1,%2"
1523 
  [(set_attr "type" "veccomplex")
1524 
   (set_attr  "length" "4")])
1525 
 
1526 
(define_insn "spe_evmmlssfa"
1527 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1528 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1529 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1530 
  "TARGET_SPE"
1531 
  "evmmlssfa %0,%1,%2"
1532 
  [(set_attr "type" "veccomplex")
1533 
   (set_attr  "length" "4")])
1534 
 
1535 
(define_insn "spe_evmmlssf"
1536 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1537 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1538 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1539 
  "TARGET_SPE"
1540 
  "evmmlssf %0,%1,%2"
1541 
  [(set_attr "type" "veccomplex")
1542 
   (set_attr  "length" "4")])
1543 
 
1544 
(define_insn "spe_evmwhsmfa"
1545 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1546 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1547 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
1548 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1549 
  "TARGET_SPE"
1550 
  "evmwhsmfa %0,%1,%2"
1551 
  [(set_attr "type" "veccomplex")
1552 
   (set_attr  "length" "4")])
1553 
 
1554 
(define_insn "spe_evmwhsmf"
1555 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1556 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1557 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1558 
  "TARGET_SPE"
1559 
  "evmwhsmf %0,%1,%2"
1560 
  [(set_attr "type" "veccomplex")
1561 
   (set_attr  "length" "4")])
1562 
 
1563 
(define_insn "spe_evmwhsmia"
1564 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1565 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1566 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
1567 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1568 
  "TARGET_SPE"
1569 
  "evmwhsmia %0,%1,%2"
1570 
  [(set_attr "type" "veccomplex")
1571 
   (set_attr  "length" "4")])
1572 
 
1573 
(define_insn "spe_evmwhsmi"
1574 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1575 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1576 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1577 
  "TARGET_SPE"
1578 
  "evmwhsmi %0,%1,%2"
1579 
  [(set_attr "type" "veccomplex")
1580 
   (set_attr  "length" "4")])
1581 
 
1582 
(define_insn "spe_evmwhssfa"
1583 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1584 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1585 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1586 
   (clobber (reg:SI SPEFSCR_REGNO))
1587 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1588 
  "TARGET_SPE"
1589 
  "evmwhssfa %0,%1,%2"
1590 
  [(set_attr "type" "veccomplex")
1591 
   (set_attr  "length" "4")])
1592 
 
1593 
(define_insn "spe_evmwhusian"
1594 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1595 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1596 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1597 
  "TARGET_SPE"
1598 
  "evmwhusian %0,%1,%2"
1599 
  [(set_attr "type" "veccomplex")
1600 
   (set_attr  "length" "4")])
1601 
 
1602 
(define_insn "spe_evmwhssf"
1603 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1604 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1605 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1606 
   (clobber (reg:SI SPEFSCR_REGNO))]
1607 
  "TARGET_SPE"
1608 
  "evmwhssf %0,%1,%2"
1609 
  [(set_attr "type" "veccomplex")
1610 
   (set_attr  "length" "4")])
1611 
 
1612 
(define_insn "spe_evmwhumia"
1613 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1614 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1615 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
1616 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1617 
  "TARGET_SPE"
1618 
  "evmwhumia %0,%1,%2"
1619 
  [(set_attr "type" "veccomplex")
1620 
   (set_attr  "length" "4")])
1621 
 
1622 
(define_insn "spe_evmwhumi"
1623 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1624 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1625 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1626 
  "TARGET_SPE"
1627 
  "evmwhumi %0,%1,%2"
1628 
  [(set_attr "type" "veccomplex")
1629 
   (set_attr  "length" "4")])
1630 
 
1631 
(define_insn "spe_evmwlsmiaaw"
1632 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1633 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1634 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1635 
                      (reg:V2SI SPE_ACC_REGNO)] 635))
1636 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1637 
  "TARGET_SPE"
1638 
  "evmwlsmiaaw %0,%1,%2"
1639 
  [(set_attr "type" "veccomplex")
1640 
   (set_attr  "length" "4")])
1641 
 
1642 
(define_insn "spe_evmwlsmianw"
1643 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1644 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1645 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1646 
                      (reg:V2SI SPE_ACC_REGNO)] 636))
1647 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1648 
  "TARGET_SPE"
1649 
  "evmwlsmianw %0,%1,%2"
1650 
  [(set_attr "type" "veccomplex")
1651 
   (set_attr  "length" "4")])
1652 
 
1653 
(define_insn "spe_evmwlssiaaw"
1654 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1655 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1656 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1657 
                      (reg:V2SI SPE_ACC_REGNO)] 641))
1658 
   (clobber (reg:SI SPEFSCR_REGNO))
1659 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1660 
  "TARGET_SPE"
1661 
  "evmwlssiaaw %0,%1,%2"
1662 
  [(set_attr "type" "veccomplex")
1663 
   (set_attr  "length" "4")])
1664 
 
1665 
(define_insn "spe_evmwlssianw"
1666 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1667 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1668 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1669 
                      (reg:V2SI SPE_ACC_REGNO)] 642))
1670 
   (clobber (reg:SI SPEFSCR_REGNO))
1671 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1672 
  "TARGET_SPE"
1673 
  "evmwlssianw %0,%1,%2"
1674 
  [(set_attr "type" "veccomplex")
1675 
   (set_attr  "length" "4")])
1676 
 
1677 
(define_insn "spe_evmwlumiaaw"
1678 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1679 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1680 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1681 
                      (reg:V2SI SPE_ACC_REGNO)] 643))
1682 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1683 
  "TARGET_SPE"
1684 
  "evmwlumiaaw %0,%1,%2"
1685 
  [(set_attr "type" "veccomplex")
1686 
   (set_attr  "length" "4")])
1687 
 
1688 
(define_insn "spe_evmwlumianw"
1689 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1690 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1691 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1692 
                      (reg:V2SI SPE_ACC_REGNO)] 644))
1693 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1694 
  "TARGET_SPE"
1695 
  "evmwlumianw %0,%1,%2"
1696 
  [(set_attr "type" "veccomplex")
1697 
   (set_attr  "length" "4")])
1698 
 
1699 
(define_insn "spe_evmwlumia"
1700 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1701 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1702 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
1703 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1704 
  "TARGET_SPE"
1705 
  "evmwlumia %0,%1,%2"
1706 
  [(set_attr "type" "veccomplex")
1707 
   (set_attr  "length" "4")])
1708 
 
1709 
(define_insn "spe_evmwlumi"
1710 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1711 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1712 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1713 
  "TARGET_SPE"
1714 
  "evmwlumi %0,%1,%2"
1715 
  [(set_attr "type" "veccomplex")
1716 
   (set_attr  "length" "4")])
1717 
 
1718 
(define_insn "spe_evmwlusiaaw"
1719 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1720 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1721 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1722 
                      (reg:V2SI SPE_ACC_REGNO)] 647))
1723 
   (clobber (reg:SI SPEFSCR_REGNO))
1724 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1725 
  "TARGET_SPE"
1726 
  "evmwlusiaaw %0,%1,%2"
1727 
  [(set_attr "type" "veccomplex")
1728 
   (set_attr  "length" "4")])
1729 
 
1730 
(define_insn "spe_evmwlusianw"
1731 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1732 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1733 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1734 
                      (reg:V2SI SPE_ACC_REGNO)] 648))
1735 
   (clobber (reg:SI SPEFSCR_REGNO))
1736 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1737 
  "TARGET_SPE"
1738 
  "evmwlusianw %0,%1,%2"
1739 
  [(set_attr "type" "veccomplex")
1740 
   (set_attr  "length" "4")])
1741 
 
1742 
(define_insn "spe_evmwsmfaa"
1743 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1744 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1745 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1746 
                      (reg:V2SI SPE_ACC_REGNO)] 649))
1747 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1748 
  "TARGET_SPE"
1749 
  "evmwsmfaa %0,%1,%2"
1750 
  [(set_attr "type" "veccomplex")
1751 
   (set_attr  "length" "4")])
1752 
 
1753 
(define_insn "spe_evmwsmfan"
1754 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1755 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1756 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1757 
                      (reg:V2SI SPE_ACC_REGNO)] 650))
1758 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1759 
  "TARGET_SPE"
1760 
  "evmwsmfan %0,%1,%2"
1761 
  [(set_attr "type" "veccomplex")
1762 
   (set_attr  "length" "4")])
1763 
 
1764 
(define_insn "spe_evmwsmfa"
1765 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1766 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1767 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
1768 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1769 
  "TARGET_SPE"
1770 
  "evmwsmfa %0,%1,%2"
1771 
  [(set_attr "type" "veccomplex")
1772 
   (set_attr  "length" "4")])
1773 
 
1774 
(define_insn "spe_evmwsmf"
1775 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1776 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1777 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1778 
  "TARGET_SPE"
1779 
  "evmwsmf %0,%1,%2"
1780 
  [(set_attr "type" "veccomplex")
1781 
   (set_attr  "length" "4")])
1782 
 
1783 
(define_insn "spe_evmwsmiaa"
1784 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1785 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1786 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1787 
                      (reg:V2SI SPE_ACC_REGNO)] 653))
1788 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1789 
  "TARGET_SPE"
1790 
  "evmwsmiaa %0,%1,%2"
1791 
  [(set_attr "type" "veccomplex")
1792 
   (set_attr  "length" "4")])
1793 
 
1794 
(define_insn "spe_evmwsmian"
1795 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1796 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1797 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1798 
                      (reg:V2SI SPE_ACC_REGNO)] 654))
1799 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1800 
  "TARGET_SPE"
1801 
  "evmwsmian %0,%1,%2"
1802 
  [(set_attr "type" "veccomplex")
1803 
   (set_attr  "length" "4")])
1804 
 
1805 
(define_insn "spe_evmwsmia"
1806 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1807 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1808 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
1809 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1810 
  "TARGET_SPE"
1811 
  "evmwsmia %0,%1,%2"
1812 
  [(set_attr "type" "veccomplex")
1813 
   (set_attr  "length" "4")])
1814 
 
1815 
(define_insn "spe_evmwsmi"
1816 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1817 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1818 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1819 
  "TARGET_SPE"
1820 
  "evmwsmi %0,%1,%2"
1821 
  [(set_attr "type" "veccomplex")
1822 
   (set_attr  "length" "4")])
1823 
 
1824 
(define_insn "spe_evmwssfaa"
1825 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1826 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1827 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1828 
                      (reg:V2SI SPE_ACC_REGNO)] 657))
1829 
   (clobber (reg:SI SPEFSCR_REGNO))
1830 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1831 
  "TARGET_SPE"
1832 
  "evmwssfaa %0,%1,%2"
1833 
  [(set_attr "type" "veccomplex")
1834 
   (set_attr  "length" "4")])
1835 
 
1836 
(define_insn "spe_evmwssfan"
1837 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1838 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1839 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1840 
                      (reg:V2SI SPE_ACC_REGNO)] 658))
1841 
   (clobber (reg:SI SPEFSCR_REGNO))
1842 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1843 
  "TARGET_SPE"
1844 
  "evmwssfan %0,%1,%2"
1845 
  [(set_attr "type" "veccomplex")
1846 
   (set_attr  "length" "4")])
1847 
 
1848 
(define_insn "spe_evmwssfa"
1849 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1850 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1851 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1852 
   (clobber (reg:SI SPEFSCR_REGNO))
1853 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1854 
  "TARGET_SPE"
1855 
  "evmwssfa %0,%1,%2"
1856 
  [(set_attr "type" "veccomplex")
1857 
   (set_attr  "length" "4")])
1858 
 
1859 
(define_insn "spe_evmwssf"
1860 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1861 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1862 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1863 
   (clobber (reg:SI SPEFSCR_REGNO))]
1864 
  "TARGET_SPE"
1865 
  "evmwssf %0,%1,%2"
1866 
  [(set_attr "type" "veccomplex")
1867 
   (set_attr  "length" "4")])
1868 
 
1869 
(define_insn "spe_evmwumiaa"
1870 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1871 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1872 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1873 
                      (reg:V2SI SPE_ACC_REGNO)] 661))
1874 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1875 
  "TARGET_SPE"
1876 
  "evmwumiaa %0,%1,%2"
1877 
  [(set_attr "type" "veccomplex")
1878 
   (set_attr  "length" "4")])
1879 
 
1880 
(define_insn "spe_evmwumian"
1881 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1882 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1883 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")
1884 
                      (reg:V2SI SPE_ACC_REGNO)] 662))
1885 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1886 
  "TARGET_SPE"
1887 
  "evmwumian %0,%1,%2"
1888 
  [(set_attr "type" "veccomplex")
1889 
   (set_attr  "length" "4")])
1890 
 
1891 
(define_insn "spe_evmwumia"
1892 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1893 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1894 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
1895 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1896 
  "TARGET_SPE"
1897 
  "evmwumia %0,%1,%2"
1898 
  [(set_attr "type" "veccomplex")
1899 
   (set_attr  "length" "4")])
1900 
 
1901 
(define_insn "spe_evmwumi"
1902 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1903 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1904 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1905 
  "TARGET_SPE"
1906 
  "evmwumi %0,%1,%2"
1907 
  [(set_attr "type" "veccomplex")
1908 
   (set_attr  "length" "4")])
1909 
 
1910 
(define_insn "addv2si3"
1911 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1912 
        (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1913 
                   (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1914 
  "TARGET_SPE"
1915 
  "evaddw %0,%1,%2"
1916 
  [(set_attr "type" "vecsimple")
1917 
   (set_attr  "length" "4")])
1918 
 
1919 
(define_insn "spe_evaddusiaaw"
1920 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1921 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1922 
                      (reg:V2SI SPE_ACC_REGNO)] 673))
1923 
   (clobber (reg:SI SPEFSCR_REGNO))
1924 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1925 
  "TARGET_SPE"
1926 
  "evaddusiaaw %0,%1"
1927 
  [(set_attr "type" "veccomplex")
1928 
   (set_attr  "length" "4")])
1929 
 
1930 
(define_insn "spe_evaddumiaaw"
1931 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1932 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1933 
                      (reg:V2SI SPE_ACC_REGNO)] 674))
1934 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1935 
  "TARGET_SPE"
1936 
  "evaddumiaaw %0,%1"
1937 
  [(set_attr "type" "veccomplex")
1938 
   (set_attr  "length" "4")])
1939 
 
1940 
(define_insn "spe_evaddssiaaw"
1941 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1942 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1943 
                      (reg:V2SI SPE_ACC_REGNO)] 675))
1944 
   (clobber (reg:SI SPEFSCR_REGNO))
1945 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1946 
  "TARGET_SPE"
1947 
  "evaddssiaaw %0,%1"
1948 
  [(set_attr "type" "veccomplex")
1949 
   (set_attr  "length" "4")])
1950 
 
1951 
(define_insn "spe_evaddsmiaaw"
1952 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1953 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1954 
                      (reg:V2SI SPE_ACC_REGNO)] 676))
1955 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1956 
  "TARGET_SPE"
1957 
  "evaddsmiaaw %0,%1"
1958 
  [(set_attr "type" "veccomplex")
1959 
   (set_attr  "length" "4")])
1960 
 
1961 
(define_insn "spe_evaddiw"
1962 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1963 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1964 
                      (match_operand:QI 2 "immediate_operand" "i")] 677))]
1965 
  "TARGET_SPE"
1966 
  "evaddiw %0,%1,%2"
1967 
  [(set_attr "type" "vecsimple")
1968 
   (set_attr  "length" "4")])
1969 
 
1970 
(define_insn "spe_evsubifw"
1971 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1972 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1973 
                      (match_operand:QI 2 "immediate_operand" "i")] 678))]
1974 
  "TARGET_SPE"
1975 
  "evsubifw %0,%2,%1"
1976 
  [(set_attr "type" "veccomplex")
1977 
   (set_attr  "length" "4")])
1978 
 
1979 
(define_insn "subv2si3"
1980 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1981 
        (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1982 
                    (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1983 
  "TARGET_SPE"
1984 
  "evsubfw %0,%2,%1"
1985 
  [(set_attr "type" "veccomplex")
1986 
   (set_attr  "length" "4")])
1987 
 
1988 
(define_insn "spe_evsubfusiaaw"
1989 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1990 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1991 
                      (reg:V2SI SPE_ACC_REGNO)] 679))
1992 
   (clobber (reg:SI SPEFSCR_REGNO))
1993 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
1994 
  "TARGET_SPE"
1995 
  "evsubfusiaaw %0,%1"
1996 
  [(set_attr "type" "veccomplex")
1997 
   (set_attr  "length" "4")])
1998 
 
1999 
(define_insn "spe_evsubfumiaaw"
2000 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2001 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2002 
                      (reg:V2SI SPE_ACC_REGNO)] 680))
2003 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2004 
  "TARGET_SPE"
2005 
  "evsubfumiaaw %0,%1"
2006 
  [(set_attr "type" "veccomplex")
2007 
   (set_attr  "length" "4")])
2008 
 
2009 
(define_insn "spe_evsubfssiaaw"
2010 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2011 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2012 
                      (reg:V2SI SPE_ACC_REGNO)] 681))
2013 
   (clobber (reg:SI SPEFSCR_REGNO))
2014 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2015 
  "TARGET_SPE"
2016 
  "evsubfssiaaw %0,%1"
2017 
  [(set_attr "type" "veccomplex")
2018 
   (set_attr  "length" "4")])
2019 
 
2020 
(define_insn "spe_evsubfsmiaaw"
2021 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2022 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2023 
                      (reg:V2SI SPE_ACC_REGNO)] 682))
2024 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2025 
  "TARGET_SPE"
2026 
  "evsubfsmiaaw %0,%1"
2027 
  [(set_attr "type" "veccomplex")
2028 
   (set_attr  "length" "4")])
2029 
 
2030 
(define_insn "spe_evmra"
2031 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2032 
        (match_operand:V2SI 1 "gpc_reg_operand" "r"))
2033 
   (set (reg:V2SI SPE_ACC_REGNO)
2034 
        (unspec:V2SI [(match_dup 1)] 726))]
2035 
  "TARGET_SPE"
2036 
  "evmra %0,%1"
2037 
  [(set_attr "type" "veccomplex")
2038 
   (set_attr  "length" "4")])
2039 
 
2040 
(define_insn "divv2si3"
2041 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2042 
        (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2043 
                  (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2044 
   (clobber (reg:SI SPEFSCR_REGNO))]
2045 
  "TARGET_SPE"
2046 
  "evdivws %0,%1,%2"
2047 
  [(set_attr "type" "vecdiv")
2048 
   (set_attr  "length" "4")])
2049 
 
2050 
(define_insn "spe_evdivwu"
2051 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2052 
        (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2053 
                   (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2054 
      (clobber (reg:SI SPEFSCR_REGNO))]
2055 
  "TARGET_SPE"
2056 
  "evdivwu %0,%1,%2"
2057 
  [(set_attr "type" "vecdiv")
2058 
   (set_attr  "length" "4")])
2059 
 
2060 
(define_insn "spe_evsplatfi"
2061 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2062 
        (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2063 
  "TARGET_SPE"
2064 
  "evsplatfi %0,%1"
2065 
  [(set_attr "type" "vecperm")
2066 
   (set_attr  "length" "4")])
2067 
 
2068 
(define_insn "spe_evsplati"
2069 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2070 
        (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2071 
  "TARGET_SPE"
2072 
  "evsplati %0,%1"
2073 
  [(set_attr "type" "vecperm")
2074 
   (set_attr  "length" "4")])
2075 
 
2076 
(define_insn "spe_evstdd"
2077 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2078 
                           (match_operand:QI 1 "immediate_operand" "i")))
2079 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2080 
   (unspec [(const_int 0)] 686)]
2081 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2082 
  "evstdd %2,%1*8(%0)"
2083 
  [(set_attr "type" "vecstore")
2084 
   (set_attr  "length" "4")])
2085 
 
2086 
(define_insn "spe_evstddx"
2087 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2088 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2089 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2090 
   (unspec [(const_int 0)] 687)]
2091 
  "TARGET_SPE"
2092 
  "evstddx %2,%0,%1"
2093 
  [(set_attr "type" "vecstore")
2094 
   (set_attr  "length" "4")])
2095 
 
2096 
(define_insn "spe_evstdh"
2097 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2098 
                           (match_operand:QI 1 "immediate_operand" "i")))
2099 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2100 
   (unspec [(const_int 0)] 688)]
2101 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2102 
  "evstdh %2,%1*8(%0)"
2103 
  [(set_attr "type" "vecstore")
2104 
   (set_attr  "length" "4")])
2105 
 
2106 
(define_insn "spe_evstdhx"
2107 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2108 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2109 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2110 
   (unspec [(const_int 0)] 689)]
2111 
  "TARGET_SPE"
2112 
  "evstdhx %2,%0,%1"
2113 
  [(set_attr "type" "vecstore")
2114 
   (set_attr  "length" "4")])
2115 
 
2116 
(define_insn "spe_evstdw"
2117 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2118 
                           (match_operand:QI 1 "immediate_operand" "i")))
2119 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2120 
   (unspec [(const_int 0)] 690)]
2121 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2122 
  "evstdw %2,%1*8(%0)"
2123 
  [(set_attr "type" "vecstore")
2124 
   (set_attr  "length" "4")])
2125 
 
2126 
(define_insn "spe_evstdwx"
2127 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2128 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2129 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2130 
   (unspec [(const_int 0)] 691)]
2131 
  "TARGET_SPE"
2132 
  "evstdwx %2,%0,%1"
2133 
  [(set_attr "type" "vecstore")
2134 
   (set_attr  "length" "4")])
2135 
 
2136 
(define_insn "spe_evstwhe"
2137 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2138 
                           (match_operand:QI 1 "immediate_operand" "i")))
2139 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2140 
   (unspec [(const_int 0)] 692)]
2141 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2142 
  "evstwhe %2,%1*4(%0)"
2143 
  [(set_attr "type" "vecstore")
2144 
   (set_attr  "length" "4")])
2145 
 
2146 
(define_insn "spe_evstwhex"
2147 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2148 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2149 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2150 
   (unspec [(const_int 0)] 693)]
2151 
  "TARGET_SPE"
2152 
  "evstwhex %2,%0,%1"
2153 
  [(set_attr "type" "vecstore")
2154 
   (set_attr  "length" "4")])
2155 
 
2156 
(define_insn "spe_evstwho"
2157 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2158 
                           (match_operand:QI 1 "immediate_operand" "i")))
2159 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2160 
   (unspec [(const_int 0)] 694)]
2161 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2162 
  "evstwho %2,%1*4(%0)"
2163 
  [(set_attr "type" "vecstore")
2164 
   (set_attr  "length" "4")])
2165 
 
2166 
(define_insn "spe_evstwhox"
2167 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2168 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2169 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2170 
   (unspec [(const_int 0)] 695)]
2171 
  "TARGET_SPE"
2172 
  "evstwhox %2,%0,%1"
2173 
  [(set_attr "type" "vecstore")
2174 
   (set_attr  "length" "4")])
2175 
 
2176 
(define_insn "spe_evstwwe"
2177 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2178 
                           (match_operand:QI 1 "immediate_operand" "i")))
2179 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2180 
   (unspec [(const_int 0)] 696)]
2181 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2182 
  "evstwwe %2,%1*4(%0)"
2183 
  [(set_attr "type" "vecstore")
2184 
   (set_attr  "length" "4")])
2185 
 
2186 
(define_insn "spe_evstwwex"
2187 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2188 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2189 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2190 
   (unspec [(const_int 0)] 697)]
2191 
  "TARGET_SPE"
2192 
  "evstwwex %2,%0,%1"
2193 
  [(set_attr "type" "vecstore")
2194 
   (set_attr  "length" "4")])
2195 
 
2196 
(define_insn "spe_evstwwo"
2197 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2198 
                           (match_operand:QI 1 "immediate_operand" "i")))
2199 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2200 
   (unspec [(const_int 0)] 698)]
2201 
  "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2202 
  "evstwwo %2,%1*4(%0)"
2203 
  [(set_attr "type" "vecstore")
2204 
   (set_attr  "length" "4")])
2205 
 
2206 
(define_insn "spe_evstwwox"
2207 
  [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2208 
                           (match_operand:SI 1 "gpc_reg_operand" "r")))
2209 
        (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2210 
   (unspec [(const_int 0)] 699)]
2211 
  "TARGET_SPE"
2212 
  "evstwwox %2,%0,%1"
2213 
  [(set_attr "type" "vecstore")
2214 
   (set_attr  "length" "4")])
2215 
 
2216 
;; Double-precision floating point instructions.
2217 
 
2218 
;; FIXME: Add o=r option.
2219 
(define_insn "*frob__"
2220 
  [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
2221 
        (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
2222 
  "(TARGET_E500_DOUBLE && mode == DFmode)
2223 
   || (TARGET_SPE && mode != DFmode)"
2224 
  "@
2225 
   evmergelo %0,%1,%L1
2226 
   evldd%X1 %0,%y1")
2227 
 
2228 
(define_insn "*frob_tf_ti"
2229 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2230 
        (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
2231 
  "TARGET_E500_DOUBLE"
2232 
  "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1"
2233 
  [(set_attr "length" "8")])
2234 
 
2235 
(define_insn "*frob__di_2"
2236 
  [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
2237 
        (match_operand:DI 1 "input_operand" "r,m"))]
2238 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2239 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2240 
  "@
2241 
   evmergelo %0,%1,%L1
2242 
   evldd%X1 %0,%y1")
2243 
 
2244 
(define_insn "*frob_tf_di_8_2"
2245 
  [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
2246 
        (match_operand:DI 1 "input_operand" "r,m"))]
2247 
  "TARGET_E500_DOUBLE"
2248 
  "@
2249 
   evmergelo %L0,%1,%L1
2250 
   evldd%X1 %L0,%y1")
2251 
 
2252 
(define_insn "*frob_di_"
2253 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2254 
        (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
2255 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2256 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2257 
  "evmergehi %0,%1,%1\;mr %L0,%1"
2258 
  [(set_attr "length" "8")])
2259 
 
2260 
(define_insn "*frob_ti_tf"
2261 
  [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
2262 
        (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
2263 
  "TARGET_E500_DOUBLE"
2264 
  "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2265 
  [(set_attr "length" "16")])
2266 
 
2267 
(define_insn "*frob___2"
2268 
  [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
2269 
        (match_operand:SPE64 1 "input_operand" "r,m"))]
2270 
  "(TARGET_E500_DOUBLE && mode == DFmode)
2271 
   || (TARGET_SPE && mode != DFmode)"
2272 
  "*
2273 
{
2274 
  switch (which_alternative)
2275 
    {
2276 
    default:
2277 
      gcc_unreachable ();
2278 
    case 0:
2279 
      return \"evmergehi %0,%1,%1\;mr %L0,%1\";
2280 
    case 1:
2281 
      /* If the address is not offsettable we need to load the whole
2282 
         doubleword into a 64-bit register and then copy the high word
2283 
         to form the correct output layout.  */
2284 
      if (!offsettable_nonstrict_memref_p (operands[1]))
2285 
        return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
2286 
      /* If the low-address word is used in the address, we must load
2287 
        it last.  Otherwise, load it first.  Note that we cannot have
2288 
        auto-increment in that case since the address register is
2289 
        known to be dead.  */
2290 
      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2291 
                             operands[1], 0))
2292 
        return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
2293 
      else
2294 
        return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
2295 
    }
2296 
}"
2297 
  [(set_attr "length" "8,8")])
2298 
 
2299 
; As the above, but TImode at offset 8.
2300 
(define_insn "*frob_ti__8_2"
2301 
  [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
2302 
        (match_operand:SPE64 1 "input_operand" "r,m"))]
2303 
  "(TARGET_E500_DOUBLE && mode == DFmode)
2304 
   || (TARGET_SPE && mode != DFmode)"
2305 
  "*
2306 
{
2307 
  switch (which_alternative)
2308 
    {
2309 
    default:
2310 
      gcc_unreachable ();
2311 
    case 0:
2312 
      return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\";
2313 
    case 1:
2314 
      if (!offsettable_nonstrict_memref_p (operands[1]))
2315 
        return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
2316 
      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2317 
                             operands[1], 0))
2318 
        return \"{l|lwz} %Z0,%L1\;{l|lwz} %Y0,%1\";
2319 
      else
2320 
        return \"{l%U1%X1|lwz%U1%X1} %Y0,%1\;{l|lwz} %Z0,%L1\";
2321 
    }
2322 
}"
2323 
  [(set_attr "length" "8,8")])
2324 
 
2325 
(define_insn "*frob_ti_tf_2"
2326 
  [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
2327 
        (match_operand:TF 1 "input_operand" "r"))]
2328 
  "TARGET_E500_DOUBLE"
2329 
  "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2330 
  [(set_attr "length" "16")])
2331 
 
2332 
(define_insn "*mov_si_e500_subreg0"
2333 
  [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
2334 
        (match_operand:SI 1 "input_operand" "r,m"))]
2335 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2336 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2337 
  "@
2338 
   evmergelo %0,%1,%0
2339 
   evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0"
2340 
  [(set_attr "length" "4,12")])
2341 
 
2342 
;; ??? Could use evstwwe for memory stores in some cases, depending on
2343 
;; the offset.
2344 
(define_insn "*mov_si_e500_subreg0_2"
2345 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2346 
        (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
2347 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2348 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2349 
  "@
2350 
   evmergehi %0,%0,%1
2351 
   evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0"
2352 
  [(set_attr "length" "4,8")])
2353 
 
2354 
(define_insn "*mov_si_e500_subreg4"
2355 
  [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
2356 
        (match_operand:SI 1 "input_operand" "r,m"))]
2357 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2358 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2359 
  "@
2360 
   mr %0,%1
2361 
   {l%U1%X1|lwz%U1%X1} %0,%1")
2362 
 
2363 
(define_insn "*mov_si_e500_subreg4_2"
2364 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2365 
        (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
2366 
  "(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
2367 
   || (TARGET_SPE && mode != DFmode && mode != TFmode)"
2368 
  "@
2369 
   mr %0,%1
2370 
   {st%U0%X0|stw%U0%X0} %1,%0")
2371 
 
2372 
(define_insn "*mov_sitf_e500_subreg8"
2373 
  [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
2374 
        (match_operand:SI 1 "input_operand" "r,m"))]
2375 
  "TARGET_E500_DOUBLE"
2376 
  "@
2377 
   evmergelo %L0,%1,%L0
2378 
   evmergelohi %L0,%L0,%L0\;{l%U1%X1|lwz%U1%X1} %L0,%1\;evmergelohi %L0,%L0,%L0"
2379 
  [(set_attr "length" "4,12")])
2380 
 
2381 
(define_insn "*mov_sitf_e500_subreg8_2"
2382 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2383 
        (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
2384 
  "TARGET_E500_DOUBLE"
2385 
  "@
2386 
   evmergehi %0,%0,%L1
2387 
   evmergelohi %L1,%L1,%L1\;{st%U0%X0|stw%U0%X0} %L1,%0"
2388 
  [(set_attr "length" "4,8")])
2389 
 
2390 
(define_insn "*mov_sitf_e500_subreg12"
2391 
  [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
2392 
        (match_operand:SI 1 "input_operand" "r,m"))]
2393 
  "TARGET_E500_DOUBLE"
2394 
  "@
2395 
   mr %L0,%1
2396 
   {l%U1%X1|lwz%U1%X1} %L0,%1")
2397 
 
2398 
(define_insn "*mov_sitf_e500_subreg12_2"
2399 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2400 
        (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
2401 
  "TARGET_E500_DOUBLE"
2402 
  "@
2403 
   mr %0,%L1
2404 
   {st%U0%X0|stw%U0%X0} %L1,%0")
2405 
 
2406 
;; FIXME: Allow r=CONST0.
2407 
(define_insn "*movdf_e500_double"
2408 
  [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
2409 
        (match_operand:DF 1 "input_operand" "r,m,r"))]
2410 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2411 
    && (gpc_reg_operand (operands[0], DFmode)
2412 
        || gpc_reg_operand (operands[1], DFmode))"
2413 
  "*
2414 
 {
2415 
   switch (which_alternative)
2416 
     {
2417 
     case 0:
2418 
       return \"evor %0,%1,%1\";
2419 
     case 1:
2420 
       return \"evldd%X1 %0,%y1\";
2421 
     case 2:
2422 
       return \"evstdd%X0 %1,%y0\";
2423 
     default:
2424 
       gcc_unreachable ();
2425 
     }
2426 
 }"
2427 
  [(set_attr "type" "*,vecload,vecstore")
2428 
   (set_attr "length" "*,*,*")])
2429 
 
2430 
(define_insn "spe_truncdfsf2"
2431 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2432 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2433 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2434 
  "efscfd %0,%1")
2435 
 
2436 
(define_insn "spe_absdf2"
2437 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2438 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2439 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2440 
  "efdabs %0,%1")
2441 
 
2442 
(define_insn "spe_nabsdf2"
2443 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2444 
        (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2445 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2446 
  "efdnabs %0,%1")
2447 
 
2448 
(define_insn "spe_negdf2"
2449 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2450 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2451 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2452 
  "efdneg %0,%1")
2453 
 
2454 
(define_insn "spe_adddf3"
2455 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2456 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2457 
                 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2458 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2459 
  "efdadd %0,%1,%2")
2460 
 
2461 
(define_insn "spe_subdf3"
2462 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2463 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2464 
                  (match_operand:DF 2 "gpc_reg_operand" "r")))]
2465 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2466 
  "efdsub %0,%1,%2")
2467 
 
2468 
(define_insn "spe_muldf3"
2469 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2470 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2471 
                 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2472 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2473 
  "efdmul %0,%1,%2")
2474 
 
2475 
(define_insn "spe_divdf3"
2476 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2477 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2478 
                (match_operand:DF 2 "gpc_reg_operand" "r")))]
2479 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2480 
  "efddiv %0,%1,%2")
2481 
 
2482 
;; Double-precision floating point instructions for IBM long double.
2483 
 
2484 
(define_insn_and_split "spe_trunctfdf2_internal1"
2485 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
2486 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
2487 
  "!TARGET_IEEEQUAD
2488 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2489 
  "@
2490 
   #
2491 
   evor %0,%1,%1"
2492 
  "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
2493 
  [(const_int 0)]
2494 
{
2495 
  emit_note (NOTE_INSN_DELETED);
2496 
  DONE;
2497 
})
2498 
 
2499 
(define_insn_and_split "spe_trunctfsf2"
2500 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2501 
        (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
2502 
   (clobber (match_scratch:DF 2 "=r"))]
2503 
  "!TARGET_IEEEQUAD
2504 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2505 
  "#"
2506 
  "&& reload_completed"
2507 
  [(set (match_dup 2)
2508 
        (float_truncate:DF (match_dup 1)))
2509 
   (set (match_dup 0)
2510 
        (float_truncate:SF (match_dup 2)))]
2511 
  "")
2512 
 
2513 
(define_insn "spe_extenddftf2"
2514 
  [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
2515 
        (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
2516 
   (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
2517 
  "!TARGET_IEEEQUAD
2518 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2519 
  "@
2520 
   evxor %L0,%L0,%L0
2521 
   evor %0,%1,%1\;evxor %L0,%L0,%L0
2522 
   evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
2523 
   evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
2524 
  [(set_attr "length" "4,8,8,12")])
2525 
 
2526 
(define_expand "spe_fix_trunctfsi2"
2527 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2528 
                   (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
2529 
              (clobber (match_dup 2))
2530 
              (clobber (match_dup 3))
2531 
              (clobber (match_dup 4))])]
2532 
  "!TARGET_IEEEQUAD
2533 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2534 
{
2535 
  operands[2] = gen_reg_rtx (DFmode);
2536 
  operands[3] = gen_reg_rtx (SImode);
2537 
  operands[4] = gen_reg_rtx (SImode);
2538 
})
2539 
 
2540 
; Like fix_trunc_helper, add with rounding towards 0.
2541 
(define_insn "spe_fix_trunctfsi2_internal"
2542 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2543 
        (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
2544 
   (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
2545 
   (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
2546 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
2547 
  "!TARGET_IEEEQUAD
2548 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2549 
  "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
2550 
  [(set_attr "length" "24")])
2551 
 
2552 
(define_insn "spe_negtf2_internal"
2553 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2554 
        (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
2555 
  "!TARGET_IEEEQUAD
2556 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2557 
  "*
2558 
{
2559 
  if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2560 
    return \"efdneg %L0,%L1\;efdneg %0,%1\";
2561 
  else
2562 
    return \"efdneg %0,%1\;efdneg %L0,%L1\";
2563 
}"
2564 
  [(set_attr "length" "8")])
2565 
 
2566 
(define_expand "spe_abstf2_cmp"
2567 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2568 
        (match_operand:TF 1 "gpc_reg_operand" "f"))
2569 
   (set (match_dup 3) (match_dup 5))
2570 
   (set (match_dup 5) (abs:DF (match_dup 5)))
2571 
   (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2572 
                                                  (match_dup 5))] CMPDFEQ_GPR))
2573 
   (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2574 
                           (label_ref (match_operand 2 "" ""))
2575 
                           (pc)))
2576 
   (set (match_dup 6) (neg:DF (match_dup 6)))]
2577 
  "!TARGET_IEEEQUAD
2578 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2579 
  "
2580 
{
2581 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2582 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2583 
  operands[3] = gen_reg_rtx (DFmode);
2584 
  operands[4] = gen_reg_rtx (CCFPmode);
2585 
  operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2586 
  operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2587 
}")
2588 
 
2589 
(define_expand "spe_abstf2_tst"
2590 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2591 
        (match_operand:TF 1 "gpc_reg_operand" "f"))
2592 
   (set (match_dup 3) (match_dup 5))
2593 
   (set (match_dup 5) (abs:DF (match_dup 5)))
2594 
   (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2595 
                                                  (match_dup 5))] TSTDFEQ_GPR))
2596 
   (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2597 
                           (label_ref (match_operand 2 "" ""))
2598 
                           (pc)))
2599 
   (set (match_dup 6) (neg:DF (match_dup 6)))]
2600 
  "!TARGET_IEEEQUAD
2601 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2602 
  "
2603 
{
2604 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2605 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2606 
  operands[3] = gen_reg_rtx (DFmode);
2607 
  operands[4] = gen_reg_rtx (CCFPmode);
2608 
  operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2609 
  operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2610 
}")
2611 
 
2612 
;; Vector move instructions.
2613 
 
2614 
(define_expand "movv2si"
2615 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2616 
        (match_operand:V2SI 1 "any_operand" ""))]
2617 
  "TARGET_SPE"
2618 
  "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2619 
 
2620 
(define_insn "*movv2si_internal"
2621 
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2622 
        (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
2623 
  "TARGET_SPE
2624 
   && (gpc_reg_operand (operands[0], V2SImode)
2625 
       || gpc_reg_operand (operands[1], V2SImode))"
2626 
  "*
2627 
{
2628 
  switch (which_alternative)
2629 
    {
2630 
    case 0: return \"evstdd%X0 %1,%y0\";
2631 
    case 1: return \"evldd%X1 %0,%y1\";
2632 
    case 2: return \"evor %0,%1,%1\";
2633 
    case 3: return output_vec_const_move (operands);
2634 
    default: gcc_unreachable ();
2635 
    }
2636 
}"
2637 
  [(set_attr "type" "vecload,vecstore,*,*")
2638 
   (set_attr "length" "*,*,*,12")])
2639 
 
2640 
(define_split
2641 
  [(set (match_operand:V2SI 0 "register_operand" "")
2642 
        (match_operand:V2SI 1 "zero_constant" ""))]
2643 
  "TARGET_SPE && reload_completed"
2644 
  [(set (match_dup 0)
2645 
        (xor:V2SI (match_dup 0) (match_dup 0)))]
2646 
  "")
2647 
 
2648 
(define_expand "movv1di"
2649 
  [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2650 
        (match_operand:V1DI 1 "any_operand" ""))]
2651 
  "TARGET_SPE"
2652 
  "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2653 
 
2654 
(define_insn "*movv1di_internal"
2655 
  [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2656 
        (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
2657 
  "TARGET_SPE
2658 
   && (gpc_reg_operand (operands[0], V1DImode)
2659 
       || gpc_reg_operand (operands[1], V1DImode))"
2660 
  "@
2661 
   evstdd%X0 %1,%y0
2662 
   evldd%X1 %0,%y1
2663 
   evor %0,%1,%1
2664 
   evxor %0,%0,%0"
2665 
  [(set_attr "type" "vecload,vecstore,*,*")
2666 
   (set_attr "length" "*,*,*,*")])
2667 
 
2668 
(define_expand "movv4hi"
2669 
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2670 
        (match_operand:V4HI 1 "any_operand" ""))]
2671 
  "TARGET_SPE"
2672 
  "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2673 
 
2674 
(define_insn "*movv4hi_internal"
2675 
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
2676 
        (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
2677 
  "TARGET_SPE
2678 
   && (gpc_reg_operand (operands[0], V4HImode)
2679 
       || gpc_reg_operand (operands[1], V4HImode))"
2680 
  "@
2681 
   evstdd%X0 %1,%y0
2682 
   evldd%X1 %0,%y1
2683 
   evor %0,%1,%1
2684 
   evxor %0,%0,%0"
2685 
  [(set_attr "type" "vecload")])
2686 
 
2687 
(define_expand "movv2sf"
2688 
  [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2689 
        (match_operand:V2SF 1 "any_operand" ""))]
2690 
  "TARGET_SPE || TARGET_PAIRED_FLOAT"
2691 
  "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2692 
 
2693 
(define_insn "*movv2sf_internal"
2694 
  [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2695 
        (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
2696 
  "TARGET_SPE
2697 
   && (gpc_reg_operand (operands[0], V2SFmode)
2698 
       || gpc_reg_operand (operands[1], V2SFmode))"
2699 
  "@
2700 
   evstdd%X0 %1,%y0
2701 
   evldd%X1 %0,%y1
2702 
   evor %0,%1,%1
2703 
   evxor %0,%0,%0"
2704 
  [(set_attr "type" "vecload,vecstore,*,*")
2705 
   (set_attr "length" "*,*,*,*")])
2706 
 
2707 
;; End of vector move instructions.
2708 
 
2709 
(define_insn "spe_evmwhssfaa"
2710 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2711 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2712 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2713 
   (clobber (reg:SI SPEFSCR_REGNO))
2714 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2715 
  "TARGET_SPE"
2716 
  "evmwhssfaa %0,%1,%2"
2717 
  [(set_attr "type" "veccomplex")
2718 
   (set_attr  "length" "4")])
2719 
 
2720 
(define_insn "spe_evmwhssmaa"
2721 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2722 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2723 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2724 
   (clobber (reg:SI SPEFSCR_REGNO))
2725 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2726 
  "TARGET_SPE"
2727 
  "evmwhssmaa %0,%1,%2"
2728 
  [(set_attr "type" "veccomplex")
2729 
   (set_attr  "length" "4")])
2730 
 
2731 
(define_insn "spe_evmwhsmfaa"
2732 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2733 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2734 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
2735 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2736 
  "TARGET_SPE"
2737 
  "evmwhsmfaa %0,%1,%2"
2738 
  [(set_attr "type" "veccomplex")
2739 
   (set_attr  "length" "4")])
2740 
 
2741 
(define_insn "spe_evmwhsmiaa"
2742 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2743 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2744 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
2745 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2746 
  "TARGET_SPE"
2747 
  "evmwhsmiaa %0,%1,%2"
2748 
  [(set_attr "type" "veccomplex")
2749 
   (set_attr  "length" "4")])
2750 
 
2751 
(define_insn "spe_evmwhusiaa"
2752 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2753 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2754 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2755 
   (clobber (reg:SI SPEFSCR_REGNO))
2756 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2757 
  "TARGET_SPE"
2758 
  "evmwhusiaa %0,%1,%2"
2759 
  [(set_attr "type" "veccomplex")
2760 
   (set_attr  "length" "4")])
2761 
 
2762 
(define_insn "spe_evmwhumiaa"
2763 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2764 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2765 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
2766 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2767 
  "TARGET_SPE"
2768 
  "evmwhumiaa %0,%1,%2"
2769 
  [(set_attr "type" "veccomplex")
2770 
   (set_attr  "length" "4")])
2771 
 
2772 
(define_insn "spe_evmwhssfan"
2773 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2774 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2775 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2776 
   (clobber (reg:SI SPEFSCR_REGNO))
2777 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2778 
  "TARGET_SPE"
2779 
  "evmwhssfan %0,%1,%2"
2780 
  [(set_attr "type" "veccomplex")
2781 
   (set_attr  "length" "4")])
2782 
 
2783 
(define_insn "spe_evmwhssian"
2784 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2785 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2786 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2787 
   (clobber (reg:SI SPEFSCR_REGNO))
2788 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2789 
  "TARGET_SPE"
2790 
  "evmwhssian %0,%1,%2"
2791 
  [(set_attr "type" "veccomplex")
2792 
   (set_attr  "length" "4")])
2793 
 
2794 
(define_insn "spe_evmwhsmfan"
2795 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2796 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2797 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
2798 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2799 
  "TARGET_SPE"
2800 
  "evmwhsmfan %0,%1,%2"
2801 
  [(set_attr "type" "veccomplex")
2802 
   (set_attr  "length" "4")])
2803 
 
2804 
(define_insn "spe_evmwhsmian"
2805 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2806 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2807 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
2808 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2809 
  "TARGET_SPE"
2810 
  "evmwhsmian %0,%1,%2"
2811 
  [(set_attr "type" "veccomplex")
2812 
   (set_attr  "length" "4")])
2813 
 
2814 
(define_insn "spe_evmwhumian"
2815 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2816 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2817 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
2818 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2819 
  "TARGET_SPE"
2820 
  "evmwhumian %0,%1,%2"
2821 
  [(set_attr "type" "veccomplex")
2822 
   (set_attr  "length" "4")])
2823 
 
2824 
(define_insn "spe_evmwhgssfaa"
2825 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2826 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2827 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2828 
   (clobber (reg:SI SPEFSCR_REGNO))
2829 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2830 
  "TARGET_SPE"
2831 
  "evmwhgssfaa %0,%1,%2"
2832 
  [(set_attr "type" "veccomplex")
2833 
   (set_attr  "length" "4")])
2834 
 
2835 
(define_insn "spe_evmwhgsmfaa"
2836 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2837 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2838 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
2839 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2840 
  "TARGET_SPE"
2841 
  "evmwhgsmfaa %0,%1,%2"
2842 
  [(set_attr "type" "veccomplex")
2843 
   (set_attr  "length" "4")])
2844 
 
2845 
(define_insn "spe_evmwhgsmiaa"
2846 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2847 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2848 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
2849 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2850 
  "TARGET_SPE"
2851 
  "evmwhgsmiaa %0,%1,%2"
2852 
  [(set_attr "type" "veccomplex")
2853 
   (set_attr  "length" "4")])
2854 
 
2855 
(define_insn "spe_evmwhgumiaa"
2856 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2857 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2858 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
2859 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2860 
  "TARGET_SPE"
2861 
  "evmwhgumiaa %0,%1,%2"
2862 
  [(set_attr "type" "veccomplex")
2863 
   (set_attr  "length" "4")])
2864 
 
2865 
(define_insn "spe_evmwhgssfan"
2866 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2867 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2868 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2869 
   (clobber (reg:SI SPEFSCR_REGNO))
2870 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2871 
  "TARGET_SPE"
2872 
  "evmwhgssfan %0,%1,%2"
2873 
  [(set_attr "type" "veccomplex")
2874 
   (set_attr  "length" "4")])
2875 
 
2876 
(define_insn "spe_evmwhgsmfan"
2877 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2878 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2879 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
2880 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2881 
  "TARGET_SPE"
2882 
  "evmwhgsmfan %0,%1,%2"
2883 
  [(set_attr "type" "veccomplex")
2884 
   (set_attr  "length" "4")])
2885 
 
2886 
(define_insn "spe_evmwhgsmian"
2887 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2888 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2889 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
2890 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2891 
  "TARGET_SPE"
2892 
  "evmwhgsmian %0,%1,%2"
2893 
  [(set_attr "type" "veccomplex")
2894 
   (set_attr  "length" "4")])
2895 
 
2896 
(define_insn "spe_evmwhgumian"
2897 
  [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2898 
        (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2899 
                      (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
2900 
   (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI  [(const_int 0)] 0))]
2901 
  "TARGET_SPE"
2902 
  "evmwhgumian %0,%1,%2"
2903 
  [(set_attr "type" "veccomplex")
2904 
   (set_attr  "length" "4")])
2905 
 
2906 
(define_insn "spe_mtspefscr"
2907 
  [(set (reg:SI SPEFSCR_REGNO)
2908 
        (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2909 
                            722))]
2910 
  "TARGET_SPE"
2911 
  "mtspefscr %0"
2912 
  [(set_attr "type" "vecsimple")])
2913 
 
2914 
(define_insn "spe_mfspefscr"
2915 
  [(set (match_operand:SI 0 "register_operand" "=r")
2916 
        (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2917 
  "TARGET_SPE"
2918 
  "mfspefscr %0"
2919 
  [(set_attr "type" "vecsimple")])
2920 
 
2921 
;; FP comparison stuff.
2922 
 
2923 
;; Flip the GT bit.
2924 
(define_insn "e500_flip_gt_bit"
2925 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2926 
        (unspec:CCFP
2927 
         [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2928 
  "!TARGET_FPRS && TARGET_HARD_FLOAT"
2929 
  "*
2930 
{
2931 
  return output_e500_flip_gt_bit (operands[0], operands[1]);
2932 
}"
2933 
  [(set_attr "type" "cr_logical")])
2934 
 
2935 
;; MPC8540 single-precision FP instructions on GPRs.
2936 
;; We have 2 variants for each.  One for IEEE compliant math and one
2937 
;; for non IEEE compliant math.
2938 
 
2939 
(define_insn "cmpsfeq_gpr"
2940 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2941 
        (unspec:CCFP
2942 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2943 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2944 
         1000))]
2945 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
2946 
   && !(flag_finite_math_only && !flag_trapping_math)"
2947 
  "efscmpeq %0,%1,%2"
2948 
  [(set_attr "type" "veccmp")])
2949 
 
2950 
(define_insn "tstsfeq_gpr"
2951 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2952 
        (unspec:CCFP
2953 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2954 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2955 
         1001))]
2956 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
2957 
   && flag_finite_math_only && !flag_trapping_math"
2958 
  "efststeq %0,%1,%2"
2959 
  [(set_attr "type" "veccmpsimple")])
2960 
 
2961 
(define_insn "cmpsfgt_gpr"
2962 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2963 
        (unspec:CCFP
2964 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2965 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2966 
         1002))]
2967 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
2968 
   && !(flag_finite_math_only && !flag_trapping_math)"
2969 
  "efscmpgt %0,%1,%2"
2970 
  [(set_attr "type" "veccmp")])
2971 
 
2972 
(define_insn "tstsfgt_gpr"
2973 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2974 
        (unspec:CCFP
2975 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2976 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2977 
         1003))]
2978 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
2979 
   && flag_finite_math_only && !flag_trapping_math"
2980 
  "efststgt %0,%1,%2"
2981 
  [(set_attr "type" "veccmpsimple")])
2982 
 
2983 
(define_insn "cmpsflt_gpr"
2984 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2985 
        (unspec:CCFP
2986 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2987 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2988 
         1004))]
2989 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
2990 
   && !(flag_finite_math_only && !flag_trapping_math)"
2991 
  "efscmplt %0,%1,%2"
2992 
  [(set_attr "type" "veccmp")])
2993 
 
2994 
(define_insn "tstsflt_gpr"
2995 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2996 
        (unspec:CCFP
2997 
         [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2998 
                        (match_operand:SF 2 "gpc_reg_operand" "r"))]
2999 
         1005))]
3000 
  "TARGET_HARD_FLOAT && !TARGET_FPRS
3001 
   && flag_finite_math_only && !flag_trapping_math"
3002 
  "efststlt %0,%1,%2"
3003 
  [(set_attr "type" "veccmpsimple")])
3004 
 
3005 
;; Same thing, but for double-precision.
3006 
 
3007 
(define_insn "cmpdfeq_gpr"
3008 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3009 
        (unspec:CCFP
3010 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3011 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3012 
         CMPDFEQ_GPR))]
3013 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3014 
   && !(flag_finite_math_only && !flag_trapping_math)"
3015 
  "efdcmpeq %0,%1,%2"
3016 
  [(set_attr "type" "veccmp")])
3017 
 
3018 
(define_insn "tstdfeq_gpr"
3019 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3020 
        (unspec:CCFP
3021 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3022 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3023 
         TSTDFEQ_GPR))]
3024 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3025 
   && flag_finite_math_only && !flag_trapping_math"
3026 
  "efdtsteq %0,%1,%2"
3027 
  [(set_attr "type" "veccmpsimple")])
3028 
 
3029 
(define_insn "cmpdfgt_gpr"
3030 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3031 
        (unspec:CCFP
3032 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3033 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3034 
         CMPDFGT_GPR))]
3035 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3036 
   && !(flag_finite_math_only && !flag_trapping_math)"
3037 
  "efdcmpgt %0,%1,%2"
3038 
  [(set_attr "type" "veccmp")])
3039 
 
3040 
(define_insn "tstdfgt_gpr"
3041 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3042 
        (unspec:CCFP
3043 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3044 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3045 
         TSTDFGT_GPR))]
3046 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3047 
   && flag_finite_math_only && !flag_trapping_math"
3048 
  "efdtstgt %0,%1,%2"
3049 
  [(set_attr "type" "veccmpsimple")])
3050 
 
3051 
(define_insn "cmpdflt_gpr"
3052 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3053 
        (unspec:CCFP
3054 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3055 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3056 
         CMPDFLT_GPR))]
3057 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3058 
   && !(flag_finite_math_only && !flag_trapping_math)"
3059 
  "efdcmplt %0,%1,%2"
3060 
  [(set_attr "type" "veccmp")])
3061 
 
3062 
(define_insn "tstdflt_gpr"
3063 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3064 
        (unspec:CCFP
3065 
         [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3066 
                        (match_operand:DF 2 "gpc_reg_operand" "r"))]
3067 
         TSTDFLT_GPR))]
3068 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
3069 
   && flag_finite_math_only && !flag_trapping_math"
3070 
  "efdtstlt %0,%1,%2"
3071 
  [(set_attr "type" "veccmpsimple")])
3072 
 
3073 
;; Same thing, but for IBM long double.
3074 
 
3075 
(define_insn "cmptfeq_gpr"
3076 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3077 
        (unspec:CCFP
3078 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3079 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3080 
         CMPTFEQ_GPR))]
3081 
  "!TARGET_IEEEQUAD
3082 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3083 
   && !(flag_finite_math_only && !flag_trapping_math)"
3084 
  "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
3085 
  [(set_attr "type" "veccmp")
3086 
   (set_attr "length" "12")])
3087 
 
3088 
(define_insn "tsttfeq_gpr"
3089 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3090 
        (unspec:CCFP
3091 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3092 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3093 
         TSTTFEQ_GPR))]
3094 
  "!TARGET_IEEEQUAD
3095 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3096 
   && flag_finite_math_only && !flag_trapping_math"
3097 
  "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
3098 
  [(set_attr "type" "veccmpsimple")
3099 
   (set_attr "length" "12")])
3100 
 
3101 
(define_insn "cmptfgt_gpr"
3102 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3103 
        (unspec:CCFP
3104 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3105 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3106 
         CMPTFGT_GPR))]
3107 
  "!TARGET_IEEEQUAD
3108 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3109 
   && !(flag_finite_math_only && !flag_trapping_math)"
3110 
  "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
3111 
  [(set_attr "type" "veccmp")
3112 
   (set_attr "length" "20")])
3113 
 
3114 
(define_insn "tsttfgt_gpr"
3115 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3116 
        (unspec:CCFP
3117 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3118 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3119 
         TSTTFGT_GPR))]
3120 
  "!TARGET_IEEEQUAD
3121 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3122 
   && flag_finite_math_only && !flag_trapping_math"
3123 
  "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
3124 
  [(set_attr "type" "veccmpsimple")
3125 
   (set_attr "length" "20")])
3126 
 
3127 
(define_insn "cmptflt_gpr"
3128 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3129 
        (unspec:CCFP
3130 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3131 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3132 
         CMPTFLT_GPR))]
3133 
  "!TARGET_IEEEQUAD
3134 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3135 
   && !(flag_finite_math_only && !flag_trapping_math)"
3136 
  "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
3137 
  [(set_attr "type" "veccmp")
3138 
   (set_attr "length" "20")])
3139 
 
3140 
(define_insn "tsttflt_gpr"
3141 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3142 
        (unspec:CCFP
3143 
         [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3144 
                        (match_operand:TF 2 "gpc_reg_operand" "r"))]
3145 
         TSTTFLT_GPR))]
3146 
  "!TARGET_IEEEQUAD
3147 
   && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3148 
   && flag_finite_math_only && !flag_trapping_math"
3149 
  "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
3150 
  [(set_attr "type" "veccmpsimple")
3151 
   (set_attr "length" "20")])
3152 
 
3153 
;; Like cceq_ior_compare, but compare the GT bits.
3154 
(define_insn "e500_cr_ior_compare"
3155 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3156 
        (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
3157 
                      (match_operand 2 "cc_reg_operand" "y")]
3158 
                     E500_CR_IOR_COMPARE))]
3159 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
3160 
  "cror 4*%0+gt,4*%1+gt,4*%2+gt"
3161 
  [(set_attr "type" "cr_logical")])
3162 
 
3163 
;; Out-of-line prologues and epilogues.
3164 
(define_insn "*save_gpregs_spe"
3165 
  [(match_parallel 0 "any_parallel_operand"
3166 
                   [(clobber (reg:P 65))
3167 
                    (use (match_operand:P 1 "symbol_ref_operand" "s"))
3168 
                    (use (reg:P 11))
3169 
                    (set (match_operand:V2SI 2 "memory_operand" "=m")
3170 
                         (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
3171 
  "TARGET_SPE_ABI"
3172 
  "bl %z1"
3173 
  [(set_attr "type" "branch")
3174 
   (set_attr "length" "4")])
3175 
 
3176 
(define_insn "*restore_gpregs_spe"
3177 
 [(match_parallel 0 "any_parallel_operand"
3178 
                  [(clobber (reg:P 65))
3179 
                   (use (match_operand:P 1 "symbol_ref_operand" "s"))
3180 
                   (use (reg:P 11))
3181 
                   (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3182 
                        (match_operand:V2SI 3 "memory_operand" "m"))])]
3183 
 "TARGET_SPE_ABI"
3184 
 "bl %z1"
3185 
 [(set_attr "type" "branch")
3186 
  (set_attr "length" "4")])
3187 
 
3188 
(define_insn "*return_and_restore_gpregs_spe"
3189 
 [(match_parallel 0 "any_parallel_operand"
3190 
                  [(return)
3191 
                   (clobber (reg:P 65))
3192 
                   (use (match_operand:P 1 "symbol_ref_operand" "s"))
3193 
                   (use (reg:P 11))
3194 
                   (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
3195 
                        (match_operand:V2SI 3 "memory_operand" "m"))])]
3196 
 "TARGET_SPE_ABI"
3197 
 "b %z1"
3198 
 [(set_attr "type" "branch")
3199 
  (set_attr "length" "4")])

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.