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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rs6000/] [sync.md] - Blame information for rev 709

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1 709 jeremybenn
;; Machine description for PowerPC synchronization instructions.
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;; Copyright (C) 2005, 2007, 2008, 2009, 2011
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;; Free Software Foundation, Inc.
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;; Contributed by Geoffrey Keating.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
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(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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  [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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(define_code_attr fetchop_pred
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  [(plus "add_operand") (minus "gpc_reg_operand")
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   (ior "logical_operand") (xor "logical_operand") (and "and_operand")])
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(define_expand "mem_thread_fence"
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  [(match_operand:SI 0 "const_int_operand" "")]         ;; model
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  ""
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{
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  enum memmodel model = (enum memmodel) INTVAL (operands[0]);
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  switch (model)
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    {
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    case MEMMODEL_RELAXED:
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      break;
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    case MEMMODEL_CONSUME:
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    case MEMMODEL_ACQUIRE:
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    case MEMMODEL_RELEASE:
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    case MEMMODEL_ACQ_REL:
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      emit_insn (gen_lwsync ());
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      break;
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    case MEMMODEL_SEQ_CST:
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      emit_insn (gen_hwsync ());
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      break;
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    default:
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      gcc_unreachable ();
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    }
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  DONE;
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})
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(define_expand "hwsync"
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  [(set (match_dup 0)
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        (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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  ""
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{
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  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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  MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*hwsync"
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  [(set (match_operand:BLK 0 "" "")
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        (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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  ""
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  "{dcs|sync}"
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  [(set_attr "type" "sync")])
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(define_expand "lwsync"
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  [(set (match_dup 0)
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        (unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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  ""
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{
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  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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  MEM_VOLATILE_P (operands[0]) = 1;
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})
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(define_insn "*lwsync"
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  [(set (match_operand:BLK 0 "" "")
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        (unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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  ""
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{
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  /* Some AIX assemblers don't accept lwsync, so we use a .long.  */
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  if (TARGET_NO_LWSYNC)
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    return "sync";
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  else if (TARGET_LWSYNC_INSTRUCTION)
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    return "lwsync";
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  else
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    return ".long 0x7c2004ac";
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}
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  [(set_attr "type" "sync")])
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(define_insn "isync"
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  [(unspec_volatile:BLK [(const_int 0)] UNSPECV_ISYNC)]
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  ""
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  "{ics|isync}"
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  [(set_attr "type" "isync")])
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;; The control dependency used for load dependency described
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;; in B.2.3 of the Power ISA 2.06B.
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(define_insn "loadsync"
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  [(unspec_volatile:BLK [(match_operand 0 "register_operand" "r")]
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                        UNSPECV_ISYNC)
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   (clobber (match_scratch:CC 1 "=y"))]
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  ""
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  "cmpw %1,%0,%0\;bne- %1,$+4\;isync"
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  [(set_attr "type" "isync")
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   (set_attr "length" "12")])
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(define_expand "atomic_load"
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  [(set (match_operand:INT 0 "register_operand" "")             ;; output
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        (match_operand:INT 1 "memory_operand" ""))              ;; memory
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   (use (match_operand:SI 2 "const_int_operand" ""))]           ;; model
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  ""
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{
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  enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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121
  if (model == MEMMODEL_SEQ_CST)
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    emit_insn (gen_hwsync ());
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124
  emit_move_insn (operands[0], operands[1]);
125
 
126
  switch (model)
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    {
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    case MEMMODEL_RELAXED:
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      break;
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    case MEMMODEL_CONSUME:
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    case MEMMODEL_ACQUIRE:
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    case MEMMODEL_SEQ_CST:
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      emit_insn (gen_loadsync (operands[0]));
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      break;
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    default:
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      gcc_unreachable ();
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    }
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  DONE;
139
})
140
 
141
(define_expand "atomic_store"
142
  [(set (match_operand:INT 0 "memory_operand" "")               ;; memory
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        (match_operand:INT 1 "register_operand" ""))            ;; input
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   (use (match_operand:SI 2 "const_int_operand" ""))]           ;; model
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  ""
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{
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  enum memmodel model = (enum memmodel) INTVAL (operands[2]);
148
  switch (model)
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    {
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    case MEMMODEL_RELAXED:
151
      break;
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    case MEMMODEL_RELEASE:
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      emit_insn (gen_lwsync ());
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      break;
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    case MEMMODEL_SEQ_CST:
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      emit_insn (gen_hwsync ());
157
      break;
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    default:
159
      gcc_unreachable ();
160
    }
161
  emit_move_insn (operands[0], operands[1]);
162
  DONE;
163
})
164
 
165
;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve
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;; opcode that is "phased-in".  Not implemented as of Power7, so not yet used,
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;; but let's prepare the macros anyway.
168
 
169
(define_mode_iterator ATOMIC    [SI (DI "TARGET_64BIT")])
170
 
171
(define_insn "load_locked"
172
  [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r")
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        (unspec_volatile:ATOMIC
174
         [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
175
  "TARGET_POWERPC"
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  " %0,%y1"
177
  [(set_attr "type" "load_l")])
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179
(define_insn "store_conditional"
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
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        (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
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   (set (match_operand:ATOMIC 1 "memory_operand" "=Z")
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        (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))]
184
  "TARGET_POWERPC"
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  " %2,%y1"
186
  [(set_attr "type" "store_c")])
187
 
188
(define_expand "atomic_compare_and_swap"
189
  [(match_operand:SI 0 "gpc_reg_operand" "")            ;; bool out
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   (match_operand:INT1 1 "gpc_reg_operand" "")          ;; val out
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   (match_operand:INT1 2 "memory_operand" "")           ;; memory
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   (match_operand:INT1 3 "reg_or_short_operand" "")     ;; expected
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   (match_operand:INT1 4 "gpc_reg_operand" "")          ;; desired
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   (match_operand:SI 5 "const_int_operand" "")          ;; is_weak
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   (match_operand:SI 6 "const_int_operand" "")          ;; model succ
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   (match_operand:SI 7 "const_int_operand" "")]         ;; model fail
197
  "TARGET_POWERPC"
198
{
199
  rs6000_expand_atomic_compare_and_swap (operands);
200
  DONE;
201
})
202
 
203
(define_expand "atomic_exchange"
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  [(match_operand:INT1 0 "gpc_reg_operand" "")          ;; output
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   (match_operand:INT1 1 "memory_operand" "")           ;; memory
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   (match_operand:INT1 2 "gpc_reg_operand" "")          ;; input
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   (match_operand:SI 3 "const_int_operand" "")]         ;; model
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  "TARGET_POWERPC"
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{
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  rs6000_expand_atomic_exchange (operands);
211
  DONE;
212
})
213
 
214
(define_expand "atomic_"
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  [(match_operand:INT1 0 "memory_operand" "")           ;; memory
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   (FETCHOP:INT1 (match_dup 0)
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     (match_operand:INT1 1 "" ""))      ;; operand
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   (match_operand:SI 2 "const_int_operand" "")]         ;; model
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  "TARGET_POWERPC"
220
{
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  rs6000_expand_atomic_op (, operands[0], operands[1],
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                           NULL_RTX, NULL_RTX, operands[2]);
223
  DONE;
224
})
225
 
226
(define_expand "atomic_nand"
227
  [(match_operand:INT1 0 "memory_operand" "")           ;; memory
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   (match_operand:INT1 1 "gpc_reg_operand" "")          ;; operand
229
   (match_operand:SI 2 "const_int_operand" "")]         ;; model
230
  "TARGET_POWERPC"
231
{
232
  rs6000_expand_atomic_op (NOT, operands[0], operands[1],
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                           NULL_RTX, NULL_RTX, operands[2]);
234
  DONE;
235
})
236
 
237
(define_expand "atomic_fetch_"
238
  [(match_operand:INT1 0 "gpc_reg_operand" "")          ;; output
239
   (match_operand:INT1 1 "memory_operand" "")           ;; memory
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   (FETCHOP:INT1 (match_dup 1)
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     (match_operand:INT1 2 "" ""))      ;; operand
242
   (match_operand:SI 3 "const_int_operand" "")]         ;; model
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  "TARGET_POWERPC"
244
{
245
  rs6000_expand_atomic_op (, operands[1], operands[2],
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                           operands[0], NULL_RTX, operands[3]);
247
  DONE;
248
})
249
 
250
(define_expand "atomic_fetch_nand"
251
  [(match_operand:INT1 0 "gpc_reg_operand" "")          ;; output
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   (match_operand:INT1 1 "memory_operand" "")           ;; memory
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   (match_operand:INT1 2 "gpc_reg_operand" "")          ;; operand
254
   (match_operand:SI 3 "const_int_operand" "")]         ;; model
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  "TARGET_POWERPC"
256
{
257
  rs6000_expand_atomic_op (NOT, operands[1], operands[2],
258
                           operands[0], NULL_RTX, operands[3]);
259
  DONE;
260
})
261
 
262
(define_expand "atomic__fetch"
263
  [(match_operand:INT1 0 "gpc_reg_operand" "")          ;; output
264
   (match_operand:INT1 1 "memory_operand" "")           ;; memory
265
   (FETCHOP:INT1 (match_dup 1)
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     (match_operand:INT1 2 "" ""))      ;; operand
267
   (match_operand:SI 3 "const_int_operand" "")]         ;; model
268
  "TARGET_POWERPC"
269
{
270
  rs6000_expand_atomic_op (, operands[1], operands[2],
271
                           NULL_RTX, operands[0], operands[3]);
272
  DONE;
273
})
274
 
275
(define_expand "atomic_nand_fetch"
276
  [(match_operand:INT1 0 "gpc_reg_operand" "")          ;; output
277
   (match_operand:INT1 1 "memory_operand" "")           ;; memory
278
   (match_operand:INT1 2 "gpc_reg_operand" "")          ;; operand
279
   (match_operand:SI 3 "const_int_operand" "")]         ;; model
280
  "TARGET_POWERPC"
281
{
282
  rs6000_expand_atomic_op (NOT, operands[1], operands[2],
283
                           NULL_RTX, operands[0], operands[3]);
284
  DONE;
285
})

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