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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [rx/] [predicates.md] - Blame information for rev 709

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1 709 jeremybenn
;; Predicate definitions for Renesas RX.
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;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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;; Check that the operand is suitable for a call insn.
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;; Only registers and symbol refs are allowed.
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(define_predicate "rx_call_operand"
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  (match_code "symbol_ref,reg")
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)
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;; For sibcall operations we can only use a symbolic address.
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(define_predicate "rx_symbolic_call_operand"
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  (match_code "symbol_ref")
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)
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;; Check that the operand is suitable for a shift insn
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;; Only small integers or a value in a register are permitted.
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(define_predicate "rx_shift_operand"
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  (ior (match_operand 0 "register_operand")
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       (and (match_code "const_int")
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            (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
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)
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(define_predicate "rx_constshift_operand"
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  (and (match_code "const_int")
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       (match_test "IN_RANGE (INTVAL (op), 0, 31)"))
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)
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(define_predicate "rx_restricted_mem_operand"
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  (and (match_code "mem")
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       (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)"))
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)
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;; Check that the operand is suitable as the source operand
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;; for a logic or arithmeitc instruction.  Registers, integers
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;; and a restricted subset of memory addresses are allowed.
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(define_predicate "rx_source_operand"
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  (ior (match_operand 0 "register_operand")
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       (match_operand 0 "immediate_operand")
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       (match_operand 0 "rx_restricted_mem_operand"))
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)
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;; Check that the operand is suitable as the source operand
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;; for a comparison instruction.  This is the same as
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;; rx_source_operand except that SUBREGs are allowed but
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;; CONST_INTs are not.
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(define_predicate "rx_compare_operand"
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  (ior (match_operand 0 "register_operand")
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       (match_operand 0 "rx_restricted_mem_operand"))
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)
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;; Check that the operand is suitable as the source operand
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;; for a min/max instruction.  This is the same as
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;; rx_source_operand except that CONST_INTs are allowed but
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;; REGs and SUBREGs are not.
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(define_predicate "rx_minmaxex_operand"
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  (ior (match_operand 0 "immediate_operand")
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       (match_operand 0 "rx_restricted_mem_operand"))
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)
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;; Return true if OP is a store multiple operation.  This looks like:
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;;
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;;   [(set (SP) (MINUS (SP) (INT)))
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;;    (set (MEM (SP)) (REG))
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;;    (set (MEM (MINUS (SP) (INT))) (REG)) {optionally repeated}
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;;   ]
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(define_special_predicate "rx_store_multiple_vector"
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  (match_code "parallel")
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{
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  int count = XVECLEN (op, 0);
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  unsigned int src_regno;
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  rtx element;
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  int i;
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  /* Perform a quick check so we don't blow up below.  */
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  if (count <= 2)
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    return false;
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  /* Check that the first element of the vector is the stack adjust.  */
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  element = XVECEXP (op, 0, 0);
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  if (   ! SET_P (element)
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      || ! REG_P (SET_DEST (element))
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      ||   REGNO (SET_DEST (element)) != SP_REG
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      ||   GET_CODE (SET_SRC (element)) != MINUS
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      || ! REG_P (XEXP (SET_SRC (element), 0))
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      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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    return false;
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  /* Check that the next element is the first push.  */
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  element = XVECEXP (op, 0, 1);
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  if (   ! SET_P (element)
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      || ! REG_P (SET_SRC (element))
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      || GET_MODE (SET_SRC (element)) != SImode
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      || ! MEM_P (SET_DEST (element))
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      || GET_MODE (SET_DEST (element)) != SImode
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      || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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      || ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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      ||   REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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      || ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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      || INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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        != GET_MODE_SIZE (SImode))
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    return false;
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130
  src_regno = REGNO (SET_SRC (element));
131
 
132
  /* Check that the remaining elements use SP-
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     addressing and decreasing register numbers.  */
134
  for (i = 2; i < count; i++)
135
    {
136
      element = XVECEXP (op, 0, i);
137
 
138
      if (   ! SET_P (element)
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          || ! REG_P (SET_SRC (element))
140
          || GET_MODE (SET_SRC (element)) != SImode
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          || REGNO (SET_SRC (element)) != src_regno - (i - 1)
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          || ! MEM_P (SET_DEST (element))
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          || GET_MODE (SET_DEST (element)) != SImode
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          || GET_CODE (XEXP (SET_DEST (element), 0)) != MINUS
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          || ! REG_P (XEXP (XEXP (SET_DEST (element), 0), 0))
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          ||   REGNO (XEXP (XEXP (SET_DEST (element), 0), 0)) != SP_REG
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          || ! CONST_INT_P (XEXP (XEXP (SET_DEST (element), 0), 1))
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          || INTVAL (XEXP (XEXP (SET_DEST (element), 0), 1))
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             != i * GET_MODE_SIZE (SImode))
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        return false;
151
    }
152
  return true;
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})
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;; Return true if OP is a load multiple operation.
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;; This looks like:
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;;  [(set (SP) (PLUS (SP) (INT)))
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;;   (set (REG) (MEM (SP)))
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;;   (set (REG) (MEM (PLUS (SP) (INT)))) {optionally repeated}
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;;  ]
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162
(define_special_predicate "rx_load_multiple_vector"
163
  (match_code "parallel")
164
{
165
  int count = XVECLEN (op, 0);
166
  unsigned int dest_regno;
167
  rtx element;
168
  int i;
169
 
170
  /* Perform a quick check so we don't blow up below.  */
171
  if (count <= 2)
172
    return false;
173
 
174
  /* Check that the first element of the vector is the stack adjust.  */
175
  element = XVECEXP (op, 0, 0);
176
  if (   ! SET_P (element)
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      || ! REG_P (SET_DEST (element))
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      ||   REGNO (SET_DEST (element)) != SP_REG
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      ||   GET_CODE (SET_SRC (element)) != PLUS
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      || ! REG_P (XEXP (SET_SRC (element), 0))
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      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
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      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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    return false;
184
 
185
  /* Check that the next element is the first push.  */
186
  element = XVECEXP (op, 0, 1);
187
  if (   ! SET_P (element)
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      || ! REG_P (SET_DEST (element))
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      || ! MEM_P (SET_SRC (element))
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      || ! REG_P (XEXP (SET_SRC (element), 0))
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      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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    return false;
193
 
194
  dest_regno = REGNO (SET_DEST (element));
195
 
196
  /* Check that the remaining elements use SP+
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     addressing and incremental register numbers.  */
198
  for (i = 2; i < count; i++)
199
    {
200
      element = XVECEXP (op, 0, i);
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202
      if (   ! SET_P (element)
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          || ! REG_P (SET_DEST (element))
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          || GET_MODE (SET_DEST (element)) != SImode
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          || REGNO (SET_DEST (element)) != dest_regno + (i - 1)
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          || ! MEM_P (SET_SRC (element))
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          || GET_MODE (SET_SRC (element)) != SImode
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          || GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
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          || ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
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          ||   REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
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          || ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
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          || INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
213
             != (i - 1) * GET_MODE_SIZE (SImode))
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        return false;
215
    }
216
  return true;
217
})
218
 
219
;; Return true if OP is a pop-and-return load multiple operation.
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;; This looks like:
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;;  [(set (SP) (PLUS (SP) (INT)))
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;;   (set (REG) (MEM (SP)))
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;;   (set (REG) (MEM (PLUS (SP) (INT)))) {optional and possibly repeated}
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;;   (return)
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;;  ]
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(define_special_predicate "rx_rtsd_vector"
228
  (match_code "parallel")
229
{
230
  int count = XVECLEN (op, 0);
231
  unsigned int dest_regno;
232
  rtx element;
233
  int i;
234
 
235
  /* Perform a quick check so we don't blow up below.  */
236
  if (count <= 2)
237
    return false;
238
 
239
  /* Check that the first element of the vector is the stack adjust.  */
240
  element = XVECEXP (op, 0, 0);
241
  if (   ! SET_P (element)
242
      || ! REG_P (SET_DEST (element))
243
      ||   REGNO (SET_DEST (element)) != SP_REG
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      ||   GET_CODE (SET_SRC (element)) != PLUS
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      || ! REG_P (XEXP (SET_SRC (element), 0))
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      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG
247
      || ! CONST_INT_P (XEXP (SET_SRC (element), 1)))
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    return false;
249
 
250
  /* Check that the next element is the first push.  */
251
  element = XVECEXP (op, 0, 1);
252
  if (   ! SET_P (element)
253
      || ! REG_P (SET_DEST (element))
254
      || ! MEM_P (SET_SRC (element))
255
      || ! REG_P (XEXP (SET_SRC (element), 0))
256
      ||   REGNO (XEXP (SET_SRC (element), 0)) != SP_REG)
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    return false;
258
 
259
  dest_regno = REGNO (SET_DEST (element));
260
 
261
  /* Check that the remaining elements, if any, and except
262
     for the last one, use SP+ addressing and incremental
263
     register numbers.  */
264
  for (i = 2; i < count - 1; i++)
265
    {
266
      element = XVECEXP (op, 0, i);
267
 
268
      if (   ! SET_P (element)
269
          || ! REG_P (SET_DEST (element))
270
          || GET_MODE (SET_DEST (element)) != SImode
271
          || REGNO (SET_DEST (element)) != dest_regno + (i - 1)
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          || ! MEM_P (SET_SRC (element))
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          || GET_MODE (SET_SRC (element)) != SImode
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          || GET_CODE (XEXP (SET_SRC (element), 0)) != PLUS
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          || ! REG_P (XEXP (XEXP (SET_SRC (element), 0), 0))
276
          ||   REGNO (XEXP (XEXP (SET_SRC (element), 0), 0)) != SP_REG
277
          || ! CONST_INT_P (XEXP (XEXP (SET_SRC (element), 0), 1))
278
          || INTVAL (XEXP (XEXP (SET_SRC (element), 0), 1))
279
             != (i - 1) * GET_MODE_SIZE (SImode))
280
        return false;
281
    }
282
 
283
  /* The last element must be a RETURN.  */
284
  element = XVECEXP (op, 0, count - 1);
285
  return GET_CODE (element) == RETURN;
286
})
287
 
288
(define_predicate "label_ref_operand"
289
  (match_code "label_ref")
290
)
291
 
292
(define_predicate "rx_z_comparison_operator"
293
  (match_code "eq,ne")
294
)
295
 
296
(define_predicate "rx_zs_comparison_operator"
297
  (match_code "eq,ne,lt,ge")
298
)
299
 
300
;; GT and LE omitted due to operand swap required.
301
(define_predicate "rx_fp_comparison_operator"
302
  (match_code "eq,ne,lt,ge,ordered,unordered")
303
)
304
 
305
(define_predicate "rshift_operator"
306
  (match_code "ashiftrt,lshiftrt")
307
)

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