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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [s390/] [s390.c] - Blame information for rev 717

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1 709 jeremybenn 
/* Subroutines used for code generation on IBM S/390 and zSeries
2 
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 
   2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4 
   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 
                  Ulrich Weigand (uweigand@de.ibm.com) and
6 
                  Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 
 
8 
This file is part of GCC.
9 
 
10 
GCC is free software; you can redistribute it and/or modify it under
11 
the terms of the GNU General Public License as published by the Free
12 
Software Foundation; either version 3, or (at your option) any later
13 
version.
14 
 
15 
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 
WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18 
for more details.
19 
 
20 
You should have received a copy of the GNU General Public License
21 
along with GCC; see the file COPYING3.  If not see
22 
<http://www.gnu.org/licenses/>.  */
23 
 
24 
#include "config.h"
25 
#include "system.h"
26 
#include "coretypes.h"
27 
#include "tm.h"
28 
#include "rtl.h"
29 
#include "tree.h"
30 
#include "tm_p.h"
31 
#include "regs.h"
32 
#include "hard-reg-set.h"
33 
#include "insn-config.h"
34 
#include "conditions.h"
35 
#include "output.h"
36 
#include "insn-attr.h"
37 
#include "flags.h"
38 
#include "except.h"
39 
#include "function.h"
40 
#include "recog.h"
41 
#include "expr.h"
42 
#include "reload.h"
43 
#include "diagnostic-core.h"
44 
#include "basic-block.h"
45 
#include "integrate.h"
46 
#include "ggc.h"
47 
#include "target.h"
48 
#include "target-def.h"
49 
#include "debug.h"
50 
#include "langhooks.h"
51 
#include "optabs.h"
52 
#include "gimple.h"
53 
#include "df.h"
54 
#include "params.h"
55 
#include "cfgloop.h"
56 
#include "opts.h"
57 
 
58 
/* Define the specific costs for a given cpu.  */
59 
 
60 
struct processor_costs
61 
{
62 
  /* multiplication */
63 
  const int m;        /* cost of an M instruction.  */
64 
  const int mghi;     /* cost of an MGHI instruction.  */
65 
  const int mh;       /* cost of an MH instruction.  */
66 
  const int mhi;      /* cost of an MHI instruction.  */
67 
  const int ml;       /* cost of an ML instruction.  */
68 
  const int mr;       /* cost of an MR instruction.  */
69 
  const int ms;       /* cost of an MS instruction.  */
70 
  const int msg;      /* cost of an MSG instruction.  */
71 
  const int msgf;     /* cost of an MSGF instruction.  */
72 
  const int msgfr;    /* cost of an MSGFR instruction.  */
73 
  const int msgr;     /* cost of an MSGR instruction.  */
74 
  const int msr;      /* cost of an MSR instruction.  */
75 
  const int mult_df;  /* cost of multiplication in DFmode.  */
76 
  const int mxbr;
77 
  /* square root */
78 
  const int sqxbr;    /* cost of square root in TFmode.  */
79 
  const int sqdbr;    /* cost of square root in DFmode.  */
80 
  const int sqebr;    /* cost of square root in SFmode.  */
81 
  /* multiply and add */
82 
  const int madbr;    /* cost of multiply and add in DFmode.  */
83 
  const int maebr;    /* cost of multiply and add in SFmode.  */
84 
  /* division */
85 
  const int dxbr;
86 
  const int ddbr;
87 
  const int debr;
88 
  const int dlgr;
89 
  const int dlr;
90 
  const int dr;
91 
  const int dsgfr;
92 
  const int dsgr;
93 
};
94 
 
95 
const struct processor_costs *s390_cost;
96 
 
97 
static const
98 
struct processor_costs z900_cost =
99 
{
100 
  COSTS_N_INSNS (5),     /* M     */
101 
  COSTS_N_INSNS (10),    /* MGHI  */
102 
  COSTS_N_INSNS (5),     /* MH    */
103 
  COSTS_N_INSNS (4),     /* MHI   */
104 
  COSTS_N_INSNS (5),     /* ML    */
105 
  COSTS_N_INSNS (5),     /* MR    */
106 
  COSTS_N_INSNS (4),     /* MS    */
107 
  COSTS_N_INSNS (15),    /* MSG   */
108 
  COSTS_N_INSNS (7),     /* MSGF  */
109 
  COSTS_N_INSNS (7),     /* MSGFR */
110 
  COSTS_N_INSNS (10),    /* MSGR  */
111 
  COSTS_N_INSNS (4),     /* MSR   */
112 
  COSTS_N_INSNS (7),     /* multiplication in DFmode */
113 
  COSTS_N_INSNS (13),    /* MXBR */
114 
  COSTS_N_INSNS (136),   /* SQXBR */
115 
  COSTS_N_INSNS (44),    /* SQDBR */
116 
  COSTS_N_INSNS (35),    /* SQEBR */
117 
  COSTS_N_INSNS (18),    /* MADBR */
118 
  COSTS_N_INSNS (13),    /* MAEBR */
119 
  COSTS_N_INSNS (134),   /* DXBR */
120 
  COSTS_N_INSNS (30),    /* DDBR */
121 
  COSTS_N_INSNS (27),    /* DEBR */
122 
  COSTS_N_INSNS (220),   /* DLGR */
123 
  COSTS_N_INSNS (34),    /* DLR */
124 
  COSTS_N_INSNS (34),    /* DR */
125 
  COSTS_N_INSNS (32),    /* DSGFR */
126 
  COSTS_N_INSNS (32),    /* DSGR */
127 
};
128 
 
129 
static const
130 
struct processor_costs z990_cost =
131 
{
132 
  COSTS_N_INSNS (4),     /* M     */
133 
  COSTS_N_INSNS (2),     /* MGHI  */
134 
  COSTS_N_INSNS (2),     /* MH    */
135 
  COSTS_N_INSNS (2),     /* MHI   */
136 
  COSTS_N_INSNS (4),     /* ML    */
137 
  COSTS_N_INSNS (4),     /* MR    */
138 
  COSTS_N_INSNS (5),     /* MS    */
139 
  COSTS_N_INSNS (6),     /* MSG   */
140 
  COSTS_N_INSNS (4),     /* MSGF  */
141 
  COSTS_N_INSNS (4),     /* MSGFR */
142 
  COSTS_N_INSNS (4),     /* MSGR  */
143 
  COSTS_N_INSNS (4),     /* MSR   */
144 
  COSTS_N_INSNS (1),     /* multiplication in DFmode */
145 
  COSTS_N_INSNS (28),    /* MXBR */
146 
  COSTS_N_INSNS (130),   /* SQXBR */
147 
  COSTS_N_INSNS (66),    /* SQDBR */
148 
  COSTS_N_INSNS (38),    /* SQEBR */
149 
  COSTS_N_INSNS (1),     /* MADBR */
150 
  COSTS_N_INSNS (1),     /* MAEBR */
151 
  COSTS_N_INSNS (60),    /* DXBR */
152 
  COSTS_N_INSNS (40),    /* DDBR */
153 
  COSTS_N_INSNS (26),    /* DEBR */
154 
  COSTS_N_INSNS (176),   /* DLGR */
155 
  COSTS_N_INSNS (31),    /* DLR */
156 
  COSTS_N_INSNS (31),    /* DR */
157 
  COSTS_N_INSNS (31),    /* DSGFR */
158 
  COSTS_N_INSNS (31),    /* DSGR */
159 
};
160 
 
161 
static const
162 
struct processor_costs z9_109_cost =
163 
{
164 
  COSTS_N_INSNS (4),     /* M     */
165 
  COSTS_N_INSNS (2),     /* MGHI  */
166 
  COSTS_N_INSNS (2),     /* MH    */
167 
  COSTS_N_INSNS (2),     /* MHI   */
168 
  COSTS_N_INSNS (4),     /* ML    */
169 
  COSTS_N_INSNS (4),     /* MR    */
170 
  COSTS_N_INSNS (5),     /* MS    */
171 
  COSTS_N_INSNS (6),     /* MSG   */
172 
  COSTS_N_INSNS (4),     /* MSGF  */
173 
  COSTS_N_INSNS (4),     /* MSGFR */
174 
  COSTS_N_INSNS (4),     /* MSGR  */
175 
  COSTS_N_INSNS (4),     /* MSR   */
176 
  COSTS_N_INSNS (1),     /* multiplication in DFmode */
177 
  COSTS_N_INSNS (28),    /* MXBR */
178 
  COSTS_N_INSNS (130),   /* SQXBR */
179 
  COSTS_N_INSNS (66),    /* SQDBR */
180 
  COSTS_N_INSNS (38),    /* SQEBR */
181 
  COSTS_N_INSNS (1),     /* MADBR */
182 
  COSTS_N_INSNS (1),     /* MAEBR */
183 
  COSTS_N_INSNS (60),    /* DXBR */
184 
  COSTS_N_INSNS (40),    /* DDBR */
185 
  COSTS_N_INSNS (26),    /* DEBR */
186 
  COSTS_N_INSNS (30),    /* DLGR */
187 
  COSTS_N_INSNS (23),    /* DLR */
188 
  COSTS_N_INSNS (23),    /* DR */
189 
  COSTS_N_INSNS (24),    /* DSGFR */
190 
  COSTS_N_INSNS (24),    /* DSGR */
191 
};
192 
 
193 
static const
194 
struct processor_costs z10_cost =
195 
{
196 
  COSTS_N_INSNS (10),    /* M     */
197 
  COSTS_N_INSNS (10),    /* MGHI  */
198 
  COSTS_N_INSNS (10),    /* MH    */
199 
  COSTS_N_INSNS (10),    /* MHI   */
200 
  COSTS_N_INSNS (10),    /* ML    */
201 
  COSTS_N_INSNS (10),    /* MR    */
202 
  COSTS_N_INSNS (10),    /* MS    */
203 
  COSTS_N_INSNS (10),    /* MSG   */
204 
  COSTS_N_INSNS (10),    /* MSGF  */
205 
  COSTS_N_INSNS (10),    /* MSGFR */
206 
  COSTS_N_INSNS (10),    /* MSGR  */
207 
  COSTS_N_INSNS (10),    /* MSR   */
208 
  COSTS_N_INSNS (1) ,    /* multiplication in DFmode */
209 
  COSTS_N_INSNS (50),    /* MXBR */
210 
  COSTS_N_INSNS (120),   /* SQXBR */
211 
  COSTS_N_INSNS (52),    /* SQDBR */
212 
  COSTS_N_INSNS (38),    /* SQEBR */
213 
  COSTS_N_INSNS (1),     /* MADBR */
214 
  COSTS_N_INSNS (1),     /* MAEBR */
215 
  COSTS_N_INSNS (111),   /* DXBR */
216 
  COSTS_N_INSNS (39),    /* DDBR */
217 
  COSTS_N_INSNS (32),    /* DEBR */
218 
  COSTS_N_INSNS (160),   /* DLGR */
219 
  COSTS_N_INSNS (71),    /* DLR */
220 
  COSTS_N_INSNS (71),    /* DR */
221 
  COSTS_N_INSNS (71),    /* DSGFR */
222 
  COSTS_N_INSNS (71),    /* DSGR */
223 
};
224 
 
225 
static const
226 
struct processor_costs z196_cost =
227 
{
228 
  COSTS_N_INSNS (7),     /* M     */
229 
  COSTS_N_INSNS (5),     /* MGHI  */
230 
  COSTS_N_INSNS (5),     /* MH    */
231 
  COSTS_N_INSNS (5),     /* MHI   */
232 
  COSTS_N_INSNS (7),     /* ML    */
233 
  COSTS_N_INSNS (7),     /* MR    */
234 
  COSTS_N_INSNS (6),     /* MS    */
235 
  COSTS_N_INSNS (8),     /* MSG   */
236 
  COSTS_N_INSNS (6),     /* MSGF  */
237 
  COSTS_N_INSNS (6),     /* MSGFR */
238 
  COSTS_N_INSNS (8),     /* MSGR  */
239 
  COSTS_N_INSNS (6),     /* MSR   */
240 
  COSTS_N_INSNS (1) ,    /* multiplication in DFmode */
241 
  COSTS_N_INSNS (40),    /* MXBR B+40 */
242 
  COSTS_N_INSNS (100),   /* SQXBR B+100 */
243 
  COSTS_N_INSNS (42),    /* SQDBR B+42 */
244 
  COSTS_N_INSNS (28),    /* SQEBR B+28 */
245 
  COSTS_N_INSNS (1),     /* MADBR B */
246 
  COSTS_N_INSNS (1),     /* MAEBR B */
247 
  COSTS_N_INSNS (101),   /* DXBR B+101 */
248 
  COSTS_N_INSNS (29),    /* DDBR */
249 
  COSTS_N_INSNS (22),    /* DEBR */
250 
  COSTS_N_INSNS (160),   /* DLGR cracked */
251 
  COSTS_N_INSNS (160),   /* DLR cracked */
252 
  COSTS_N_INSNS (160),   /* DR expanded */
253 
  COSTS_N_INSNS (160),   /* DSGFR cracked */
254 
  COSTS_N_INSNS (160),   /* DSGR cracked */
255 
};
256 
 
257 
extern int reload_completed;
258 
 
259 
/* Kept up to date using the SCHED_VARIABLE_ISSUE hook.  */
260 
static rtx last_scheduled_insn;
261 
 
262 
/* Structure used to hold the components of a S/390 memory
263 
   address.  A legitimate address on S/390 is of the general
264 
   form
265 
          base + index + displacement
266 
   where any of the components is optional.
267 
 
268 
   base and index are registers of the class ADDR_REGS,
269 
   displacement is an unsigned 12-bit immediate constant.  */
270 
 
271 
struct s390_address
272 
{
273 
  rtx base;
274 
  rtx indx;
275 
  rtx disp;
276 
  bool pointer;
277 
  bool literal_pool;
278 
};
279 
 
280 
/* The following structure is embedded in the machine
281 
   specific part of struct function.  */
282 
 
283 
struct GTY (()) s390_frame_layout
284 
{
285 
  /* Offset within stack frame.  */
286 
  HOST_WIDE_INT gprs_offset;
287 
  HOST_WIDE_INT f0_offset;
288 
  HOST_WIDE_INT f4_offset;
289 
  HOST_WIDE_INT f8_offset;
290 
  HOST_WIDE_INT backchain_offset;
291 
 
292 
  /* Number of first and last gpr where slots in the register
293 
     save area are reserved for.  */
294 
  int first_save_gpr_slot;
295 
  int last_save_gpr_slot;
296 
 
297 
  /* Number of first and last gpr to be saved, restored.  */
298 
  int first_save_gpr;
299 
  int first_restore_gpr;
300 
  int last_save_gpr;
301 
  int last_restore_gpr;
302 
 
303 
  /* Bits standing for floating point registers. Set, if the
304 
     respective register has to be saved. Starting with reg 16 (f0)
305 
     at the rightmost bit.
306 
     Bit 15 -  8  7  6  5  4  3  2  1  0
307 
     fpr 15 -  8  7  5  3  1  6  4  2  0
308 
     reg 31 - 24 23 22 21 20 19 18 17 16  */
309 
  unsigned int fpr_bitmap;
310 
 
311 
  /* Number of floating point registers f8-f15 which must be saved.  */
312 
  int high_fprs;
313 
 
314 
  /* Set if return address needs to be saved.
315 
     This flag is set by s390_return_addr_rtx if it could not use
316 
     the initial value of r14 and therefore depends on r14 saved
317 
     to the stack.  */
318 
  bool save_return_addr_p;
319 
 
320 
  /* Size of stack frame.  */
321 
  HOST_WIDE_INT frame_size;
322 
};
323 
 
324 
/* Define the structure for the machine field in struct function.  */
325 
 
326 
struct GTY(()) machine_function
327 
{
328 
  struct s390_frame_layout frame_layout;
329 
 
330 
  /* Literal pool base register.  */
331 
  rtx base_reg;
332 
 
333 
  /* True if we may need to perform branch splitting.  */
334 
  bool split_branches_pending_p;
335 
 
336 
  /* Some local-dynamic TLS symbol name.  */
337 
  const char *some_ld_name;
338 
 
339 
  bool has_landing_pad_p;
340 
};
341 
 
342 
/* Few accessor macros for struct cfun->machine->s390_frame_layout.  */
343 
 
344 
#define cfun_frame_layout (cfun->machine->frame_layout)
345 
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
346 
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot -           \
347 
  cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
348 
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |=    \
349 
  (1 << (BITNUM)))
350 
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap &    \
351 
  (1 << (BITNUM))))
352 
 
353 
/* Number of GPRs and FPRs used for argument passing.  */
354 
#define GP_ARG_NUM_REG 5
355 
#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
356 
 
357 
/* A couple of shortcuts.  */
358 
#define CONST_OK_FOR_J(x) \
359 
        CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
360 
#define CONST_OK_FOR_K(x) \
361 
        CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
362 
#define CONST_OK_FOR_Os(x) \
363 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
364 
#define CONST_OK_FOR_Op(x) \
365 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
366 
#define CONST_OK_FOR_On(x) \
367 
        CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
368 
 
369 
#define REGNO_PAIR_OK(REGNO, MODE)                               \
370 
  (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
371 
 
372 
/* That's the read ahead of the dynamic branch prediction unit in
373 
   bytes on a z10 (or higher) CPU.  */
374 
#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
375 
 
376 
/* Return the alignment for LABEL.  We default to the -falign-labels
377 
   value except for the literal pool base label.  */
378 
int
379 
s390_label_align (rtx label)
380 
{
381 
  rtx prev_insn = prev_active_insn (label);
382 
 
383 
  if (prev_insn == NULL_RTX)
384 
    goto old;
385 
 
386 
  prev_insn = single_set (prev_insn);
387 
 
388 
  if (prev_insn == NULL_RTX)
389 
    goto old;
390 
 
391 
  prev_insn = SET_SRC (prev_insn);
392 
 
393 
  /* Don't align literal pool base labels.  */
394 
  if (GET_CODE (prev_insn) == UNSPEC
395 
      && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
396 
    return 0;
397 
 
398 
 old:
399 
  return align_labels_log;
400 
}
401 
 
402 
static enum machine_mode
403 
s390_libgcc_cmp_return_mode (void)
404 
{
405 
  return TARGET_64BIT ? DImode : SImode;
406 
}
407 
 
408 
static enum machine_mode
409 
s390_libgcc_shift_count_mode (void)
410 
{
411 
  return TARGET_64BIT ? DImode : SImode;
412 
}
413 
 
414 
static enum machine_mode
415 
s390_unwind_word_mode (void)
416 
{
417 
  return TARGET_64BIT ? DImode : SImode;
418 
}
419 
 
420 
/* Return true if the back end supports mode MODE.  */
421 
static bool
422 
s390_scalar_mode_supported_p (enum machine_mode mode)
423 
{
424 
  /* In contrast to the default implementation reject TImode constants on 31bit
425 
     TARGET_ZARCH for ABI compliance.  */
426 
  if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
427 
    return false;
428 
 
429 
  if (DECIMAL_FLOAT_MODE_P (mode))
430 
    return default_decimal_float_supported_p ();
431 
 
432 
  return default_scalar_mode_supported_p (mode);
433 
}
434 
 
435 
/* Set the has_landing_pad_p flag in struct machine_function to VALUE.  */
436 
 
437 
void
438 
s390_set_has_landing_pad_p (bool value)
439 
{
440 
  cfun->machine->has_landing_pad_p = value;
441 
}
442 
 
443 
/* If two condition code modes are compatible, return a condition code
444 
   mode which is compatible with both.  Otherwise, return
445 
   VOIDmode.  */
446 
 
447 
static enum machine_mode
448 
s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
449 
{
450 
  if (m1 == m2)
451 
    return m1;
452 
 
453 
  switch (m1)
454 
    {
455 
    case CCZmode:
456 
      if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
457 
          || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
458 
        return m2;
459 
      return VOIDmode;
460 
 
461 
    case CCSmode:
462 
    case CCUmode:
463 
    case CCTmode:
464 
    case CCSRmode:
465 
    case CCURmode:
466 
    case CCZ1mode:
467 
      if (m2 == CCZmode)
468 
        return m1;
469 
 
470 
      return VOIDmode;
471 
 
472 
    default:
473 
      return VOIDmode;
474 
    }
475 
  return VOIDmode;
476 
}
477 
 
478 
/* Return true if SET either doesn't set the CC register, or else
479 
   the source and destination have matching CC modes and that
480 
   CC mode is at least as constrained as REQ_MODE.  */
481 
 
482 
static bool
483 
s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
484 
{
485 
  enum machine_mode set_mode;
486 
 
487 
  gcc_assert (GET_CODE (set) == SET);
488 
 
489 
  if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
490 
    return 1;
491 
 
492 
  set_mode = GET_MODE (SET_DEST (set));
493 
  switch (set_mode)
494 
    {
495 
    case CCSmode:
496 
    case CCSRmode:
497 
    case CCUmode:
498 
    case CCURmode:
499 
    case CCLmode:
500 
    case CCL1mode:
501 
    case CCL2mode:
502 
    case CCL3mode:
503 
    case CCT1mode:
504 
    case CCT2mode:
505 
    case CCT3mode:
506 
      if (req_mode != set_mode)
507 
        return 0;
508 
      break;
509 
 
510 
    case CCZmode:
511 
      if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
512 
          && req_mode != CCSRmode && req_mode != CCURmode)
513 
        return 0;
514 
      break;
515 
 
516 
    case CCAPmode:
517 
    case CCANmode:
518 
      if (req_mode != CCAmode)
519 
        return 0;
520 
      break;
521 
 
522 
    default:
523 
      gcc_unreachable ();
524 
    }
525 
 
526 
  return (GET_MODE (SET_SRC (set)) == set_mode);
527 
}
528 
 
529 
/* Return true if every SET in INSN that sets the CC register
530 
   has source and destination with matching CC modes and that
531 
   CC mode is at least as constrained as REQ_MODE.
532 
   If REQ_MODE is VOIDmode, always return false.  */
533 
 
534 
bool
535 
s390_match_ccmode (rtx insn, enum machine_mode req_mode)
536 
{
537 
  int i;
538 
 
539 
  /* s390_tm_ccmode returns VOIDmode to indicate failure.  */
540 
  if (req_mode == VOIDmode)
541 
    return false;
542 
 
543 
  if (GET_CODE (PATTERN (insn)) == SET)
544 
    return s390_match_ccmode_set (PATTERN (insn), req_mode);
545 
 
546 
  if (GET_CODE (PATTERN (insn)) == PARALLEL)
547 
      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
548 
        {
549 
          rtx set = XVECEXP (PATTERN (insn), 0, i);
550 
          if (GET_CODE (set) == SET)
551 
            if (!s390_match_ccmode_set (set, req_mode))
552 
              return false;
553 
        }
554 
 
555 
  return true;
556 
}
557 
 
558 
/* If a test-under-mask instruction can be used to implement
559 
   (compare (and ... OP1) OP2), return the CC mode required
560 
   to do that.  Otherwise, return VOIDmode.
561 
   MIXED is true if the instruction can distinguish between
562 
   CC1 and CC2 for mixed selected bits (TMxx), it is false
563 
   if the instruction cannot (TM).  */
564 
 
565 
enum machine_mode
566 
s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
567 
{
568 
  int bit0, bit1;
569 
 
570 
  /* ??? Fixme: should work on CONST_DOUBLE as well.  */
571 
  if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
572 
    return VOIDmode;
573 
 
574 
  /* Selected bits all zero: CC0.
575 
     e.g.: int a; if ((a & (16 + 128)) == 0) */
576 
  if (INTVAL (op2) == 0)
577 
    return CCTmode;
578 
 
579 
  /* Selected bits all one: CC3.
580 
     e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
581 
  if (INTVAL (op2) == INTVAL (op1))
582 
    return CCT3mode;
583 
 
584 
  /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
585 
     int a;
586 
     if ((a & (16 + 128)) == 16)         -> CCT1
587 
     if ((a & (16 + 128)) == 128)        -> CCT2  */
588 
  if (mixed)
589 
    {
590 
      bit1 = exact_log2 (INTVAL (op2));
591 
      bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
592 
      if (bit0 != -1 && bit1 != -1)
593 
        return bit0 > bit1 ? CCT1mode : CCT2mode;
594 
    }
595 
 
596 
  return VOIDmode;
597 
}
598 
 
599 
/* Given a comparison code OP (EQ, NE, etc.) and the operands
600 
   OP0 and OP1 of a COMPARE, return the mode to be used for the
601 
   comparison.  */
602 
 
603 
enum machine_mode
604 
s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
605 
{
606 
  switch (code)
607 
    {
608 
      case EQ:
609 
      case NE:
610 
        if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
611 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
612 
          return CCAPmode;
613 
        if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
614 
            && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
615 
          return CCAPmode;
616 
        if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
617 
             || GET_CODE (op1) == NEG)
618 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
619 
          return CCLmode;
620 
 
621 
        if (GET_CODE (op0) == AND)
622 
          {
623 
            /* Check whether we can potentially do it via TM.  */
624 
            enum machine_mode ccmode;
625 
            ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
626 
            if (ccmode != VOIDmode)
627 
              {
628 
                /* Relax CCTmode to CCZmode to allow fall-back to AND
629 
                   if that turns out to be beneficial.  */
630 
                return ccmode == CCTmode ? CCZmode : ccmode;
631 
              }
632 
          }
633 
 
634 
        if (register_operand (op0, HImode)
635 
            && GET_CODE (op1) == CONST_INT
636 
            && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
637 
          return CCT3mode;
638 
        if (register_operand (op0, QImode)
639 
            && GET_CODE (op1) == CONST_INT
640 
            && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
641 
          return CCT3mode;
642 
 
643 
        return CCZmode;
644 
 
645 
      case LE:
646 
      case LT:
647 
      case GE:
648 
      case GT:
649 
        /* The only overflow condition of NEG and ABS happens when
650 
           -INT_MAX is used as parameter, which stays negative. So
651 
           we have an overflow from a positive value to a negative.
652 
           Using CCAP mode the resulting cc can be used for comparisons.  */
653 
        if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
654 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
655 
          return CCAPmode;
656 
 
657 
        /* If constants are involved in an add instruction it is possible to use
658 
           the resulting cc for comparisons with zero. Knowing the sign of the
659 
           constant the overflow behavior gets predictable. e.g.:
660 
             int a, b; if ((b = a + c) > 0)
661 
           with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP  */
662 
        if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
663 
            && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
664 
          {
665 
            if (INTVAL (XEXP((op0), 1)) < 0)
666 
              return CCANmode;
667 
            else
668 
              return CCAPmode;
669 
          }
670 
        /* Fall through.  */
671 
      case UNORDERED:
672 
      case ORDERED:
673 
      case UNEQ:
674 
      case UNLE:
675 
      case UNLT:
676 
      case UNGE:
677 
      case UNGT:
678 
      case LTGT:
679 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
680 
            && GET_CODE (op1) != CONST_INT)
681 
          return CCSRmode;
682 
        return CCSmode;
683 
 
684 
      case LTU:
685 
      case GEU:
686 
        if (GET_CODE (op0) == PLUS
687 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
688 
          return CCL1mode;
689 
 
690 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
691 
            && GET_CODE (op1) != CONST_INT)
692 
          return CCURmode;
693 
        return CCUmode;
694 
 
695 
      case LEU:
696 
      case GTU:
697 
        if (GET_CODE (op0) == MINUS
698 
            && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
699 
          return CCL2mode;
700 
 
701 
        if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
702 
            && GET_CODE (op1) != CONST_INT)
703 
          return CCURmode;
704 
        return CCUmode;
705 
 
706 
      default:
707 
        gcc_unreachable ();
708 
    }
709 
}
710 
 
711 
/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
712 
   that we can implement more efficiently.  */
713 
 
714 
void
715 
s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
716 
{
717 
  /* Convert ZERO_EXTRACT back to AND to enable TM patterns.  */
718 
  if ((*code == EQ || *code == NE)
719 
      && *op1 == const0_rtx
720 
      && GET_CODE (*op0) == ZERO_EXTRACT
721 
      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
722 
      && GET_CODE (XEXP (*op0, 2)) == CONST_INT
723 
      && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
724 
    {
725 
      rtx inner = XEXP (*op0, 0);
726 
      HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
727 
      HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
728 
      HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
729 
 
730 
      if (len > 0 && len < modesize
731 
          && pos >= 0 && pos + len <= modesize
732 
          && modesize <= HOST_BITS_PER_WIDE_INT)
733 
        {
734 
          unsigned HOST_WIDE_INT block;
735 
          block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
736 
          block <<= modesize - pos - len;
737 
 
738 
          *op0 = gen_rtx_AND (GET_MODE (inner), inner,
739 
                              gen_int_mode (block, GET_MODE (inner)));
740 
        }
741 
    }
742 
 
743 
  /* Narrow AND of memory against immediate to enable TM.  */
744 
  if ((*code == EQ || *code == NE)
745 
      && *op1 == const0_rtx
746 
      && GET_CODE (*op0) == AND
747 
      && GET_CODE (XEXP (*op0, 1)) == CONST_INT
748 
      && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
749 
    {
750 
      rtx inner = XEXP (*op0, 0);
751 
      rtx mask = XEXP (*op0, 1);
752 
 
753 
      /* Ignore paradoxical SUBREGs if all extra bits are masked out.  */
754 
      if (GET_CODE (inner) == SUBREG
755 
          && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
756 
          && (GET_MODE_SIZE (GET_MODE (inner))
757 
              >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
758 
          && ((INTVAL (mask)
759 
               & GET_MODE_MASK (GET_MODE (inner))
760 
               & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
761 
              == 0))
762 
        inner = SUBREG_REG (inner);
763 
 
764 
      /* Do not change volatile MEMs.  */
765 
      if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
766 
        {
767 
          int part = s390_single_part (XEXP (*op0, 1),
768 
                                       GET_MODE (inner), QImode, 0);
769 
          if (part >= 0)
770 
            {
771 
              mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
772 
              inner = adjust_address_nv (inner, QImode, part);
773 
              *op0 = gen_rtx_AND (QImode, inner, mask);
774 
            }
775 
        }
776 
    }
777 
 
778 
  /* Narrow comparisons against 0xffff to HImode if possible.  */
779 
  if ((*code == EQ || *code == NE)
780 
      && GET_CODE (*op1) == CONST_INT
781 
      && INTVAL (*op1) == 0xffff
782 
      && SCALAR_INT_MODE_P (GET_MODE (*op0))
783 
      && (nonzero_bits (*op0, GET_MODE (*op0))
784 
          & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
785 
    {
786 
      *op0 = gen_lowpart (HImode, *op0);
787 
      *op1 = constm1_rtx;
788 
    }
789 
 
790 
  /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible.  */
791 
  if (GET_CODE (*op0) == UNSPEC
792 
      && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
793 
      && XVECLEN (*op0, 0) == 1
794 
      && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
795 
      && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
796 
      && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
797 
      && *op1 == const0_rtx)
798 
    {
799 
      enum rtx_code new_code = UNKNOWN;
800 
      switch (*code)
801 
        {
802 
          case EQ: new_code = EQ;  break;
803 
          case NE: new_code = NE;  break;
804 
          case LT: new_code = GTU; break;
805 
          case GT: new_code = LTU; break;
806 
          case LE: new_code = GEU; break;
807 
          case GE: new_code = LEU; break;
808 
          default: break;
809 
        }
810 
 
811 
      if (new_code != UNKNOWN)
812 
        {
813 
          *op0 = XVECEXP (*op0, 0, 0);
814 
          *code = new_code;
815 
        }
816 
    }
817 
 
818 
  /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible.  */
819 
  if (GET_CODE (*op0) == UNSPEC
820 
      && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
821 
      && XVECLEN (*op0, 0) == 1
822 
      && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
823 
      && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
824 
      && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
825 
      && *op1 == const0_rtx)
826 
    {
827 
      enum rtx_code new_code = UNKNOWN;
828 
      switch (*code)
829 
        {
830 
          case EQ: new_code = EQ;  break;
831 
          case NE: new_code = NE;  break;
832 
          default: break;
833 
        }
834 
 
835 
      if (new_code != UNKNOWN)
836 
        {
837 
          *op0 = XVECEXP (*op0, 0, 0);
838 
          *code = new_code;
839 
        }
840 
    }
841 
 
842 
  /* Simplify cascaded EQ, NE with const0_rtx.  */
843 
  if ((*code == NE || *code == EQ)
844 
      && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
845 
      && GET_MODE (*op0) == SImode
846 
      && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
847 
      && REG_P (XEXP (*op0, 0))
848 
      && XEXP (*op0, 1) == const0_rtx
849 
      && *op1 == const0_rtx)
850 
    {
851 
      if ((*code == EQ && GET_CODE (*op0) == NE)
852 
          || (*code == NE && GET_CODE (*op0) == EQ))
853 
        *code = EQ;
854 
      else
855 
        *code = NE;
856 
      *op0 = XEXP (*op0, 0);
857 
    }
858 
 
859 
  /* Prefer register over memory as first operand.  */
860 
  if (MEM_P (*op0) && REG_P (*op1))
861 
    {
862 
      rtx tem = *op0; *op0 = *op1; *op1 = tem;
863 
      *code = swap_condition (*code);
864 
    }
865 
}
866 
 
867 
/* Emit a compare instruction suitable to implement the comparison
868 
   OP0 CODE OP1.  Return the correct condition RTL to be placed in
869 
   the IF_THEN_ELSE of the conditional branch testing the result.  */
870 
 
871 
rtx
872 
s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
873 
{
874 
  enum machine_mode mode = s390_select_ccmode (code, op0, op1);
875 
  rtx cc;
876 
 
877 
  /* Do not output a redundant compare instruction if a compare_and_swap
878 
     pattern already computed the result and the machine modes are compatible.  */
879 
  if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
880 
    {
881 
      gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
882 
                  == GET_MODE (op0));
883 
      cc = op0;
884 
    }
885 
  else
886 
    {
887 
      cc = gen_rtx_REG (mode, CC_REGNUM);
888 
      emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
889 
    }
890 
 
891 
  return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
892 
}
893 
 
894 
/* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
895 
   matches CMP.
896 
   Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
897 
   conditional branch testing the result.  */
898 
 
899 
static rtx
900 
s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
901 
{
902 
  emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
903 
  return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
904 
}
905 
 
906 
/* Emit a jump instruction to TARGET.  If COND is NULL_RTX, emit an
907 
   unconditional jump, else a conditional jump under condition COND.  */
908 
 
909 
void
910 
s390_emit_jump (rtx target, rtx cond)
911 
{
912 
  rtx insn;
913 
 
914 
  target = gen_rtx_LABEL_REF (VOIDmode, target);
915 
  if (cond)
916 
    target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
917 
 
918 
  insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
919 
  emit_jump_insn (insn);
920 
}
921 
 
922 
/* Return branch condition mask to implement a branch
923 
   specified by CODE.  Return -1 for invalid comparisons.  */
924 
 
925 
int
926 
s390_branch_condition_mask (rtx code)
927 
{
928 
  const int CC0 = 1 << 3;
929 
  const int CC1 = 1 << 2;
930 
  const int CC2 = 1 << 1;
931 
  const int CC3 = 1 << 0;
932 
 
933 
  gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
934 
  gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
935 
  gcc_assert (XEXP (code, 1) == const0_rtx);
936 
 
937 
  switch (GET_MODE (XEXP (code, 0)))
938 
    {
939 
    case CCZmode:
940 
    case CCZ1mode:
941 
      switch (GET_CODE (code))
942 
        {
943 
        case EQ:        return CC0;
944 
        case NE:        return CC1 | CC2 | CC3;
945 
        default:        return -1;
946 
        }
947 
      break;
948 
 
949 
    case CCT1mode:
950 
      switch (GET_CODE (code))
951 
        {
952 
        case EQ:        return CC1;
953 
        case NE:        return CC0 | CC2 | CC3;
954 
        default:        return -1;
955 
        }
956 
      break;
957 
 
958 
    case CCT2mode:
959 
      switch (GET_CODE (code))
960 
        {
961 
        case EQ:        return CC2;
962 
        case NE:        return CC0 | CC1 | CC3;
963 
        default:        return -1;
964 
        }
965 
      break;
966 
 
967 
    case CCT3mode:
968 
      switch (GET_CODE (code))
969 
        {
970 
        case EQ:        return CC3;
971 
        case NE:        return CC0 | CC1 | CC2;
972 
        default:        return -1;
973 
        }
974 
      break;
975 
 
976 
    case CCLmode:
977 
      switch (GET_CODE (code))
978 
        {
979 
        case EQ:        return CC0 | CC2;
980 
        case NE:        return CC1 | CC3;
981 
        default:        return -1;
982 
        }
983 
      break;
984 
 
985 
    case CCL1mode:
986 
      switch (GET_CODE (code))
987 
        {
988 
        case LTU:       return CC2 | CC3;  /* carry */
989 
        case GEU:       return CC0 | CC1;  /* no carry */
990 
        default:        return -1;
991 
        }
992 
      break;
993 
 
994 
    case CCL2mode:
995 
      switch (GET_CODE (code))
996 
        {
997 
        case GTU:       return CC0 | CC1;  /* borrow */
998 
        case LEU:       return CC2 | CC3;  /* no borrow */
999 
        default:        return -1;
1000 
        }
1001 
      break;
1002 
 
1003 
    case CCL3mode:
1004 
      switch (GET_CODE (code))
1005 
        {
1006 
        case EQ:        return CC0 | CC2;
1007 
        case NE:        return CC1 | CC3;
1008 
        case LTU:       return CC1;
1009 
        case GTU:       return CC3;
1010 
        case LEU:       return CC1 | CC2;
1011 
        case GEU:       return CC2 | CC3;
1012 
        default:        return -1;
1013 
        }
1014 
 
1015 
    case CCUmode:
1016 
      switch (GET_CODE (code))
1017 
        {
1018 
        case EQ:        return CC0;
1019 
        case NE:        return CC1 | CC2 | CC3;
1020 
        case LTU:       return CC1;
1021 
        case GTU:       return CC2;
1022 
        case LEU:       return CC0 | CC1;
1023 
        case GEU:       return CC0 | CC2;
1024 
        default:        return -1;
1025 
        }
1026 
      break;
1027 
 
1028 
    case CCURmode:
1029 
      switch (GET_CODE (code))
1030 
        {
1031 
        case EQ:        return CC0;
1032 
        case NE:        return CC2 | CC1 | CC3;
1033 
        case LTU:       return CC2;
1034 
        case GTU:       return CC1;
1035 
        case LEU:       return CC0 | CC2;
1036 
        case GEU:       return CC0 | CC1;
1037 
        default:        return -1;
1038 
        }
1039 
      break;
1040 
 
1041 
    case CCAPmode:
1042 
      switch (GET_CODE (code))
1043 
        {
1044 
        case EQ:        return CC0;
1045 
        case NE:        return CC1 | CC2 | CC3;
1046 
        case LT:        return CC1 | CC3;
1047 
        case GT:        return CC2;
1048 
        case LE:        return CC0 | CC1 | CC3;
1049 
        case GE:        return CC0 | CC2;
1050 
        default:        return -1;
1051 
        }
1052 
      break;
1053 
 
1054 
    case CCANmode:
1055 
      switch (GET_CODE (code))
1056 
        {
1057 
        case EQ:        return CC0;
1058 
        case NE:        return CC1 | CC2 | CC3;
1059 
        case LT:        return CC1;
1060 
        case GT:        return CC2 | CC3;
1061 
        case LE:        return CC0 | CC1;
1062 
        case GE:        return CC0 | CC2 | CC3;
1063 
        default:        return -1;
1064 
        }
1065 
      break;
1066 
 
1067 
    case CCSmode:
1068 
      switch (GET_CODE (code))
1069 
        {
1070 
        case EQ:        return CC0;
1071 
        case NE:        return CC1 | CC2 | CC3;
1072 
        case LT:        return CC1;
1073 
        case GT:        return CC2;
1074 
        case LE:        return CC0 | CC1;
1075 
        case GE:        return CC0 | CC2;
1076 
        case UNORDERED: return CC3;
1077 
        case ORDERED:   return CC0 | CC1 | CC2;
1078 
        case UNEQ:      return CC0 | CC3;
1079 
        case UNLT:      return CC1 | CC3;
1080 
        case UNGT:      return CC2 | CC3;
1081 
        case UNLE:      return CC0 | CC1 | CC3;
1082 
        case UNGE:      return CC0 | CC2 | CC3;
1083 
        case LTGT:      return CC1 | CC2;
1084 
        default:        return -1;
1085 
        }
1086 
      break;
1087 
 
1088 
    case CCSRmode:
1089 
      switch (GET_CODE (code))
1090 
        {
1091 
        case EQ:        return CC0;
1092 
        case NE:        return CC2 | CC1 | CC3;
1093 
        case LT:        return CC2;
1094 
        case GT:        return CC1;
1095 
        case LE:        return CC0 | CC2;
1096 
        case GE:        return CC0 | CC1;
1097 
        case UNORDERED: return CC3;
1098 
        case ORDERED:   return CC0 | CC2 | CC1;
1099 
        case UNEQ:      return CC0 | CC3;
1100 
        case UNLT:      return CC2 | CC3;
1101 
        case UNGT:      return CC1 | CC3;
1102 
        case UNLE:      return CC0 | CC2 | CC3;
1103 
        case UNGE:      return CC0 | CC1 | CC3;
1104 
        case LTGT:      return CC2 | CC1;
1105 
        default:        return -1;
1106 
        }
1107 
      break;
1108 
 
1109 
    default:
1110 
      return -1;
1111 
    }
1112 
}
1113 
 
1114 
 
1115 
/* Return branch condition mask to implement a compare and branch
1116 
   specified by CODE.  Return -1 for invalid comparisons.  */
1117 
 
1118 
int
1119 
s390_compare_and_branch_condition_mask (rtx code)
1120 
{
1121 
  const int CC0 = 1 << 3;
1122 
  const int CC1 = 1 << 2;
1123 
  const int CC2 = 1 << 1;
1124 
 
1125 
  switch (GET_CODE (code))
1126 
    {
1127 
    case EQ:
1128 
      return CC0;
1129 
    case NE:
1130 
      return CC1 | CC2;
1131 
    case LT:
1132 
    case LTU:
1133 
      return CC1;
1134 
    case GT:
1135 
    case GTU:
1136 
      return CC2;
1137 
    case LE:
1138 
    case LEU:
1139 
      return CC0 | CC1;
1140 
    case GE:
1141 
    case GEU:
1142 
      return CC0 | CC2;
1143 
    default:
1144 
      gcc_unreachable ();
1145 
    }
1146 
  return -1;
1147 
}
1148 
 
1149 
/* If INV is false, return assembler mnemonic string to implement
1150 
   a branch specified by CODE.  If INV is true, return mnemonic
1151 
   for the corresponding inverted branch.  */
1152 
 
1153 
static const char *
1154 
s390_branch_condition_mnemonic (rtx code, int inv)
1155 
{
1156 
  int mask;
1157 
 
1158 
  static const char *const mnemonic[16] =
1159 
    {
1160 
      NULL, "o", "h", "nle",
1161 
      "l", "nhe", "lh", "ne",
1162 
      "e", "nlh", "he", "nl",
1163 
      "le", "nh", "no", NULL
1164 
    };
1165 
 
1166 
  if (GET_CODE (XEXP (code, 0)) == REG
1167 
      && REGNO (XEXP (code, 0)) == CC_REGNUM
1168 
      && XEXP (code, 1) == const0_rtx)
1169 
    mask = s390_branch_condition_mask (code);
1170 
  else
1171 
    mask = s390_compare_and_branch_condition_mask (code);
1172 
 
1173 
  gcc_assert (mask >= 0);
1174 
 
1175 
  if (inv)
1176 
    mask ^= 15;
1177 
 
1178 
  gcc_assert (mask >= 1 && mask <= 14);
1179 
 
1180 
  return mnemonic[mask];
1181 
}
1182 
 
1183 
/* Return the part of op which has a value different from def.
1184 
   The size of the part is determined by mode.
1185 
   Use this function only if you already know that op really
1186 
   contains such a part.  */
1187 
 
1188 
unsigned HOST_WIDE_INT
1189 
s390_extract_part (rtx op, enum machine_mode mode, int def)
1190 
{
1191 
  unsigned HOST_WIDE_INT value = 0;
1192 
  int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1193 
  int part_bits = GET_MODE_BITSIZE (mode);
1194 
  unsigned HOST_WIDE_INT part_mask
1195 
    = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1196 
  int i;
1197 
 
1198 
  for (i = 0; i < max_parts; i++)
1199 
    {
1200 
      if (i == 0)
1201 
        value = (unsigned HOST_WIDE_INT) INTVAL (op);
1202 
      else
1203 
        value >>= part_bits;
1204 
 
1205 
      if ((value & part_mask) != (def & part_mask))
1206 
        return value & part_mask;
1207 
    }
1208 
 
1209 
  gcc_unreachable ();
1210 
}
1211 
 
1212 
/* If OP is an integer constant of mode MODE with exactly one
1213 
   part of mode PART_MODE unequal to DEF, return the number of that
1214 
   part. Otherwise, return -1.  */
1215 
 
1216 
int
1217 
s390_single_part (rtx op,
1218 
                  enum machine_mode mode,
1219 
                  enum machine_mode part_mode,
1220 
                  int def)
1221 
{
1222 
  unsigned HOST_WIDE_INT value = 0;
1223 
  int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1224 
  unsigned HOST_WIDE_INT part_mask
1225 
    = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1226 
  int i, part = -1;
1227 
 
1228 
  if (GET_CODE (op) != CONST_INT)
1229 
    return -1;
1230 
 
1231 
  for (i = 0; i < n_parts; i++)
1232 
    {
1233 
      if (i == 0)
1234 
        value = (unsigned HOST_WIDE_INT) INTVAL (op);
1235 
      else
1236 
        value >>= GET_MODE_BITSIZE (part_mode);
1237 
 
1238 
      if ((value & part_mask) != (def & part_mask))
1239 
        {
1240 
          if (part != -1)
1241 
            return -1;
1242 
          else
1243 
            part = i;
1244 
        }
1245 
    }
1246 
  return part == -1 ? -1 : n_parts - 1 - part;
1247 
}
1248 
 
1249 
/* Return true if IN contains a contiguous bitfield in the lower SIZE
1250 
   bits and no other bits are set in IN.  POS and LENGTH can be used
1251 
   to obtain the start position and the length of the bitfield.
1252 
 
1253 
   POS gives the position of the first bit of the bitfield counting
1254 
   from the lowest order bit starting with zero.  In order to use this
1255 
   value for S/390 instructions this has to be converted to "bits big
1256 
   endian" style.  */
1257 
 
1258 
bool
1259 
s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1260 
                           int *pos, int *length)
1261 
{
1262 
  int tmp_pos = 0;
1263 
  int tmp_length = 0;
1264 
  int i;
1265 
  unsigned HOST_WIDE_INT mask = 1ULL;
1266 
  bool contiguous = false;
1267 
 
1268 
  for (i = 0; i < size; mask <<= 1, i++)
1269 
    {
1270 
      if (contiguous)
1271 
        {
1272 
          if (mask & in)
1273 
            tmp_length++;
1274 
          else
1275 
            break;
1276 
        }
1277 
      else
1278 
        {
1279 
          if (mask & in)
1280 
            {
1281 
              contiguous = true;
1282 
              tmp_length++;
1283 
            }
1284 
          else
1285 
            tmp_pos++;
1286 
        }
1287 
    }
1288 
 
1289 
  if (!tmp_length)
1290 
    return false;
1291 
 
1292 
  /* Calculate a mask for all bits beyond the contiguous bits.  */
1293 
  mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1294 
 
1295 
  if (mask & in)
1296 
    return false;
1297 
 
1298 
  if (tmp_length + tmp_pos - 1 > size)
1299 
    return false;
1300 
 
1301 
  if (length)
1302 
    *length = tmp_length;
1303 
 
1304 
  if (pos)
1305 
    *pos = tmp_pos;
1306 
 
1307 
  return true;
1308 
}
1309 
 
1310 
/* Check whether we can (and want to) split a double-word
1311 
   move in mode MODE from SRC to DST into two single-word
1312 
   moves, moving the subword FIRST_SUBWORD first.  */
1313 
 
1314 
bool
1315 
s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1316 
{
1317 
  /* Floating point registers cannot be split.  */
1318 
  if (FP_REG_P (src) || FP_REG_P (dst))
1319 
    return false;
1320 
 
1321 
  /* We don't need to split if operands are directly accessible.  */
1322 
  if (s_operand (src, mode) || s_operand (dst, mode))
1323 
    return false;
1324 
 
1325 
  /* Non-offsettable memory references cannot be split.  */
1326 
  if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1327 
      || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1328 
    return false;
1329 
 
1330 
  /* Moving the first subword must not clobber a register
1331 
     needed to move the second subword.  */
1332 
  if (register_operand (dst, mode))
1333 
    {
1334 
      rtx subreg = operand_subword (dst, first_subword, 0, mode);
1335 
      if (reg_overlap_mentioned_p (subreg, src))
1336 
        return false;
1337 
    }
1338 
 
1339 
  return true;
1340 
}
1341 
 
1342 
/* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1343 
   and [MEM2, MEM2 + SIZE] do overlap and false
1344 
   otherwise.  */
1345 
 
1346 
bool
1347 
s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1348 
{
1349 
  rtx addr1, addr2, addr_delta;
1350 
  HOST_WIDE_INT delta;
1351 
 
1352 
  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1353 
    return true;
1354 
 
1355 
  if (size == 0)
1356 
    return false;
1357 
 
1358 
  addr1 = XEXP (mem1, 0);
1359 
  addr2 = XEXP (mem2, 0);
1360 
 
1361 
  addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1362 
 
1363 
  /* This overlapping check is used by peepholes merging memory block operations.
1364 
     Overlapping operations would otherwise be recognized by the S/390 hardware
1365 
     and would fall back to a slower implementation. Allowing overlapping
1366 
     operations would lead to slow code but not to wrong code. Therefore we are
1367 
     somewhat optimistic if we cannot prove that the memory blocks are
1368 
     overlapping.
1369 
     That's why we return false here although this may accept operations on
1370 
     overlapping memory areas.  */
1371 
  if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1372 
    return false;
1373 
 
1374 
  delta = INTVAL (addr_delta);
1375 
 
1376 
  if (delta == 0
1377 
      || (delta > 0 && delta < size)
1378 
      || (delta < 0 && -delta < size))
1379 
    return true;
1380 
 
1381 
  return false;
1382 
}
1383 
 
1384 
/* Check whether the address of memory reference MEM2 equals exactly
1385 
   the address of memory reference MEM1 plus DELTA.  Return true if
1386 
   we can prove this to be the case, false otherwise.  */
1387 
 
1388 
bool
1389 
s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1390 
{
1391 
  rtx addr1, addr2, addr_delta;
1392 
 
1393 
  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1394 
    return false;
1395 
 
1396 
  addr1 = XEXP (mem1, 0);
1397 
  addr2 = XEXP (mem2, 0);
1398 
 
1399 
  addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1400 
  if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1401 
    return false;
1402 
 
1403 
  return true;
1404 
}
1405 
 
1406 
/* Expand logical operator CODE in mode MODE with operands OPERANDS.  */
1407 
 
1408 
void
1409 
s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1410 
                              rtx *operands)
1411 
{
1412 
  enum machine_mode wmode = mode;
1413 
  rtx dst = operands[0];
1414 
  rtx src1 = operands[1];
1415 
  rtx src2 = operands[2];
1416 
  rtx op, clob, tem;
1417 
 
1418 
  /* If we cannot handle the operation directly, use a temp register.  */
1419 
  if (!s390_logical_operator_ok_p (operands))
1420 
    dst = gen_reg_rtx (mode);
1421 
 
1422 
  /* QImode and HImode patterns make sense only if we have a destination
1423 
     in memory.  Otherwise perform the operation in SImode.  */
1424 
  if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1425 
    wmode = SImode;
1426 
 
1427 
  /* Widen operands if required.  */
1428 
  if (mode != wmode)
1429 
    {
1430 
      if (GET_CODE (dst) == SUBREG
1431 
          && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1432 
        dst = tem;
1433 
      else if (REG_P (dst))
1434 
        dst = gen_rtx_SUBREG (wmode, dst, 0);
1435 
      else
1436 
        dst = gen_reg_rtx (wmode);
1437 
 
1438 
      if (GET_CODE (src1) == SUBREG
1439 
          && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1440 
        src1 = tem;
1441 
      else if (GET_MODE (src1) != VOIDmode)
1442 
        src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1443 
 
1444 
      if (GET_CODE (src2) == SUBREG
1445 
          && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1446 
        src2 = tem;
1447 
      else if (GET_MODE (src2) != VOIDmode)
1448 
        src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1449 
    }
1450 
 
1451 
  /* Emit the instruction.  */
1452 
  op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1453 
  clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1454 
  emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1455 
 
1456 
  /* Fix up the destination if needed.  */
1457 
  if (dst != operands[0])
1458 
    emit_move_insn (operands[0], gen_lowpart (mode, dst));
1459 
}
1460 
 
1461 
/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR).  */
1462 
 
1463 
bool
1464 
s390_logical_operator_ok_p (rtx *operands)
1465 
{
1466 
  /* If the destination operand is in memory, it needs to coincide
1467 
     with one of the source operands.  After reload, it has to be
1468 
     the first source operand.  */
1469 
  if (GET_CODE (operands[0]) == MEM)
1470 
    return rtx_equal_p (operands[0], operands[1])
1471 
           || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1472 
 
1473 
  return true;
1474 
}
1475 
 
1476 
/* Narrow logical operation CODE of memory operand MEMOP with immediate
1477 
   operand IMMOP to switch from SS to SI type instructions.  */
1478 
 
1479 
void
1480 
s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1481 
{
1482 
  int def = code == AND ? -1 : 0;
1483 
  HOST_WIDE_INT mask;
1484 
  int part;
1485 
 
1486 
  gcc_assert (GET_CODE (*memop) == MEM);
1487 
  gcc_assert (!MEM_VOLATILE_P (*memop));
1488 
 
1489 
  mask = s390_extract_part (*immop, QImode, def);
1490 
  part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1491 
  gcc_assert (part >= 0);
1492 
 
1493 
  *memop = adjust_address (*memop, QImode, part);
1494 
  *immop = gen_int_mode (mask, QImode);
1495 
}
1496 
 
1497 
 
1498 
/* How to allocate a 'struct machine_function'.  */
1499 
 
1500 
static struct machine_function *
1501 
s390_init_machine_status (void)
1502 
{
1503 
  return ggc_alloc_cleared_machine_function ();
1504 
}
1505 
 
1506 
static void
1507 
s390_option_override (void)
1508 
{
1509 
  /* Set up function hooks.  */
1510 
  init_machine_status = s390_init_machine_status;
1511 
 
1512 
  /* Architecture mode defaults according to ABI.  */
1513 
  if (!(target_flags_explicit & MASK_ZARCH))
1514 
    {
1515 
      if (TARGET_64BIT)
1516 
        target_flags |= MASK_ZARCH;
1517 
      else
1518 
        target_flags &= ~MASK_ZARCH;
1519 
    }
1520 
 
1521 
  /* Set the march default in case it hasn't been specified on
1522 
     cmdline.  */
1523 
  if (s390_arch == PROCESSOR_max)
1524 
    {
1525 
      s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1526 
      s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1527 
      s390_arch_flags = processor_flags_table[(int)s390_arch];
1528 
    }
1529 
 
1530 
  /* Determine processor to tune for.  */
1531 
  if (s390_tune == PROCESSOR_max)
1532 
    {
1533 
      s390_tune = s390_arch;
1534 
      s390_tune_flags = s390_arch_flags;
1535 
    }
1536 
 
1537 
  /* Sanity checks.  */
1538 
  if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1539 
    error ("z/Architecture mode not supported on %s", s390_arch_string);
1540 
  if (TARGET_64BIT && !TARGET_ZARCH)
1541 
    error ("64-bit ABI not supported in ESA/390 mode");
1542 
 
1543 
  /* Use hardware DFP if available and not explicitly disabled by
1544 
     user. E.g. with -m31 -march=z10 -mzarch   */
1545 
  if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1546 
    target_flags |= MASK_HARD_DFP;
1547 
 
1548 
  if (TARGET_HARD_DFP && !TARGET_DFP)
1549 
    {
1550 
      if (target_flags_explicit & MASK_HARD_DFP)
1551 
        {
1552 
          if (!TARGET_CPU_DFP)
1553 
            error ("hardware decimal floating point instructions"
1554 
                   " not available on %s", s390_arch_string);
1555 
          if (!TARGET_ZARCH)
1556 
            error ("hardware decimal floating point instructions"
1557 
                   " not available in ESA/390 mode");
1558 
        }
1559 
      else
1560 
        target_flags &= ~MASK_HARD_DFP;
1561 
    }
1562 
 
1563 
  if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1564 
    {
1565 
      if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1566 
        error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1567 
 
1568 
      target_flags &= ~MASK_HARD_DFP;
1569 
    }
1570 
 
1571 
  /* Set processor cost function.  */
1572 
  switch (s390_tune)
1573 
    {
1574 
    case PROCESSOR_2084_Z990:
1575 
      s390_cost = &z990_cost;
1576 
      break;
1577 
    case PROCESSOR_2094_Z9_109:
1578 
      s390_cost = &z9_109_cost;
1579 
      break;
1580 
    case PROCESSOR_2097_Z10:
1581 
      s390_cost = &z10_cost;
1582 
    case PROCESSOR_2817_Z196:
1583 
      s390_cost = &z196_cost;
1584 
      break;
1585 
    default:
1586 
      s390_cost = &z900_cost;
1587 
    }
1588 
 
1589 
  if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1590 
    error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1591 
           "in combination");
1592 
 
1593 
  if (s390_stack_size)
1594 
    {
1595 
      if (s390_stack_guard >= s390_stack_size)
1596 
        error ("stack size must be greater than the stack guard value");
1597 
      else if (s390_stack_size > 1 << 16)
1598 
        error ("stack size must not be greater than 64k");
1599 
    }
1600 
  else if (s390_stack_guard)
1601 
    error ("-mstack-guard implies use of -mstack-size");
1602 
 
1603 
#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1604 
  if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1605 
    target_flags |= MASK_LONG_DOUBLE_128;
1606 
#endif
1607 
 
1608 
  if (s390_tune == PROCESSOR_2097_Z10
1609 
      || s390_tune == PROCESSOR_2817_Z196)
1610 
    {
1611 
      maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1612 
                             global_options.x_param_values,
1613 
                             global_options_set.x_param_values);
1614 
      maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1615 
                             global_options.x_param_values,
1616 
                             global_options_set.x_param_values);
1617 
      maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1618 
                             global_options.x_param_values,
1619 
                             global_options_set.x_param_values);
1620 
      maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1621 
                             global_options.x_param_values,
1622 
                             global_options_set.x_param_values);
1623 
    }
1624 
 
1625 
  maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1626 
                         global_options.x_param_values,
1627 
                         global_options_set.x_param_values);
1628 
  /* values for loop prefetching */
1629 
  maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1630 
                         global_options.x_param_values,
1631 
                         global_options_set.x_param_values);
1632 
  maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1633 
                         global_options.x_param_values,
1634 
                         global_options_set.x_param_values);
1635 
  /* s390 has more than 2 levels and the size is much larger.  Since
1636 
     we are always running virtualized assume that we only get a small
1637 
     part of the caches above l1.  */
1638 
  maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1639 
                         global_options.x_param_values,
1640 
                         global_options_set.x_param_values);
1641 
  maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1642 
                         global_options.x_param_values,
1643 
                         global_options_set.x_param_values);
1644 
  maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1645 
                         global_options.x_param_values,
1646 
                         global_options_set.x_param_values);
1647 
 
1648 
  /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1649 
     requires the arch flags to be evaluated already.  Since prefetching
1650 
     is beneficial on s390, we enable it if available.  */
1651 
  if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
1652 
    flag_prefetch_loop_arrays = 1;
1653 
}
1654 
 
1655 
/* Map for smallest class containing reg regno.  */
1656 
 
1657 
const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1658 
{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1659 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1660 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1661 
  ADDR_REGS,    ADDR_REGS, ADDR_REGS, ADDR_REGS,
1662 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1663 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1664 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1665 
  FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
1666 
  ADDR_REGS,    CC_REGS,   ADDR_REGS, ADDR_REGS,
1667 
  ACCESS_REGS,  ACCESS_REGS
1668 
};
1669 
 
1670 
/* Return attribute type of insn.  */
1671 
 
1672 
static enum attr_type
1673 
s390_safe_attr_type (rtx insn)
1674 
{
1675 
  if (recog_memoized (insn) >= 0)
1676 
    return get_attr_type (insn);
1677 
  else
1678 
    return TYPE_NONE;
1679 
}
1680 
 
1681 
/* Return true if DISP is a valid short displacement.  */
1682 
 
1683 
static bool
1684 
s390_short_displacement (rtx disp)
1685 
{
1686 
  /* No displacement is OK.  */
1687 
  if (!disp)
1688 
    return true;
1689 
 
1690 
  /* Without the long displacement facility we don't need to
1691 
     distingiush between long and short displacement.  */
1692 
  if (!TARGET_LONG_DISPLACEMENT)
1693 
    return true;
1694 
 
1695 
  /* Integer displacement in range.  */
1696 
  if (GET_CODE (disp) == CONST_INT)
1697 
    return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1698 
 
1699 
  /* GOT offset is not OK, the GOT can be large.  */
1700 
  if (GET_CODE (disp) == CONST
1701 
      && GET_CODE (XEXP (disp, 0)) == UNSPEC
1702 
      && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1703 
          || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1704 
    return false;
1705 
 
1706 
  /* All other symbolic constants are literal pool references,
1707 
     which are OK as the literal pool must be small.  */
1708 
  if (GET_CODE (disp) == CONST)
1709 
    return true;
1710 
 
1711 
  return false;
1712 
}
1713 
 
1714 
/* Decompose a RTL expression ADDR for a memory address into
1715 
   its components, returned in OUT.
1716 
 
1717 
   Returns false if ADDR is not a valid memory address, true
1718 
   otherwise.  If OUT is NULL, don't return the components,
1719 
   but check for validity only.
1720 
 
1721 
   Note: Only addresses in canonical form are recognized.
1722 
   LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1723 
   canonical form so that they will be recognized.  */
1724 
 
1725 
static int
1726 
s390_decompose_address (rtx addr, struct s390_address *out)
1727 
{
1728 
  HOST_WIDE_INT offset = 0;
1729 
  rtx base = NULL_RTX;
1730 
  rtx indx = NULL_RTX;
1731 
  rtx disp = NULL_RTX;
1732 
  rtx orig_disp;
1733 
  bool pointer = false;
1734 
  bool base_ptr = false;
1735 
  bool indx_ptr = false;
1736 
  bool literal_pool = false;
1737 
 
1738 
  /* We may need to substitute the literal pool base register into the address
1739 
     below.  However, at this point we do not know which register is going to
1740 
     be used as base, so we substitute the arg pointer register.  This is going
1741 
     to be treated as holding a pointer below -- it shouldn't be used for any
1742 
     other purpose.  */
1743 
  rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1744 
 
1745 
  /* Decompose address into base + index + displacement.  */
1746 
 
1747 
  if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1748 
    base = addr;
1749 
 
1750 
  else if (GET_CODE (addr) == PLUS)
1751 
    {
1752 
      rtx op0 = XEXP (addr, 0);
1753 
      rtx op1 = XEXP (addr, 1);
1754 
      enum rtx_code code0 = GET_CODE (op0);
1755 
      enum rtx_code code1 = GET_CODE (op1);
1756 
 
1757 
      if (code0 == REG || code0 == UNSPEC)
1758 
        {
1759 
          if (code1 == REG || code1 == UNSPEC)
1760 
            {
1761 
              indx = op0;       /* index + base */
1762 
              base = op1;
1763 
            }
1764 
 
1765 
          else
1766 
            {
1767 
              base = op0;       /* base + displacement */
1768 
              disp = op1;
1769 
            }
1770 
        }
1771 
 
1772 
      else if (code0 == PLUS)
1773 
        {
1774 
          indx = XEXP (op0, 0);  /* index + base + disp */
1775 
          base = XEXP (op0, 1);
1776 
          disp = op1;
1777 
        }
1778 
 
1779 
      else
1780 
        {
1781 
          return false;
1782 
        }
1783 
    }
1784 
 
1785 
  else
1786 
    disp = addr;                /* displacement */
1787 
 
1788 
  /* Extract integer part of displacement.  */
1789 
  orig_disp = disp;
1790 
  if (disp)
1791 
    {
1792 
      if (GET_CODE (disp) == CONST_INT)
1793 
        {
1794 
          offset = INTVAL (disp);
1795 
          disp = NULL_RTX;
1796 
        }
1797 
      else if (GET_CODE (disp) == CONST
1798 
               && GET_CODE (XEXP (disp, 0)) == PLUS
1799 
               && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1800 
        {
1801 
          offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1802 
          disp = XEXP (XEXP (disp, 0), 0);
1803 
        }
1804 
    }
1805 
 
1806 
  /* Strip off CONST here to avoid special case tests later.  */
1807 
  if (disp && GET_CODE (disp) == CONST)
1808 
    disp = XEXP (disp, 0);
1809 
 
1810 
  /* We can convert literal pool addresses to
1811 
     displacements by basing them off the base register.  */
1812 
  if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1813 
    {
1814 
      /* Either base or index must be free to hold the base register.  */
1815 
      if (!base)
1816 
        base = fake_pool_base, literal_pool = true;
1817 
      else if (!indx)
1818 
        indx = fake_pool_base, literal_pool = true;
1819 
      else
1820 
        return false;
1821 
 
1822 
      /* Mark up the displacement.  */
1823 
      disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1824 
                             UNSPEC_LTREL_OFFSET);
1825 
    }
1826 
 
1827 
  /* Validate base register.  */
1828 
  if (base)
1829 
    {
1830 
      if (GET_CODE (base) == UNSPEC)
1831 
        switch (XINT (base, 1))
1832 
          {
1833 
          case UNSPEC_LTREF:
1834 
            if (!disp)
1835 
              disp = gen_rtx_UNSPEC (Pmode,
1836 
                                     gen_rtvec (1, XVECEXP (base, 0, 0)),
1837 
                                     UNSPEC_LTREL_OFFSET);
1838 
            else
1839 
              return false;
1840 
 
1841 
            base = XVECEXP (base, 0, 1);
1842 
            break;
1843 
 
1844 
          case UNSPEC_LTREL_BASE:
1845 
            if (XVECLEN (base, 0) == 1)
1846 
              base = fake_pool_base, literal_pool = true;
1847 
            else
1848 
              base = XVECEXP (base, 0, 1);
1849 
            break;
1850 
 
1851 
          default:
1852 
            return false;
1853 
          }
1854 
 
1855 
      if (!REG_P (base)
1856 
          || (GET_MODE (base) != SImode
1857 
              && GET_MODE (base) != Pmode))
1858 
        return false;
1859 
 
1860 
      if (REGNO (base) == STACK_POINTER_REGNUM
1861 
          || REGNO (base) == FRAME_POINTER_REGNUM
1862 
          || ((reload_completed || reload_in_progress)
1863 
              && frame_pointer_needed
1864 
              && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1865 
          || REGNO (base) == ARG_POINTER_REGNUM
1866 
          || (flag_pic
1867 
              && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1868 
        pointer = base_ptr = true;
1869 
 
1870 
      if ((reload_completed || reload_in_progress)
1871 
          && base == cfun->machine->base_reg)
1872 
        pointer = base_ptr = literal_pool = true;
1873 
    }
1874 
 
1875 
  /* Validate index register.  */
1876 
  if (indx)
1877 
    {
1878 
      if (GET_CODE (indx) == UNSPEC)
1879 
        switch (XINT (indx, 1))
1880 
          {
1881 
          case UNSPEC_LTREF:
1882 
            if (!disp)
1883 
              disp = gen_rtx_UNSPEC (Pmode,
1884 
                                     gen_rtvec (1, XVECEXP (indx, 0, 0)),
1885 
                                     UNSPEC_LTREL_OFFSET);
1886 
            else
1887 
              return false;
1888 
 
1889 
            indx = XVECEXP (indx, 0, 1);
1890 
            break;
1891 
 
1892 
          case UNSPEC_LTREL_BASE:
1893 
            if (XVECLEN (indx, 0) == 1)
1894 
              indx = fake_pool_base, literal_pool = true;
1895 
            else
1896 
              indx = XVECEXP (indx, 0, 1);
1897 
            break;
1898 
 
1899 
          default:
1900 
            return false;
1901 
          }
1902 
 
1903 
      if (!REG_P (indx)
1904 
          || (GET_MODE (indx) != SImode
1905 
              && GET_MODE (indx) != Pmode))
1906 
        return false;
1907 
 
1908 
      if (REGNO (indx) == STACK_POINTER_REGNUM
1909 
          || REGNO (indx) == FRAME_POINTER_REGNUM
1910 
          || ((reload_completed || reload_in_progress)
1911 
              && frame_pointer_needed
1912 
              && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1913 
          || REGNO (indx) == ARG_POINTER_REGNUM
1914 
          || (flag_pic
1915 
              && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1916 
        pointer = indx_ptr = true;
1917 
 
1918 
      if ((reload_completed || reload_in_progress)
1919 
          && indx == cfun->machine->base_reg)
1920 
        pointer = indx_ptr = literal_pool = true;
1921 
    }
1922 
 
1923 
  /* Prefer to use pointer as base, not index.  */
1924 
  if (base && indx && !base_ptr
1925 
      && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1926 
    {
1927 
      rtx tmp = base;
1928 
      base = indx;
1929 
      indx = tmp;
1930 
    }
1931 
 
1932 
  /* Validate displacement.  */
1933 
  if (!disp)
1934 
    {
1935 
      /* If virtual registers are involved, the displacement will change later
1936 
         anyway as the virtual registers get eliminated.  This could make a
1937 
         valid displacement invalid, but it is more likely to make an invalid
1938 
         displacement valid, because we sometimes access the register save area
1939 
         via negative offsets to one of those registers.
1940 
         Thus we don't check the displacement for validity here.  If after
1941 
         elimination the displacement turns out to be invalid after all,
1942 
         this is fixed up by reload in any case.  */
1943 
      if (base != arg_pointer_rtx
1944 
          && indx != arg_pointer_rtx
1945 
          && base != return_address_pointer_rtx
1946 
          && indx != return_address_pointer_rtx
1947 
          && base != frame_pointer_rtx
1948 
          && indx != frame_pointer_rtx
1949 
          && base != virtual_stack_vars_rtx
1950 
          && indx != virtual_stack_vars_rtx)
1951 
        if (!DISP_IN_RANGE (offset))
1952 
          return false;
1953 
    }
1954 
  else
1955 
    {
1956 
      /* All the special cases are pointers.  */
1957 
      pointer = true;
1958 
 
1959 
      /* In the small-PIC case, the linker converts @GOT
1960 
         and @GOTNTPOFF offsets to possible displacements.  */
1961 
      if (GET_CODE (disp) == UNSPEC
1962 
          && (XINT (disp, 1) == UNSPEC_GOT
1963 
              || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1964 
          && flag_pic == 1)
1965 
        {
1966 
          ;
1967 
        }
1968 
 
1969 
      /* Accept pool label offsets.  */
1970 
      else if (GET_CODE (disp) == UNSPEC
1971 
               && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1972 
        ;
1973 
 
1974 
      /* Accept literal pool references.  */
1975 
      else if (GET_CODE (disp) == UNSPEC
1976 
               && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1977 
        {
1978 
          /* In case CSE pulled a non literal pool reference out of
1979 
             the pool we have to reject the address.  This is
1980 
             especially important when loading the GOT pointer on non
1981 
             zarch CPUs.  In this case the literal pool contains an lt
1982 
             relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1983 
             will most likely exceed the displacement.  */
1984 
          if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
1985 
              || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
1986 
            return false;
1987 
 
1988 
          orig_disp = gen_rtx_CONST (Pmode, disp);
1989 
          if (offset)
1990 
            {
1991 
              /* If we have an offset, make sure it does not
1992 
                 exceed the size of the constant pool entry.  */
1993 
              rtx sym = XVECEXP (disp, 0, 0);
1994 
              if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1995 
                return false;
1996 
 
1997 
              orig_disp = plus_constant (orig_disp, offset);
1998 
            }
1999 
        }
2000 
 
2001 
      else
2002 
        return false;
2003 
    }
2004 
 
2005 
  if (!base && !indx)
2006 
    pointer = true;
2007 
 
2008 
  if (out)
2009 
    {
2010 
      out->base = base;
2011 
      out->indx = indx;
2012 
      out->disp = orig_disp;
2013 
      out->pointer = pointer;
2014 
      out->literal_pool = literal_pool;
2015 
    }
2016 
 
2017 
  return true;
2018 
}
2019 
 
2020 
/* Decompose a RTL expression OP for a shift count into its components,
2021 
   and return the base register in BASE and the offset in OFFSET.
2022 
 
2023 
   Return true if OP is a valid shift count, false if not.  */
2024 
 
2025 
bool
2026 
s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2027 
{
2028 
  HOST_WIDE_INT off = 0;
2029 
 
2030 
  /* We can have an integer constant, an address register,
2031 
     or a sum of the two.  */
2032 
  if (GET_CODE (op) == CONST_INT)
2033 
    {
2034 
      off = INTVAL (op);
2035 
      op = NULL_RTX;
2036 
    }
2037 
  if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2038 
    {
2039 
      off = INTVAL (XEXP (op, 1));
2040 
      op = XEXP (op, 0);
2041 
    }
2042 
  while (op && GET_CODE (op) == SUBREG)
2043 
    op = SUBREG_REG (op);
2044 
 
2045 
  if (op && GET_CODE (op) != REG)
2046 
    return false;
2047 
 
2048 
  if (offset)
2049 
    *offset = off;
2050 
  if (base)
2051 
    *base = op;
2052 
 
2053 
   return true;
2054 
}
2055 
 
2056 
 
2057 
/* Return true if CODE is a valid address without index.  */
2058 
 
2059 
bool
2060 
s390_legitimate_address_without_index_p (rtx op)
2061 
{
2062 
  struct s390_address addr;
2063 
 
2064 
  if (!s390_decompose_address (XEXP (op, 0), &addr))
2065 
    return false;
2066 
  if (addr.indx)
2067 
    return false;
2068 
 
2069 
  return true;
2070 
}
2071 
 
2072 
 
2073 
/* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2074 
   and return these parts in SYMREF and ADDEND.  You can pass NULL in
2075 
   SYMREF and/or ADDEND if you are not interested in these values.
2076 
   Literal pool references are *not* considered symbol references.  */
2077 
 
2078 
static bool
2079 
s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2080 
{
2081 
  HOST_WIDE_INT tmpaddend = 0;
2082 
 
2083 
  if (GET_CODE (addr) == CONST)
2084 
    addr = XEXP (addr, 0);
2085 
 
2086 
  if (GET_CODE (addr) == PLUS)
2087 
    {
2088 
      if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2089 
          && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0))
2090 
          && CONST_INT_P (XEXP (addr, 1)))
2091 
        {
2092 
          tmpaddend = INTVAL (XEXP (addr, 1));
2093 
          addr = XEXP (addr, 0);
2094 
        }
2095 
      else
2096 
        return false;
2097 
    }
2098 
  else
2099 
    if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr))
2100 
        return false;
2101 
 
2102 
  if (symref)
2103 
    *symref = addr;
2104 
  if (addend)
2105 
    *addend = tmpaddend;
2106 
 
2107 
  return true;
2108 
}
2109 
 
2110 
 
2111 
/* Return true if the address in OP is valid for constraint letter C
2112 
   if wrapped in a MEM rtx.  Set LIT_POOL_OK to true if it literal
2113 
   pool MEMs should be accepted.  Only the Q, R, S, T constraint
2114 
   letters are allowed for C.  */
2115 
 
2116 
static int
2117 
s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2118 
{
2119 
  struct s390_address addr;
2120 
  bool decomposed = false;
2121 
 
2122 
  /* This check makes sure that no symbolic address (except literal
2123 
     pool references) are accepted by the R or T constraints.  */
2124 
  if (s390_symref_operand_p (op, NULL, NULL))
2125 
    return 0;
2126 
 
2127 
  /* Ensure literal pool references are only accepted if LIT_POOL_OK.  */
2128 
  if (!lit_pool_ok)
2129 
    {
2130 
      if (!s390_decompose_address (op, &addr))
2131 
        return 0;
2132 
      if (addr.literal_pool)
2133 
        return 0;
2134 
      decomposed = true;
2135 
    }
2136 
 
2137 
  switch (c)
2138 
    {
2139 
    case 'Q': /* no index short displacement */
2140 
      if (!decomposed && !s390_decompose_address (op, &addr))
2141 
        return 0;
2142 
      if (addr.indx)
2143 
        return 0;
2144 
      if (!s390_short_displacement (addr.disp))
2145 
        return 0;
2146 
      break;
2147 
 
2148 
    case 'R': /* with index short displacement */
2149 
      if (TARGET_LONG_DISPLACEMENT)
2150 
        {
2151 
          if (!decomposed && !s390_decompose_address (op, &addr))
2152 
            return 0;
2153 
          if (!s390_short_displacement (addr.disp))
2154 
            return 0;
2155 
        }
2156 
      /* Any invalid address here will be fixed up by reload,
2157 
         so accept it for the most generic constraint.  */
2158 
      break;
2159 
 
2160 
    case 'S': /* no index long displacement */
2161 
      if (!TARGET_LONG_DISPLACEMENT)
2162 
        return 0;
2163 
      if (!decomposed && !s390_decompose_address (op, &addr))
2164 
        return 0;
2165 
      if (addr.indx)
2166 
        return 0;
2167 
      if (s390_short_displacement (addr.disp))
2168 
        return 0;
2169 
      break;
2170 
 
2171 
    case 'T': /* with index long displacement */
2172 
      if (!TARGET_LONG_DISPLACEMENT)
2173 
        return 0;
2174 
      /* Any invalid address here will be fixed up by reload,
2175 
         so accept it for the most generic constraint.  */
2176 
      if ((decomposed || s390_decompose_address (op, &addr))
2177 
          && s390_short_displacement (addr.disp))
2178 
        return 0;
2179 
      break;
2180 
    default:
2181 
      return 0;
2182 
    }
2183 
  return 1;
2184 
}
2185 
 
2186 
 
2187 
/* Evaluates constraint strings described by the regular expression
2188 
   ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2189 
   the constraint given in STR, or 0 else.  */
2190 
 
2191 
int
2192 
s390_mem_constraint (const char *str, rtx op)
2193 
{
2194 
  char c = str[0];
2195 
 
2196 
  switch (c)
2197 
    {
2198 
    case 'A':
2199 
      /* Check for offsettable variants of memory constraints.  */
2200 
      if (!MEM_P (op) || MEM_VOLATILE_P (op))
2201 
        return 0;
2202 
      if ((reload_completed || reload_in_progress)
2203 
          ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2204 
        return 0;
2205 
      return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2206 
    case 'B':
2207 
      /* Check for non-literal-pool variants of memory constraints.  */
2208 
      if (!MEM_P (op))
2209 
        return 0;
2210 
      return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2211 
    case 'Q':
2212 
    case 'R':
2213 
    case 'S':
2214 
    case 'T':
2215 
      if (GET_CODE (op) != MEM)
2216 
        return 0;
2217 
      return s390_check_qrst_address (c, XEXP (op, 0), true);
2218 
    case 'U':
2219 
      return (s390_check_qrst_address ('Q', op, true)
2220 
              || s390_check_qrst_address ('R', op, true));
2221 
    case 'W':
2222 
      return (s390_check_qrst_address ('S', op, true)
2223 
              || s390_check_qrst_address ('T', op, true));
2224 
    case 'Y':
2225 
      /* Simply check for the basic form of a shift count.  Reload will
2226 
         take care of making sure we have a proper base register.  */
2227 
      if (!s390_decompose_shift_count (op, NULL, NULL))
2228 
        return 0;
2229 
      break;
2230 
    case 'Z':
2231 
      return s390_check_qrst_address (str[1], op, true);
2232 
    default:
2233 
      return 0;
2234 
    }
2235 
  return 1;
2236 
}
2237 
 
2238 
 
2239 
/* Evaluates constraint strings starting with letter O.  Input
2240 
   parameter C is the second letter following the "O" in the constraint
2241 
   string. Returns 1 if VALUE meets the respective constraint and 0
2242 
   otherwise.  */
2243 
 
2244 
int
2245 
s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2246 
{
2247 
  if (!TARGET_EXTIMM)
2248 
    return 0;
2249 
 
2250 
  switch (c)
2251 
    {
2252 
    case 's':
2253 
      return trunc_int_for_mode (value, SImode) == value;
2254 
 
2255 
    case 'p':
2256 
      return value == 0
2257 
        || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2258 
 
2259 
    case 'n':
2260 
      return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2261 
 
2262 
    default:
2263 
      gcc_unreachable ();
2264 
    }
2265 
}
2266 
 
2267 
 
2268 
/* Evaluates constraint strings starting with letter N.  Parameter STR
2269 
   contains the letters following letter "N" in the constraint string.
2270 
   Returns true if VALUE matches the constraint.  */
2271 
 
2272 
int
2273 
s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2274 
{
2275 
  enum machine_mode mode, part_mode;
2276 
  int def;
2277 
  int part, part_goal;
2278 
 
2279 
 
2280 
  if (str[0] == 'x')
2281 
    part_goal = -1;
2282 
  else
2283 
    part_goal = str[0] - '0';
2284 
 
2285 
  switch (str[1])
2286 
    {
2287 
    case 'Q':
2288 
      part_mode = QImode;
2289 
      break;
2290 
    case 'H':
2291 
      part_mode = HImode;
2292 
      break;
2293 
    case 'S':
2294 
      part_mode = SImode;
2295 
      break;
2296 
    default:
2297 
      return 0;
2298 
    }
2299 
 
2300 
  switch (str[2])
2301 
    {
2302 
    case 'H':
2303 
      mode = HImode;
2304 
      break;
2305 
    case 'S':
2306 
      mode = SImode;
2307 
      break;
2308 
    case 'D':
2309 
      mode = DImode;
2310 
      break;
2311 
    default:
2312 
      return 0;
2313 
    }
2314 
 
2315 
  switch (str[3])
2316 
    {
2317 
    case '0':
2318 
      def = 0;
2319 
      break;
2320 
    case 'F':
2321 
      def = -1;
2322 
      break;
2323 
    default:
2324 
      return 0;
2325 
    }
2326 
 
2327 
  if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2328 
    return 0;
2329 
 
2330 
  part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2331 
  if (part < 0)
2332 
    return 0;
2333 
  if (part_goal != -1 && part_goal != part)
2334 
    return 0;
2335 
 
2336 
  return 1;
2337 
}
2338 
 
2339 
 
2340 
/* Returns true if the input parameter VALUE is a float zero.  */
2341 
 
2342 
int
2343 
s390_float_const_zero_p (rtx value)
2344 
{
2345 
  return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2346 
          && value == CONST0_RTX (GET_MODE (value)));
2347 
}
2348 
 
2349 
/* Implement TARGET_REGISTER_MOVE_COST.  */
2350 
 
2351 
static int
2352 
s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2353 
                         reg_class_t from, reg_class_t to)
2354 
{
2355 
/* On s390, copy between fprs and gprs is expensive.  */
2356 
  if ((reg_classes_intersect_p (from, GENERAL_REGS)
2357 
       && reg_classes_intersect_p (to, FP_REGS))
2358 
      || (reg_classes_intersect_p (from, FP_REGS)
2359 
          && reg_classes_intersect_p (to, GENERAL_REGS)))
2360 
    return 10;
2361 
 
2362 
  return 1;
2363 
}
2364 
 
2365 
/* Implement TARGET_MEMORY_MOVE_COST.  */
2366 
 
2367 
static int
2368 
s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2369 
                       reg_class_t rclass ATTRIBUTE_UNUSED,
2370 
                       bool in ATTRIBUTE_UNUSED)
2371 
{
2372 
  return 1;
2373 
}
2374 
 
2375 
/* Compute a (partial) cost for rtx X.  Return true if the complete
2376 
   cost has been computed, and false if subexpressions should be
2377 
   scanned.  In either case, *TOTAL contains the cost result.
2378 
   CODE contains GET_CODE (x), OUTER_CODE contains the code
2379 
   of the superexpression of x.  */
2380 
 
2381 
static bool
2382 
s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2383 
                int *total, bool speed ATTRIBUTE_UNUSED)
2384 
{
2385 
  switch (code)
2386 
    {
2387 
    case CONST:
2388 
    case CONST_INT:
2389 
    case LABEL_REF:
2390 
    case SYMBOL_REF:
2391 
    case CONST_DOUBLE:
2392 
    case MEM:
2393 
      *total = 0;
2394 
      return true;
2395 
 
2396 
    case ASHIFT:
2397 
    case ASHIFTRT:
2398 
    case LSHIFTRT:
2399 
    case ROTATE:
2400 
    case ROTATERT:
2401 
    case AND:
2402 
    case IOR:
2403 
    case XOR:
2404 
    case NEG:
2405 
    case NOT:
2406 
      *total = COSTS_N_INSNS (1);
2407 
      return false;
2408 
 
2409 
    case PLUS:
2410 
    case MINUS:
2411 
      *total = COSTS_N_INSNS (1);
2412 
      return false;
2413 
 
2414 
    case MULT:
2415 
      switch (GET_MODE (x))
2416 
        {
2417 
        case SImode:
2418 
          {
2419 
            rtx left = XEXP (x, 0);
2420 
            rtx right = XEXP (x, 1);
2421 
            if (GET_CODE (right) == CONST_INT
2422 
                && CONST_OK_FOR_K (INTVAL (right)))
2423 
              *total = s390_cost->mhi;
2424 
            else if (GET_CODE (left) == SIGN_EXTEND)
2425 
              *total = s390_cost->mh;
2426 
            else
2427 
              *total = s390_cost->ms;  /* msr, ms, msy */
2428 
            break;
2429 
          }
2430 
        case DImode:
2431 
          {
2432 
            rtx left = XEXP (x, 0);
2433 
            rtx right = XEXP (x, 1);
2434 
            if (TARGET_ZARCH)
2435 
              {
2436 
                if (GET_CODE (right) == CONST_INT
2437 
                    && CONST_OK_FOR_K (INTVAL (right)))
2438 
                  *total = s390_cost->mghi;
2439 
                else if (GET_CODE (left) == SIGN_EXTEND)
2440 
                  *total = s390_cost->msgf;
2441 
                else
2442 
                  *total = s390_cost->msg;  /* msgr, msg */
2443 
              }
2444 
            else /* TARGET_31BIT */
2445 
              {
2446 
                if (GET_CODE (left) == SIGN_EXTEND
2447 
                    && GET_CODE (right) == SIGN_EXTEND)
2448 
                  /* mulsidi case: mr, m */
2449 
                  *total = s390_cost->m;
2450 
                else if (GET_CODE (left) == ZERO_EXTEND
2451 
                         && GET_CODE (right) == ZERO_EXTEND
2452 
                         && TARGET_CPU_ZARCH)
2453 
                  /* umulsidi case: ml, mlr */
2454 
                  *total = s390_cost->ml;
2455 
                else
2456 
                  /* Complex calculation is required.  */
2457 
                  *total = COSTS_N_INSNS (40);
2458 
              }
2459 
            break;
2460 
          }
2461 
        case SFmode:
2462 
        case DFmode:
2463 
          *total = s390_cost->mult_df;
2464 
          break;
2465 
        case TFmode:
2466 
          *total = s390_cost->mxbr;
2467 
          break;
2468 
        default:
2469 
          return false;
2470 
        }
2471 
      return false;
2472 
 
2473 
    case FMA:
2474 
      switch (GET_MODE (x))
2475 
        {
2476 
        case DFmode:
2477 
          *total = s390_cost->madbr;
2478 
          break;
2479 
        case SFmode:
2480 
          *total = s390_cost->maebr;
2481 
          break;
2482 
        default:
2483 
          return false;
2484 
        }
2485 
      /* Negate in the third argument is free: FMSUB.  */
2486 
      if (GET_CODE (XEXP (x, 2)) == NEG)
2487 
        {
2488 
          *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2489 
                     + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2490 
                     + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2491 
          return true;
2492 
        }
2493 
      return false;
2494 
 
2495 
    case UDIV:
2496 
    case UMOD:
2497 
      if (GET_MODE (x) == TImode)              /* 128 bit division */
2498 
        *total = s390_cost->dlgr;
2499 
      else if (GET_MODE (x) == DImode)
2500 
        {
2501 
          rtx right = XEXP (x, 1);
2502 
          if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2503 
            *total = s390_cost->dlr;
2504 
          else                                 /* 64 by 64 bit division */
2505 
            *total = s390_cost->dlgr;
2506 
        }
2507 
      else if (GET_MODE (x) == SImode)         /* 32 bit division */
2508 
        *total = s390_cost->dlr;
2509 
      return false;
2510 
 
2511 
    case DIV:
2512 
    case MOD:
2513 
      if (GET_MODE (x) == DImode)
2514 
        {
2515 
          rtx right = XEXP (x, 1);
2516 
          if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2517 
            if (TARGET_ZARCH)
2518 
              *total = s390_cost->dsgfr;
2519 
            else
2520 
              *total = s390_cost->dr;
2521 
          else                                 /* 64 by 64 bit division */
2522 
            *total = s390_cost->dsgr;
2523 
        }
2524 
      else if (GET_MODE (x) == SImode)         /* 32 bit division */
2525 
        *total = s390_cost->dlr;
2526 
      else if (GET_MODE (x) == SFmode)
2527 
        {
2528 
          *total = s390_cost->debr;
2529 
        }
2530 
      else if (GET_MODE (x) == DFmode)
2531 
        {
2532 
          *total = s390_cost->ddbr;
2533 
        }
2534 
      else if (GET_MODE (x) == TFmode)
2535 
        {
2536 
          *total = s390_cost->dxbr;
2537 
        }
2538 
      return false;
2539 
 
2540 
    case SQRT:
2541 
      if (GET_MODE (x) == SFmode)
2542 
        *total = s390_cost->sqebr;
2543 
      else if (GET_MODE (x) == DFmode)
2544 
        *total = s390_cost->sqdbr;
2545 
      else /* TFmode */
2546 
        *total = s390_cost->sqxbr;
2547 
      return false;
2548 
 
2549 
    case SIGN_EXTEND:
2550 
    case ZERO_EXTEND:
2551 
      if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2552 
          || outer_code == PLUS || outer_code == MINUS
2553 
          || outer_code == COMPARE)
2554 
        *total = 0;
2555 
      return false;
2556 
 
2557 
    case COMPARE:
2558 
      *total = COSTS_N_INSNS (1);
2559 
      if (GET_CODE (XEXP (x, 0)) == AND
2560 
          && GET_CODE (XEXP (x, 1)) == CONST_INT
2561 
          && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2562 
        {
2563 
          rtx op0 = XEXP (XEXP (x, 0), 0);
2564 
          rtx op1 = XEXP (XEXP (x, 0), 1);
2565 
          rtx op2 = XEXP (x, 1);
2566 
 
2567 
          if (memory_operand (op0, GET_MODE (op0))
2568 
              && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2569 
            return true;
2570 
          if (register_operand (op0, GET_MODE (op0))
2571 
              && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2572 
            return true;
2573 
        }
2574 
      return false;
2575 
 
2576 
    default:
2577 
      return false;
2578 
    }
2579 
}
2580 
 
2581 
/* Return the cost of an address rtx ADDR.  */
2582 
 
2583 
static int
2584 
s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2585 
{
2586 
  struct s390_address ad;
2587 
  if (!s390_decompose_address (addr, &ad))
2588 
    return 1000;
2589 
 
2590 
  return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2591 
}
2592 
 
2593 
/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2594 
   otherwise return 0.  */
2595 
 
2596 
int
2597 
tls_symbolic_operand (rtx op)
2598 
{
2599 
  if (GET_CODE (op) != SYMBOL_REF)
2600 
    return 0;
2601 
  return SYMBOL_REF_TLS_MODEL (op);
2602 
}
2603 
 
2604 
/* Split DImode access register reference REG (on 64-bit) into its constituent
2605 
   low and high parts, and store them into LO and HI.  Note that gen_lowpart/
2606 
   gen_highpart cannot be used as they assume all registers are word-sized,
2607 
   while our access registers have only half that size.  */
2608 
 
2609 
void
2610 
s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2611 
{
2612 
  gcc_assert (TARGET_64BIT);
2613 
  gcc_assert (ACCESS_REG_P (reg));
2614 
  gcc_assert (GET_MODE (reg) == DImode);
2615 
  gcc_assert (!(REGNO (reg) & 1));
2616 
 
2617 
  *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2618 
  *hi = gen_rtx_REG (SImode, REGNO (reg));
2619 
}
2620 
 
2621 
/* Return true if OP contains a symbol reference */
2622 
 
2623 
bool
2624 
symbolic_reference_mentioned_p (rtx op)
2625 
{
2626 
  const char *fmt;
2627 
  int i;
2628 
 
2629 
  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2630 
    return 1;
2631 
 
2632 
  fmt = GET_RTX_FORMAT (GET_CODE (op));
2633 
  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2634 
    {
2635 
      if (fmt[i] == 'E')
2636 
        {
2637 
          int j;
2638 
 
2639 
          for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2640 
            if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2641 
              return 1;
2642 
        }
2643 
 
2644 
      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2645 
        return 1;
2646 
    }
2647 
 
2648 
  return 0;
2649 
}
2650 
 
2651 
/* Return true if OP contains a reference to a thread-local symbol.  */
2652 
 
2653 
bool
2654 
tls_symbolic_reference_mentioned_p (rtx op)
2655 
{
2656 
  const char *fmt;
2657 
  int i;
2658 
 
2659 
  if (GET_CODE (op) == SYMBOL_REF)
2660 
    return tls_symbolic_operand (op);
2661 
 
2662 
  fmt = GET_RTX_FORMAT (GET_CODE (op));
2663 
  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2664 
    {
2665 
      if (fmt[i] == 'E')
2666 
        {
2667 
          int j;
2668 
 
2669 
          for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2670 
            if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2671 
              return true;
2672 
        }
2673 
 
2674 
      else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2675 
        return true;
2676 
    }
2677 
 
2678 
  return false;
2679 
}
2680 
 
2681 
 
2682 
/* Return true if OP is a legitimate general operand when
2683 
   generating PIC code.  It is given that flag_pic is on
2684 
   and that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
2685 
 
2686 
int
2687 
legitimate_pic_operand_p (rtx op)
2688 
{
2689 
  /* Accept all non-symbolic constants.  */
2690 
  if (!SYMBOLIC_CONST (op))
2691 
    return 1;
2692 
 
2693 
  /* Reject everything else; must be handled
2694 
     via emit_symbolic_move.  */
2695 
  return 0;
2696 
}
2697 
 
2698 
/* Returns true if the constant value OP is a legitimate general operand.
2699 
   It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
2700 
 
2701 
static bool
2702 
s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2703 
{
2704 
  /* Accept all non-symbolic constants.  */
2705 
  if (!SYMBOLIC_CONST (op))
2706 
    return 1;
2707 
 
2708 
  /* Accept immediate LARL operands.  */
2709 
  if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2710 
    return 1;
2711 
 
2712 
  /* Thread-local symbols are never legal constants.  This is
2713 
     so that emit_call knows that computing such addresses
2714 
     might require a function call.  */
2715 
  if (TLS_SYMBOLIC_CONST (op))
2716 
    return 0;
2717 
 
2718 
  /* In the PIC case, symbolic constants must *not* be
2719 
     forced into the literal pool.  We accept them here,
2720 
     so that they will be handled by emit_symbolic_move.  */
2721 
  if (flag_pic)
2722 
    return 1;
2723 
 
2724 
  /* All remaining non-PIC symbolic constants are
2725 
     forced into the literal pool.  */
2726 
  return 0;
2727 
}
2728 
 
2729 
/* Determine if it's legal to put X into the constant pool.  This
2730 
   is not possible if X contains the address of a symbol that is
2731 
   not constant (TLS) or not known at final link time (PIC).  */
2732 
 
2733 
static bool
2734 
s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2735 
{
2736 
  switch (GET_CODE (x))
2737 
    {
2738 
    case CONST_INT:
2739 
    case CONST_DOUBLE:
2740 
      /* Accept all non-symbolic constants.  */
2741 
      return false;
2742 
 
2743 
    case LABEL_REF:
2744 
      /* Labels are OK iff we are non-PIC.  */
2745 
      return flag_pic != 0;
2746 
 
2747 
    case SYMBOL_REF:
2748 
      /* 'Naked' TLS symbol references are never OK,
2749 
         non-TLS symbols are OK iff we are non-PIC.  */
2750 
      if (tls_symbolic_operand (x))
2751 
        return true;
2752 
      else
2753 
        return flag_pic != 0;
2754 
 
2755 
    case CONST:
2756 
      return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2757 
    case PLUS:
2758 
    case MINUS:
2759 
      return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2760 
             || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2761 
 
2762 
    case UNSPEC:
2763 
      switch (XINT (x, 1))
2764 
        {
2765 
        /* Only lt-relative or GOT-relative UNSPECs are OK.  */
2766 
        case UNSPEC_LTREL_OFFSET:
2767 
        case UNSPEC_GOT:
2768 
        case UNSPEC_GOTOFF:
2769 
        case UNSPEC_PLTOFF:
2770 
        case UNSPEC_TLSGD:
2771 
        case UNSPEC_TLSLDM:
2772 
        case UNSPEC_NTPOFF:
2773 
        case UNSPEC_DTPOFF:
2774 
        case UNSPEC_GOTNTPOFF:
2775 
        case UNSPEC_INDNTPOFF:
2776 
          return false;
2777 
 
2778 
        /* If the literal pool shares the code section, be put
2779 
           execute template placeholders into the pool as well.  */
2780 
        case UNSPEC_INSN:
2781 
          return TARGET_CPU_ZARCH;
2782 
 
2783 
        default:
2784 
          return true;
2785 
        }
2786 
      break;
2787 
 
2788 
    default:
2789 
      gcc_unreachable ();
2790 
    }
2791 
}
2792 
 
2793 
/* Returns true if the constant value OP is a legitimate general
2794 
   operand during and after reload.  The difference to
2795 
   legitimate_constant_p is that this function will not accept
2796 
   a constant that would need to be forced to the literal pool
2797 
   before it can be used as operand.
2798 
   This function accepts all constants which can be loaded directly
2799 
   into a GPR.  */
2800 
 
2801 
bool
2802 
legitimate_reload_constant_p (rtx op)
2803 
{
2804 
  /* Accept la(y) operands.  */
2805 
  if (GET_CODE (op) == CONST_INT
2806 
      && DISP_IN_RANGE (INTVAL (op)))
2807 
    return true;
2808 
 
2809 
  /* Accept l(g)hi/l(g)fi operands.  */
2810 
  if (GET_CODE (op) == CONST_INT
2811 
      && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2812 
    return true;
2813 
 
2814 
  /* Accept lliXX operands.  */
2815 
  if (TARGET_ZARCH
2816 
      && GET_CODE (op) == CONST_INT
2817 
      && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2818 
      && s390_single_part (op, word_mode, HImode, 0) >= 0)
2819 
  return true;
2820 
 
2821 
  if (TARGET_EXTIMM
2822 
      && GET_CODE (op) == CONST_INT
2823 
      && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2824 
      && s390_single_part (op, word_mode, SImode, 0) >= 0)
2825 
    return true;
2826 
 
2827 
  /* Accept larl operands.  */
2828 
  if (TARGET_CPU_ZARCH
2829 
      && larl_operand (op, VOIDmode))
2830 
    return true;
2831 
 
2832 
  /* Accept floating-point zero operands that fit into a single GPR.  */
2833 
  if (GET_CODE (op) == CONST_DOUBLE
2834 
      && s390_float_const_zero_p (op)
2835 
      && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2836 
    return true;
2837 
 
2838 
  /* Accept double-word operands that can be split.  */
2839 
  if (GET_CODE (op) == CONST_INT
2840 
      && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2841 
    {
2842 
      enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2843 
      rtx hi = operand_subword (op, 0, 0, dword_mode);
2844 
      rtx lo = operand_subword (op, 1, 0, dword_mode);
2845 
      return legitimate_reload_constant_p (hi)
2846 
             && legitimate_reload_constant_p (lo);
2847 
    }
2848 
 
2849 
  /* Everything else cannot be handled without reload.  */
2850 
  return false;
2851 
}
2852 
 
2853 
/* Returns true if the constant value OP is a legitimate fp operand
2854 
   during and after reload.
2855 
   This function accepts all constants which can be loaded directly
2856 
   into an FPR.  */
2857 
 
2858 
static bool
2859 
legitimate_reload_fp_constant_p (rtx op)
2860 
{
2861 
  /* Accept floating-point zero operands if the load zero instruction
2862 
     can be used.  */
2863 
  if (TARGET_Z196
2864 
      && GET_CODE (op) == CONST_DOUBLE
2865 
      && s390_float_const_zero_p (op))
2866 
    return true;
2867 
 
2868 
  return false;
2869 
}
2870 
 
2871 
/* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2872 
   return the class of reg to actually use.  */
2873 
 
2874 
static reg_class_t
2875 
s390_preferred_reload_class (rtx op, reg_class_t rclass)
2876 
{
2877 
  switch (GET_CODE (op))
2878 
    {
2879 
      /* Constants we cannot reload into general registers
2880 
         must be forced into the literal pool.  */
2881 
      case CONST_DOUBLE:
2882 
      case CONST_INT:
2883 
        if (reg_class_subset_p (GENERAL_REGS, rclass)
2884 
            && legitimate_reload_constant_p (op))
2885 
          return GENERAL_REGS;
2886 
        else if (reg_class_subset_p (ADDR_REGS, rclass)
2887 
                 && legitimate_reload_constant_p (op))
2888 
          return ADDR_REGS;
2889 
        else if (reg_class_subset_p (FP_REGS, rclass)
2890 
                 && legitimate_reload_fp_constant_p (op))
2891 
          return FP_REGS;
2892 
        return NO_REGS;
2893 
 
2894 
      /* If a symbolic constant or a PLUS is reloaded,
2895 
         it is most likely being used as an address, so
2896 
         prefer ADDR_REGS.  If 'class' is not a superset
2897 
         of ADDR_REGS, e.g. FP_REGS, reject this reload.  */
2898 
      case LABEL_REF:
2899 
      case SYMBOL_REF:
2900 
      case CONST:
2901 
        if (!legitimate_reload_constant_p (op))
2902 
          return NO_REGS;
2903 
        /* fallthrough */
2904 
      case PLUS:
2905 
        /* load address will be used.  */
2906 
        if (reg_class_subset_p (ADDR_REGS, rclass))
2907 
          return ADDR_REGS;
2908 
        else
2909 
          return NO_REGS;
2910 
 
2911 
      default:
2912 
        break;
2913 
    }
2914 
 
2915 
  return rclass;
2916 
}
2917 
 
2918 
/* Return true if ADDR is SYMBOL_REF + addend with addend being a
2919 
   multiple of ALIGNMENT and the SYMBOL_REF being naturally
2920 
   aligned.  */
2921 
 
2922 
bool
2923 
s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2924 
{
2925 
  HOST_WIDE_INT addend;
2926 
  rtx symref;
2927 
 
2928 
  if (!s390_symref_operand_p (addr, &symref, &addend))
2929 
    return false;
2930 
 
2931 
  return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2932 
          && !(addend & (alignment - 1)));
2933 
}
2934 
 
2935 
/* ADDR is moved into REG using larl.  If ADDR isn't a valid larl
2936 
   operand SCRATCH is used to reload the even part of the address and
2937 
   adding one.  */
2938 
 
2939 
void
2940 
s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2941 
{
2942 
  HOST_WIDE_INT addend;
2943 
  rtx symref;
2944 
 
2945 
  if (!s390_symref_operand_p (addr, &symref, &addend))
2946 
    gcc_unreachable ();
2947 
 
2948 
  if (!(addend & 1))
2949 
    /* Easy case.  The addend is even so larl will do fine.  */
2950 
    emit_move_insn (reg, addr);
2951 
  else
2952 
    {
2953 
      /* We can leave the scratch register untouched if the target
2954 
         register is a valid base register.  */
2955 
      if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2956 
          && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2957 
        scratch = reg;
2958 
 
2959 
      gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2960 
      gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2961 
 
2962 
      if (addend != 1)
2963 
        emit_move_insn (scratch,
2964 
                        gen_rtx_CONST (Pmode,
2965 
                                       gen_rtx_PLUS (Pmode, symref,
2966 
                                                     GEN_INT (addend - 1))));
2967 
      else
2968 
        emit_move_insn (scratch, symref);
2969 
 
2970 
      /* Increment the address using la in order to avoid clobbering cc.  */
2971 
      emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2972 
    }
2973 
}
2974 
 
2975 
/* Generate what is necessary to move between REG and MEM using
2976 
   SCRATCH.  The direction is given by TOMEM.  */
2977 
 
2978 
void
2979 
s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2980 
{
2981 
  /* Reload might have pulled a constant out of the literal pool.
2982 
     Force it back in.  */
2983 
  if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2984 
      || GET_CODE (mem) == CONST)
2985 
    mem = force_const_mem (GET_MODE (reg), mem);
2986 
 
2987 
  gcc_assert (MEM_P (mem));
2988 
 
2989 
  /* For a load from memory we can leave the scratch register
2990 
     untouched if the target register is a valid base register.  */
2991 
  if (!tomem
2992 
      && REGNO (reg) < FIRST_PSEUDO_REGISTER
2993 
      && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2994 
      && GET_MODE (reg) == GET_MODE (scratch))
2995 
    scratch = reg;
2996 
 
2997 
  /* Load address into scratch register.  Since we can't have a
2998 
     secondary reload for a secondary reload we have to cover the case
2999 
     where larl would need a secondary reload here as well.  */
3000 
  s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3001 
 
3002 
  /* Now we can use a standard load/store to do the move.  */
3003 
  if (tomem)
3004 
    emit_move_insn (replace_equiv_address (mem, scratch), reg);
3005 
  else
3006 
    emit_move_insn (reg, replace_equiv_address (mem, scratch));
3007 
}
3008 
 
3009 
/* Inform reload about cases where moving X with a mode MODE to a register in
3010 
   RCLASS requires an extra scratch or immediate register.  Return the class
3011 
   needed for the immediate register.  */
3012 
 
3013 
static reg_class_t
3014 
s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3015 
                       enum machine_mode mode, secondary_reload_info *sri)
3016 
{
3017 
  enum reg_class rclass = (enum reg_class) rclass_i;
3018 
 
3019 
  /* Intermediate register needed.  */
3020 
  if (reg_classes_intersect_p (CC_REGS, rclass))
3021 
    return GENERAL_REGS;
3022 
 
3023 
  if (TARGET_Z10)
3024 
    {
3025 
      HOST_WIDE_INT offset;
3026 
      rtx symref;
3027 
 
3028 
      /* On z10 several optimizer steps may generate larl operands with
3029 
         an odd addend.  */
3030 
      if (in_p
3031 
          && s390_symref_operand_p (x, &symref, &offset)
3032 
          && mode == Pmode
3033 
          && !SYMBOL_REF_ALIGN1_P (symref)
3034 
          && (offset & 1) == 1)
3035 
        sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3036 
                      : CODE_FOR_reloadsi_larl_odd_addend_z10);
3037 
 
3038 
      /* On z10 we need a scratch register when moving QI, TI or floating
3039 
         point mode values from or to a memory location with a SYMBOL_REF
3040 
         or if the symref addend of a SI or DI move is not aligned to the
3041 
         width of the access.  */
3042 
      if (MEM_P (x)
3043 
          && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
3044 
          && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3045 
              || (!TARGET_ZARCH && mode == DImode)
3046 
              || ((mode == HImode || mode == SImode || mode == DImode)
3047 
                  && (!s390_check_symref_alignment (XEXP (x, 0),
3048 
                                                    GET_MODE_SIZE (mode))))))
3049 
        {
3050 
#define __SECONDARY_RELOAD_CASE(M,m)                                    \
3051 
          case M##mode:                                                 \
3052 
            if (TARGET_64BIT)                                           \
3053 
              sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 :    \
3054 
                                  CODE_FOR_reload##m##di_tomem_z10;     \
3055 
            else                                                        \
3056 
              sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 :    \
3057 
                                  CODE_FOR_reload##m##si_tomem_z10;     \
3058 
          break;
3059 
 
3060 
          switch (GET_MODE (x))
3061 
            {
3062 
              __SECONDARY_RELOAD_CASE (QI, qi);
3063 
              __SECONDARY_RELOAD_CASE (HI, hi);
3064 
              __SECONDARY_RELOAD_CASE (SI, si);
3065 
              __SECONDARY_RELOAD_CASE (DI, di);
3066 
              __SECONDARY_RELOAD_CASE (TI, ti);
3067 
              __SECONDARY_RELOAD_CASE (SF, sf);
3068 
              __SECONDARY_RELOAD_CASE (DF, df);
3069 
              __SECONDARY_RELOAD_CASE (TF, tf);
3070 
              __SECONDARY_RELOAD_CASE (SD, sd);
3071 
              __SECONDARY_RELOAD_CASE (DD, dd);
3072 
              __SECONDARY_RELOAD_CASE (TD, td);
3073 
 
3074 
            default:
3075 
              gcc_unreachable ();
3076 
            }
3077 
#undef __SECONDARY_RELOAD_CASE
3078 
        }
3079 
    }
3080 
 
3081 
  /* We need a scratch register when loading a PLUS expression which
3082 
     is not a legitimate operand of the LOAD ADDRESS instruction.  */
3083 
  if (in_p && s390_plus_operand (x, mode))
3084 
    sri->icode = (TARGET_64BIT ?
3085 
                  CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3086 
 
3087 
  /* Performing a multiword move from or to memory we have to make sure the
3088 
     second chunk in memory is addressable without causing a displacement
3089 
     overflow.  If that would be the case we calculate the address in
3090 
     a scratch register.  */
3091 
  if (MEM_P (x)
3092 
      && GET_CODE (XEXP (x, 0)) == PLUS
3093 
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3094 
      && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3095 
                         + GET_MODE_SIZE (mode) - 1))
3096 
    {
3097 
      /* For GENERAL_REGS a displacement overflow is no problem if occurring
3098 
         in a s_operand address since we may fallback to lm/stm.  So we only
3099 
         have to care about overflows in the b+i+d case.  */
3100 
      if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3101 
           && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3102 
           && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3103 
          /* For FP_REGS no lm/stm is available so this check is triggered
3104 
             for displacement overflows in b+i+d and b+d like addresses.  */
3105 
          || (reg_classes_intersect_p (FP_REGS, rclass)
3106 
              && s390_class_max_nregs (FP_REGS, mode) > 1))
3107 
        {
3108 
          if (in_p)
3109 
            sri->icode = (TARGET_64BIT ?
3110 
                          CODE_FOR_reloaddi_nonoffmem_in :
3111 
                          CODE_FOR_reloadsi_nonoffmem_in);
3112 
          else
3113 
            sri->icode = (TARGET_64BIT ?
3114 
                          CODE_FOR_reloaddi_nonoffmem_out :
3115 
                          CODE_FOR_reloadsi_nonoffmem_out);
3116 
        }
3117 
    }
3118 
 
3119 
  /* A scratch address register is needed when a symbolic constant is
3120 
     copied to r0 compiling with -fPIC.  In other cases the target
3121 
     register might be used as temporary (see legitimize_pic_address).  */
3122 
  if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3123 
    sri->icode = (TARGET_64BIT ?
3124 
                  CODE_FOR_reloaddi_PIC_addr :
3125 
                  CODE_FOR_reloadsi_PIC_addr);
3126 
 
3127 
  /* Either scratch or no register needed.  */
3128 
  return NO_REGS;
3129 
}
3130 
 
3131 
/* Generate code to load SRC, which is PLUS that is not a
3132 
   legitimate operand for the LA instruction, into TARGET.
3133 
   SCRATCH may be used as scratch register.  */
3134 
 
3135 
void
3136 
s390_expand_plus_operand (rtx target, rtx src,
3137 
                          rtx scratch)
3138 
{
3139 
  rtx sum1, sum2;
3140 
  struct s390_address ad;
3141 
 
3142 
  /* src must be a PLUS; get its two operands.  */
3143 
  gcc_assert (GET_CODE (src) == PLUS);
3144 
  gcc_assert (GET_MODE (src) == Pmode);
3145 
 
3146 
  /* Check if any of the two operands is already scheduled
3147 
     for replacement by reload.  This can happen e.g. when
3148 
     float registers occur in an address.  */
3149 
  sum1 = find_replacement (&XEXP (src, 0));
3150 
  sum2 = find_replacement (&XEXP (src, 1));
3151 
  src = gen_rtx_PLUS (Pmode, sum1, sum2);
3152 
 
3153 
  /* If the address is already strictly valid, there's nothing to do.  */
3154 
  if (!s390_decompose_address (src, &ad)
3155 
      || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3156 
      || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3157 
    {
3158 
      /* Otherwise, one of the operands cannot be an address register;
3159 
         we reload its value into the scratch register.  */
3160 
      if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3161 
        {
3162 
          emit_move_insn (scratch, sum1);
3163 
          sum1 = scratch;
3164 
        }
3165 
      if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3166 
        {
3167 
          emit_move_insn (scratch, sum2);
3168 
          sum2 = scratch;
3169 
        }
3170 
 
3171 
      /* According to the way these invalid addresses are generated
3172 
         in reload.c, it should never happen (at least on s390) that
3173 
         *neither* of the PLUS components, after find_replacements
3174 
         was applied, is an address register.  */
3175 
      if (sum1 == scratch && sum2 == scratch)
3176 
        {
3177 
          debug_rtx (src);
3178 
          gcc_unreachable ();
3179 
        }
3180 
 
3181 
      src = gen_rtx_PLUS (Pmode, sum1, sum2);
3182 
    }
3183 
 
3184 
  /* Emit the LOAD ADDRESS pattern.  Note that reload of PLUS
3185 
     is only ever performed on addresses, so we can mark the
3186 
     sum as legitimate for LA in any case.  */
3187 
  s390_load_address (target, src);
3188 
}
3189 
 
3190 
 
3191 
/* Return true if ADDR is a valid memory address.
3192 
   STRICT specifies whether strict register checking applies.  */
3193 
 
3194 
static bool
3195 
s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3196 
{
3197 
  struct s390_address ad;
3198 
 
3199 
  if (TARGET_Z10
3200 
      && larl_operand (addr, VOIDmode)
3201 
      && (mode == VOIDmode
3202 
          || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3203 
    return true;
3204 
 
3205 
  if (!s390_decompose_address (addr, &ad))
3206 
    return false;
3207 
 
3208 
  if (strict)
3209 
    {
3210 
      if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3211 
        return false;
3212 
 
3213 
      if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3214 
        return false;
3215 
    }
3216 
  else
3217 
    {
3218 
      if (ad.base
3219 
          && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3220 
               || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3221 
        return false;
3222 
 
3223 
      if (ad.indx
3224 
          && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3225 
               || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3226 
          return false;
3227 
    }
3228 
  return true;
3229 
}
3230 
 
3231 
/* Return true if OP is a valid operand for the LA instruction.
3232 
   In 31-bit, we need to prove that the result is used as an
3233 
   address, as LA performs only a 31-bit addition.  */
3234 
 
3235 
bool
3236 
legitimate_la_operand_p (rtx op)
3237 
{
3238 
  struct s390_address addr;
3239 
  if (!s390_decompose_address (op, &addr))
3240 
    return false;
3241 
 
3242 
  return (TARGET_64BIT || addr.pointer);
3243 
}
3244 
 
3245 
/* Return true if it is valid *and* preferable to use LA to
3246 
   compute the sum of OP1 and OP2.  */
3247 
 
3248 
bool
3249 
preferred_la_operand_p (rtx op1, rtx op2)
3250 
{
3251 
  struct s390_address addr;
3252 
 
3253 
  if (op2 != const0_rtx)
3254 
    op1 = gen_rtx_PLUS (Pmode, op1, op2);
3255 
 
3256 
  if (!s390_decompose_address (op1, &addr))
3257 
    return false;
3258 
  if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3259 
    return false;
3260 
  if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3261 
    return false;
3262 
 
3263 
  /* Avoid LA instructions with index register on z196; it is
3264 
     preferable to use regular add instructions when possible.  */
3265 
  if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3266 
    return false;
3267 
 
3268 
  if (!TARGET_64BIT && !addr.pointer)
3269 
    return false;
3270 
 
3271 
  if (addr.pointer)
3272 
    return true;
3273 
 
3274 
  if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3275 
      || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3276 
    return true;
3277 
 
3278 
  return false;
3279 
}
3280 
 
3281 
/* Emit a forced load-address operation to load SRC into DST.
3282 
   This will use the LOAD ADDRESS instruction even in situations
3283 
   where legitimate_la_operand_p (SRC) returns false.  */
3284 
 
3285 
void
3286 
s390_load_address (rtx dst, rtx src)
3287 
{
3288 
  if (TARGET_64BIT)
3289 
    emit_move_insn (dst, src);
3290 
  else
3291 
    emit_insn (gen_force_la_31 (dst, src));
3292 
}
3293 
 
3294 
/* Return a legitimate reference for ORIG (an address) using the
3295 
   register REG.  If REG is 0, a new pseudo is generated.
3296 
 
3297 
   There are two types of references that must be handled:
3298 
 
3299 
   1. Global data references must load the address from the GOT, via
3300 
      the PIC reg.  An insn is emitted to do this load, and the reg is
3301 
      returned.
3302 
 
3303 
   2. Static data references, constant pool addresses, and code labels
3304 
      compute the address as an offset from the GOT, whose base is in
3305 
      the PIC reg.  Static data objects have SYMBOL_FLAG_LOCAL set to
3306 
      differentiate them from global data objects.  The returned
3307 
      address is the PIC reg + an unspec constant.
3308 
 
3309 
   TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3310 
   reg also appears in the address.  */
3311 
 
3312 
rtx
3313 
legitimize_pic_address (rtx orig, rtx reg)
3314 
{
3315 
  rtx addr = orig;
3316 
  rtx new_rtx = orig;
3317 
  rtx base;
3318 
 
3319 
  gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3320 
 
3321 
  if (GET_CODE (addr) == LABEL_REF
3322 
      || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3323 
    {
3324 
      /* This is a local symbol.  */
3325 
      if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3326 
        {
3327 
          /* Access local symbols PC-relative via LARL.
3328 
             This is the same as in the non-PIC case, so it is
3329 
             handled automatically ...  */
3330 
        }
3331 
      else
3332 
        {
3333 
          /* Access local symbols relative to the GOT.  */
3334 
 
3335 
          rtx temp = reg? reg : gen_reg_rtx (Pmode);
3336 
 
3337 
          if (reload_in_progress || reload_completed)
3338 
            df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3339 
 
3340 
          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3341 
          addr = gen_rtx_CONST (Pmode, addr);
3342 
          addr = force_const_mem (Pmode, addr);
3343 
          emit_move_insn (temp, addr);
3344 
 
3345 
          new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3346 
          if (reg != 0)
3347 
            {
3348 
              s390_load_address (reg, new_rtx);
3349 
              new_rtx = reg;
3350 
            }
3351 
        }
3352 
    }
3353 
  else if (GET_CODE (addr) == SYMBOL_REF)
3354 
    {
3355 
      if (reg == 0)
3356 
        reg = gen_reg_rtx (Pmode);
3357 
 
3358 
      if (flag_pic == 1)
3359 
        {
3360 
          /* Assume GOT offset < 4k.  This is handled the same way
3361 
             in both 31- and 64-bit code (@GOT).  */
3362 
 
3363 
          if (reload_in_progress || reload_completed)
3364 
            df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3365 
 
3366 
          new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3367 
          new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3368 
          new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3369 
          new_rtx = gen_const_mem (Pmode, new_rtx);
3370 
          emit_move_insn (reg, new_rtx);
3371 
          new_rtx = reg;
3372 
        }
3373 
      else if (TARGET_CPU_ZARCH)
3374 
        {
3375 
          /* If the GOT offset might be >= 4k, we determine the position
3376 
             of the GOT entry via a PC-relative LARL (@GOTENT).  */
3377 
 
3378 
          rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3379 
 
3380 
          gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3381 
                      || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3382 
 
3383 
          new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3384 
          new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3385 
          emit_move_insn (temp, new_rtx);
3386 
 
3387 
          new_rtx = gen_const_mem (Pmode, temp);
3388 
          emit_move_insn (reg, new_rtx);
3389 
          new_rtx = reg;
3390 
        }
3391 
      else
3392 
        {
3393 
          /* If the GOT offset might be >= 4k, we have to load it
3394 
             from the literal pool (@GOT).  */
3395 
 
3396 
          rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3397 
 
3398 
          gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3399 
                      || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3400 
 
3401 
          if (reload_in_progress || reload_completed)
3402 
            df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3403 
 
3404 
          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3405 
          addr = gen_rtx_CONST (Pmode, addr);
3406 
          addr = force_const_mem (Pmode, addr);
3407 
          emit_move_insn (temp, addr);
3408 
 
3409 
          new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3410 
          new_rtx = gen_const_mem (Pmode, new_rtx);
3411 
          emit_move_insn (reg, new_rtx);
3412 
          new_rtx = reg;
3413 
        }
3414 
    }
3415 
  else
3416 
    {
3417 
      if (GET_CODE (addr) == CONST)
3418 
        {
3419 
          addr = XEXP (addr, 0);
3420 
          if (GET_CODE (addr) == UNSPEC)
3421 
            {
3422 
              gcc_assert (XVECLEN (addr, 0) == 1);
3423 
              switch (XINT (addr, 1))
3424 
                {
3425 
                  /* If someone moved a GOT-relative UNSPEC
3426 
                     out of the literal pool, force them back in.  */
3427 
                  case UNSPEC_GOTOFF:
3428 
                  case UNSPEC_PLTOFF:
3429 
                    new_rtx = force_const_mem (Pmode, orig);
3430 
                    break;
3431 
 
3432 
                  /* @GOT is OK as is if small.  */
3433 
                  case UNSPEC_GOT:
3434 
                    if (flag_pic == 2)
3435 
                      new_rtx = force_const_mem (Pmode, orig);
3436 
                    break;
3437 
 
3438 
                  /* @GOTENT is OK as is.  */
3439 
                  case UNSPEC_GOTENT:
3440 
                    break;
3441 
 
3442 
                  /* @PLT is OK as is on 64-bit, must be converted to
3443 
                     GOT-relative @PLTOFF on 31-bit.  */
3444 
                  case UNSPEC_PLT:
3445 
                    if (!TARGET_CPU_ZARCH)
3446 
                      {
3447 
                        rtx temp = reg? reg : gen_reg_rtx (Pmode);
3448 
 
3449 
                        if (reload_in_progress || reload_completed)
3450 
                          df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3451 
 
3452 
                        addr = XVECEXP (addr, 0, 0);
3453 
                        addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3454 
                                               UNSPEC_PLTOFF);
3455 
                        addr = gen_rtx_CONST (Pmode, addr);
3456 
                        addr = force_const_mem (Pmode, addr);
3457 
                        emit_move_insn (temp, addr);
3458 
 
3459 
                        new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3460 
                        if (reg != 0)
3461 
                          {
3462 
                            s390_load_address (reg, new_rtx);
3463 
                            new_rtx = reg;
3464 
                          }
3465 
                      }
3466 
                    break;
3467 
 
3468 
                  /* Everything else cannot happen.  */
3469 
                  default:
3470 
                    gcc_unreachable ();
3471 
                }
3472 
            }
3473 
          else
3474 
            gcc_assert (GET_CODE (addr) == PLUS);
3475 
        }
3476 
      if (GET_CODE (addr) == PLUS)
3477 
        {
3478 
          rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3479 
 
3480 
          gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3481 
          gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3482 
 
3483 
          /* Check first to see if this is a constant offset
3484 
             from a local symbol reference.  */
3485 
          if ((GET_CODE (op0) == LABEL_REF
3486 
                || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3487 
              && GET_CODE (op1) == CONST_INT)
3488 
            {
3489 
              if (TARGET_CPU_ZARCH
3490 
                  && larl_operand (op0, VOIDmode)
3491 
                  && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3492 
                  && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3493 
                {
3494 
                  if (INTVAL (op1) & 1)
3495 
                    {
3496 
                      /* LARL can't handle odd offsets, so emit a
3497 
                         pair of LARL and LA.  */
3498 
                      rtx temp = reg? reg : gen_reg_rtx (Pmode);
3499 
 
3500 
                      if (!DISP_IN_RANGE (INTVAL (op1)))
3501 
                        {
3502 
                          HOST_WIDE_INT even = INTVAL (op1) - 1;
3503 
                          op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3504 
                          op0 = gen_rtx_CONST (Pmode, op0);
3505 
                          op1 = const1_rtx;
3506 
                        }
3507 
 
3508 
                      emit_move_insn (temp, op0);
3509 
                      new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3510 
 
3511 
                      if (reg != 0)
3512 
                        {
3513 
                          s390_load_address (reg, new_rtx);
3514 
                          new_rtx = reg;
3515 
                        }
3516 
                    }
3517 
                  else
3518 
                    {
3519 
                      /* If the offset is even, we can just use LARL.
3520 
                         This will happen automatically.  */
3521 
                    }
3522 
                }
3523 
              else
3524 
                {
3525 
                  /* Access local symbols relative to the GOT.  */
3526 
 
3527 
                  rtx temp = reg? reg : gen_reg_rtx (Pmode);
3528 
 
3529 
                  if (reload_in_progress || reload_completed)
3530 
                    df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3531 
 
3532 
                  addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3533 
                                         UNSPEC_GOTOFF);
3534 
                  addr = gen_rtx_PLUS (Pmode, addr, op1);
3535 
                  addr = gen_rtx_CONST (Pmode, addr);
3536 
                  addr = force_const_mem (Pmode, addr);
3537 
                  emit_move_insn (temp, addr);
3538 
 
3539 
                  new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3540 
                  if (reg != 0)
3541 
                    {
3542 
                      s390_load_address (reg, new_rtx);
3543 
                      new_rtx = reg;
3544 
                    }
3545 
                }
3546 
            }
3547 
 
3548 
          /* Now, check whether it is a GOT relative symbol plus offset
3549 
             that was pulled out of the literal pool.  Force it back in.  */
3550 
 
3551 
          else if (GET_CODE (op0) == UNSPEC
3552 
                   && GET_CODE (op1) == CONST_INT
3553 
                   && XINT (op0, 1) == UNSPEC_GOTOFF)
3554 
            {
3555 
              gcc_assert (XVECLEN (op0, 0) == 1);
3556 
 
3557 
              new_rtx = force_const_mem (Pmode, orig);
3558 
            }
3559 
 
3560 
          /* Otherwise, compute the sum.  */
3561 
          else
3562 
            {
3563 
              base = legitimize_pic_address (XEXP (addr, 0), reg);
3564 
              new_rtx  = legitimize_pic_address (XEXP (addr, 1),
3565 
                                             base == reg ? NULL_RTX : reg);
3566 
              if (GET_CODE (new_rtx) == CONST_INT)
3567 
                new_rtx = plus_constant (base, INTVAL (new_rtx));
3568 
              else
3569 
                {
3570 
                  if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3571 
                    {
3572 
                      base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3573 
                      new_rtx = XEXP (new_rtx, 1);
3574 
                    }
3575 
                  new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3576 
                }
3577 
 
3578 
              if (GET_CODE (new_rtx) == CONST)
3579 
                new_rtx = XEXP (new_rtx, 0);
3580 
              new_rtx = force_operand (new_rtx, 0);
3581 
            }
3582 
        }
3583 
    }
3584 
  return new_rtx;
3585 
}
3586 
 
3587 
/* Load the thread pointer into a register.  */
3588 
 
3589 
rtx
3590 
s390_get_thread_pointer (void)
3591 
{
3592 
  rtx tp = gen_reg_rtx (Pmode);
3593 
 
3594 
  emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3595 
  mark_reg_pointer (tp, BITS_PER_WORD);
3596 
 
3597 
  return tp;
3598 
}
3599 
 
3600 
/* Emit a tls call insn. The call target is the SYMBOL_REF stored
3601 
   in s390_tls_symbol which always refers to __tls_get_offset.
3602 
   The returned offset is written to RESULT_REG and an USE rtx is
3603 
   generated for TLS_CALL.  */
3604 
 
3605 
static GTY(()) rtx s390_tls_symbol;
3606 
 
3607 
static void
3608 
s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3609 
{
3610 
  rtx insn;
3611 
 
3612 
  if (!flag_pic)
3613 
    emit_insn (s390_load_got ());
3614 
 
3615 
  if (!s390_tls_symbol)
3616 
    s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3617 
 
3618 
  insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3619 
                         gen_rtx_REG (Pmode, RETURN_REGNUM));
3620 
 
3621 
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3622 
  RTL_CONST_CALL_P (insn) = 1;
3623 
}
3624 
 
3625 
/* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
3626 
   this (thread-local) address.  REG may be used as temporary.  */
3627 
 
3628 
static rtx
3629 
legitimize_tls_address (rtx addr, rtx reg)
3630 
{
3631 
  rtx new_rtx, tls_call, temp, base, r2, insn;
3632 
 
3633 
  if (GET_CODE (addr) == SYMBOL_REF)
3634 
    switch (tls_symbolic_operand (addr))
3635 
      {
3636 
      case TLS_MODEL_GLOBAL_DYNAMIC:
3637 
        start_sequence ();
3638 
        r2 = gen_rtx_REG (Pmode, 2);
3639 
        tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3640 
        new_rtx = gen_rtx_CONST (Pmode, tls_call);
3641 
        new_rtx = force_const_mem (Pmode, new_rtx);
3642 
        emit_move_insn (r2, new_rtx);
3643 
        s390_emit_tls_call_insn (r2, tls_call);
3644 
        insn = get_insns ();
3645 
        end_sequence ();
3646 
 
3647 
        new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3648 
        temp = gen_reg_rtx (Pmode);
3649 
        emit_libcall_block (insn, temp, r2, new_rtx);
3650 
 
3651 
        new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3652 
        if (reg != 0)
3653 
          {
3654 
            s390_load_address (reg, new_rtx);
3655 
            new_rtx = reg;
3656 
          }
3657 
        break;
3658 
 
3659 
      case TLS_MODEL_LOCAL_DYNAMIC:
3660 
        start_sequence ();
3661 
        r2 = gen_rtx_REG (Pmode, 2);
3662 
        tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3663 
        new_rtx = gen_rtx_CONST (Pmode, tls_call);
3664 
        new_rtx = force_const_mem (Pmode, new_rtx);
3665 
        emit_move_insn (r2, new_rtx);
3666 
        s390_emit_tls_call_insn (r2, tls_call);
3667 
        insn = get_insns ();
3668 
        end_sequence ();
3669 
 
3670 
        new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3671 
        temp = gen_reg_rtx (Pmode);
3672 
        emit_libcall_block (insn, temp, r2, new_rtx);
3673 
 
3674 
        new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3675 
        base = gen_reg_rtx (Pmode);
3676 
        s390_load_address (base, new_rtx);
3677 
 
3678 
        new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3679 
        new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3680 
        new_rtx = force_const_mem (Pmode, new_rtx);
3681 
        temp = gen_reg_rtx (Pmode);
3682 
        emit_move_insn (temp, new_rtx);
3683 
 
3684 
        new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3685 
        if (reg != 0)
3686 
          {
3687 
            s390_load_address (reg, new_rtx);
3688 
            new_rtx = reg;
3689 
          }
3690 
        break;
3691 
 
3692 
      case TLS_MODEL_INITIAL_EXEC:
3693 
        if (flag_pic == 1)
3694 
          {
3695 
            /* Assume GOT offset < 4k.  This is handled the same way
3696 
               in both 31- and 64-bit code.  */
3697 
 
3698 
            if (reload_in_progress || reload_completed)
3699 
              df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3700 
 
3701 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3702 
            new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3703 
            new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3704 
            new_rtx = gen_const_mem (Pmode, new_rtx);
3705 
            temp = gen_reg_rtx (Pmode);
3706 
            emit_move_insn (temp, new_rtx);
3707 
          }
3708 
        else if (TARGET_CPU_ZARCH)
3709 
          {
3710 
            /* If the GOT offset might be >= 4k, we determine the position
3711 
               of the GOT entry via a PC-relative LARL.  */
3712 
 
3713 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3714 
            new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3715 
            temp = gen_reg_rtx (Pmode);
3716 
            emit_move_insn (temp, new_rtx);
3717 
 
3718 
            new_rtx = gen_const_mem (Pmode, temp);
3719 
            temp = gen_reg_rtx (Pmode);
3720 
            emit_move_insn (temp, new_rtx);
3721 
          }
3722 
        else if (flag_pic)
3723 
          {
3724 
            /* If the GOT offset might be >= 4k, we have to load it
3725 
               from the literal pool.  */
3726 
 
3727 
            if (reload_in_progress || reload_completed)
3728 
              df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3729 
 
3730 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3731 
            new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3732 
            new_rtx = force_const_mem (Pmode, new_rtx);
3733 
            temp = gen_reg_rtx (Pmode);
3734 
            emit_move_insn (temp, new_rtx);
3735 
 
3736 
            new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3737 
            new_rtx = gen_const_mem (Pmode, new_rtx);
3738 
 
3739 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3740 
            temp = gen_reg_rtx (Pmode);
3741 
            emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3742 
          }
3743 
        else
3744 
          {
3745 
            /* In position-dependent code, load the absolute address of
3746 
               the GOT entry from the literal pool.  */
3747 
 
3748 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3749 
            new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3750 
            new_rtx = force_const_mem (Pmode, new_rtx);
3751 
            temp = gen_reg_rtx (Pmode);
3752 
            emit_move_insn (temp, new_rtx);
3753 
 
3754 
            new_rtx = temp;
3755 
            new_rtx = gen_const_mem (Pmode, new_rtx);
3756 
            new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3757 
            temp = gen_reg_rtx (Pmode);
3758 
            emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3759 
          }
3760 
 
3761 
        new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3762 
        if (reg != 0)
3763 
          {
3764 
            s390_load_address (reg, new_rtx);
3765 
            new_rtx = reg;
3766 
          }
3767 
        break;
3768 
 
3769 
      case TLS_MODEL_LOCAL_EXEC:
3770 
        new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3771 
        new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3772 
        new_rtx = force_const_mem (Pmode, new_rtx);
3773 
        temp = gen_reg_rtx (Pmode);
3774 
        emit_move_insn (temp, new_rtx);
3775 
 
3776 
        new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3777 
        if (reg != 0)
3778 
          {
3779 
            s390_load_address (reg, new_rtx);
3780 
            new_rtx = reg;
3781 
          }
3782 
        break;
3783 
 
3784 
      default:
3785 
        gcc_unreachable ();
3786 
      }
3787 
 
3788 
  else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3789 
    {
3790 
      switch (XINT (XEXP (addr, 0), 1))
3791 
        {
3792 
        case UNSPEC_INDNTPOFF:
3793 
          gcc_assert (TARGET_CPU_ZARCH);
3794 
          new_rtx = addr;
3795 
          break;
3796 
 
3797 
        default:
3798 
          gcc_unreachable ();
3799 
        }
3800 
    }
3801 
 
3802 
  else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3803 
           && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3804 
    {
3805 
      new_rtx = XEXP (XEXP (addr, 0), 0);
3806 
      if (GET_CODE (new_rtx) != SYMBOL_REF)
3807 
        new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3808 
 
3809 
      new_rtx = legitimize_tls_address (new_rtx, reg);
3810 
      new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3811 
      new_rtx = force_operand (new_rtx, 0);
3812 
    }
3813 
 
3814 
  else
3815 
    gcc_unreachable ();  /* for now ... */
3816 
 
3817 
  return new_rtx;
3818 
}
3819 
 
3820 
/* Emit insns making the address in operands[1] valid for a standard
3821 
   move to operands[0].  operands[1] is replaced by an address which
3822 
   should be used instead of the former RTX to emit the move
3823 
   pattern.  */
3824 
 
3825 
void
3826 
emit_symbolic_move (rtx *operands)
3827 
{
3828 
  rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3829 
 
3830 
  if (GET_CODE (operands[0]) == MEM)
3831 
    operands[1] = force_reg (Pmode, operands[1]);
3832 
  else if (TLS_SYMBOLIC_CONST (operands[1]))
3833 
    operands[1] = legitimize_tls_address (operands[1], temp);
3834 
  else if (flag_pic)
3835 
    operands[1] = legitimize_pic_address (operands[1], temp);
3836 
}
3837 
 
3838 
/* Try machine-dependent ways of modifying an illegitimate address X
3839 
   to be legitimate.  If we find one, return the new, valid address.
3840 
 
3841 
   OLDX is the address as it was before break_out_memory_refs was called.
3842 
   In some cases it is useful to look at this to decide what needs to be done.
3843 
 
3844 
   MODE is the mode of the operand pointed to by X.
3845 
 
3846 
   When -fpic is used, special handling is needed for symbolic references.
3847 
   See comments by legitimize_pic_address for details.  */
3848 
 
3849 
static rtx
3850 
s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3851 
                         enum machine_mode mode ATTRIBUTE_UNUSED)
3852 
{
3853 
  rtx constant_term = const0_rtx;
3854 
 
3855 
  if (TLS_SYMBOLIC_CONST (x))
3856 
    {
3857 
      x = legitimize_tls_address (x, 0);
3858 
 
3859 
      if (s390_legitimate_address_p (mode, x, FALSE))
3860 
        return x;
3861 
    }
3862 
  else if (GET_CODE (x) == PLUS
3863 
           && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3864 
               || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3865 
    {
3866 
      return x;
3867 
    }
3868 
  else if (flag_pic)
3869 
    {
3870 
      if (SYMBOLIC_CONST (x)
3871 
          || (GET_CODE (x) == PLUS
3872 
              && (SYMBOLIC_CONST (XEXP (x, 0))
3873 
                  || SYMBOLIC_CONST (XEXP (x, 1)))))
3874 
          x = legitimize_pic_address (x, 0);
3875 
 
3876 
      if (s390_legitimate_address_p (mode, x, FALSE))
3877 
        return x;
3878 
    }
3879 
 
3880 
  x = eliminate_constant_term (x, &constant_term);
3881 
 
3882 
  /* Optimize loading of large displacements by splitting them
3883 
     into the multiple of 4K and the rest; this allows the
3884 
     former to be CSE'd if possible.
3885 
 
3886 
     Don't do this if the displacement is added to a register
3887 
     pointing into the stack frame, as the offsets will
3888 
     change later anyway.  */
3889 
 
3890 
  if (GET_CODE (constant_term) == CONST_INT
3891 
      && !TARGET_LONG_DISPLACEMENT
3892 
      && !DISP_IN_RANGE (INTVAL (constant_term))
3893 
      && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3894 
    {
3895 
      HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3896 
      HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3897 
 
3898 
      rtx temp = gen_reg_rtx (Pmode);
3899 
      rtx val  = force_operand (GEN_INT (upper), temp);
3900 
      if (val != temp)
3901 
        emit_move_insn (temp, val);
3902 
 
3903 
      x = gen_rtx_PLUS (Pmode, x, temp);
3904 
      constant_term = GEN_INT (lower);
3905 
    }
3906 
 
3907 
  if (GET_CODE (x) == PLUS)
3908 
    {
3909 
      if (GET_CODE (XEXP (x, 0)) == REG)
3910 
        {
3911 
          rtx temp = gen_reg_rtx (Pmode);
3912 
          rtx val  = force_operand (XEXP (x, 1), temp);
3913 
          if (val != temp)
3914 
            emit_move_insn (temp, val);
3915 
 
3916 
          x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3917 
        }
3918 
 
3919 
      else if (GET_CODE (XEXP (x, 1)) == REG)
3920 
        {
3921 
          rtx temp = gen_reg_rtx (Pmode);
3922 
          rtx val  = force_operand (XEXP (x, 0), temp);
3923 
          if (val != temp)
3924 
            emit_move_insn (temp, val);
3925 
 
3926 
          x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3927 
        }
3928 
    }
3929 
 
3930 
  if (constant_term != const0_rtx)
3931 
    x = gen_rtx_PLUS (Pmode, x, constant_term);
3932 
 
3933 
  return x;
3934 
}
3935 
 
3936 
/* Try a machine-dependent way of reloading an illegitimate address AD
3937 
   operand.  If we find one, push the reload and return the new address.
3938 
 
3939 
   MODE is the mode of the enclosing MEM.  OPNUM is the operand number
3940 
   and TYPE is the reload type of the current reload.  */
3941 
 
3942 
rtx
3943 
legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3944 
                           int opnum, int type)
3945 
{
3946 
  if (!optimize || TARGET_LONG_DISPLACEMENT)
3947 
    return NULL_RTX;
3948 
 
3949 
  if (GET_CODE (ad) == PLUS)
3950 
    {
3951 
      rtx tem = simplify_binary_operation (PLUS, Pmode,
3952 
                                           XEXP (ad, 0), XEXP (ad, 1));
3953 
      if (tem)
3954 
        ad = tem;
3955 
    }
3956 
 
3957 
  if (GET_CODE (ad) == PLUS
3958 
      && GET_CODE (XEXP (ad, 0)) == REG
3959 
      && GET_CODE (XEXP (ad, 1)) == CONST_INT
3960 
      && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3961 
    {
3962 
      HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3963 
      HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3964 
      rtx cst, tem, new_rtx;
3965 
 
3966 
      cst = GEN_INT (upper);
3967 
      if (!legitimate_reload_constant_p (cst))
3968 
        cst = force_const_mem (Pmode, cst);
3969 
 
3970 
      tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3971 
      new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3972 
 
3973 
      push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3974 
                   BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3975 
                   opnum, (enum reload_type) type);
3976 
      return new_rtx;
3977 
    }
3978 
 
3979 
  return NULL_RTX;
3980 
}
3981 
 
3982 
/* Emit code to move LEN bytes from DST to SRC.  */
3983 
 
3984 
void
3985 
s390_expand_movmem (rtx dst, rtx src, rtx len)
3986 
{
3987 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3988 
    {
3989 
      if (INTVAL (len) > 0)
3990 
        emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3991 
    }
3992 
 
3993 
  else if (TARGET_MVCLE)
3994 
    {
3995 
      emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3996 
    }
3997 
 
3998 
  else
3999 
    {
4000 
      rtx dst_addr, src_addr, count, blocks, temp;
4001 
      rtx loop_start_label = gen_label_rtx ();
4002 
      rtx loop_end_label = gen_label_rtx ();
4003 
      rtx end_label = gen_label_rtx ();
4004 
      enum machine_mode mode;
4005 
 
4006 
      mode = GET_MODE (len);
4007 
      if (mode == VOIDmode)
4008 
        mode = Pmode;
4009 
 
4010 
      dst_addr = gen_reg_rtx (Pmode);
4011 
      src_addr = gen_reg_rtx (Pmode);
4012 
      count = gen_reg_rtx (mode);
4013 
      blocks = gen_reg_rtx (mode);
4014 
 
4015 
      convert_move (count, len, 1);
4016 
      emit_cmp_and_jump_insns (count, const0_rtx,
4017 
                               EQ, NULL_RTX, mode, 1, end_label);
4018 
 
4019 
      emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4020 
      emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4021 
      dst = change_address (dst, VOIDmode, dst_addr);
4022 
      src = change_address (src, VOIDmode, src_addr);
4023 
 
4024 
      temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4025 
                           OPTAB_DIRECT);
4026 
      if (temp != count)
4027 
        emit_move_insn (count, temp);
4028 
 
4029 
      temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4030 
                           OPTAB_DIRECT);
4031 
      if (temp != blocks)
4032 
        emit_move_insn (blocks, temp);
4033 
 
4034 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4035 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4036 
 
4037 
      emit_label (loop_start_label);
4038 
 
4039 
      if (TARGET_Z10
4040 
          && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4041 
        {
4042 
          rtx prefetch;
4043 
 
4044 
          /* Issue a read prefetch for the +3 cache line.  */
4045 
          prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4046 
                                   const0_rtx, const0_rtx);
4047 
          PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4048 
          emit_insn (prefetch);
4049 
 
4050 
          /* Issue a write prefetch for the +3 cache line.  */
4051 
          prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4052 
                                   const1_rtx, const0_rtx);
4053 
          PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4054 
          emit_insn (prefetch);
4055 
        }
4056 
 
4057 
      emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4058 
      s390_load_address (dst_addr,
4059 
                         gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4060 
      s390_load_address (src_addr,
4061 
                         gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4062 
 
4063 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4064 
                           OPTAB_DIRECT);
4065 
      if (temp != blocks)
4066 
        emit_move_insn (blocks, temp);
4067 
 
4068 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4069 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4070 
 
4071 
      emit_jump (loop_start_label);
4072 
      emit_label (loop_end_label);
4073 
 
4074 
      emit_insn (gen_movmem_short (dst, src,
4075 
                                   convert_to_mode (Pmode, count, 1)));
4076 
      emit_label (end_label);
4077 
    }
4078 
}
4079 
 
4080 
/* Emit code to set LEN bytes at DST to VAL.
4081 
   Make use of clrmem if VAL is zero.  */
4082 
 
4083 
void
4084 
s390_expand_setmem (rtx dst, rtx len, rtx val)
4085 
{
4086 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4087 
    return;
4088 
 
4089 
  gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4090 
 
4091 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4092 
    {
4093 
      if (val == const0_rtx && INTVAL (len) <= 256)
4094 
        emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4095 
      else
4096 
        {
4097 
          /* Initialize memory by storing the first byte.  */
4098 
          emit_move_insn (adjust_address (dst, QImode, 0), val);
4099 
 
4100 
          if (INTVAL (len) > 1)
4101 
            {
4102 
              /* Initiate 1 byte overlap move.
4103 
                 The first byte of DST is propagated through DSTP1.
4104 
                 Prepare a movmem for:  DST+1 = DST (length = LEN - 1).
4105 
                 DST is set to size 1 so the rest of the memory location
4106 
                 does not count as source operand.  */
4107 
              rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4108 
              set_mem_size (dst, 1);
4109 
 
4110 
              emit_insn (gen_movmem_short (dstp1, dst,
4111 
                                           GEN_INT (INTVAL (len) - 2)));
4112 
            }
4113 
        }
4114 
    }
4115 
 
4116 
  else if (TARGET_MVCLE)
4117 
    {
4118 
      val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4119 
      emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4120 
    }
4121 
 
4122 
  else
4123 
    {
4124 
      rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4125 
      rtx loop_start_label = gen_label_rtx ();
4126 
      rtx loop_end_label = gen_label_rtx ();
4127 
      rtx end_label = gen_label_rtx ();
4128 
      enum machine_mode mode;
4129 
 
4130 
      mode = GET_MODE (len);
4131 
      if (mode == VOIDmode)
4132 
        mode = Pmode;
4133 
 
4134 
      dst_addr = gen_reg_rtx (Pmode);
4135 
      count = gen_reg_rtx (mode);
4136 
      blocks = gen_reg_rtx (mode);
4137 
 
4138 
      convert_move (count, len, 1);
4139 
      emit_cmp_and_jump_insns (count, const0_rtx,
4140 
                               EQ, NULL_RTX, mode, 1, end_label);
4141 
 
4142 
      emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4143 
      dst = change_address (dst, VOIDmode, dst_addr);
4144 
 
4145 
      if (val == const0_rtx)
4146 
        temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4147 
                             OPTAB_DIRECT);
4148 
      else
4149 
        {
4150 
          dstp1 = adjust_address (dst, VOIDmode, 1);
4151 
          set_mem_size (dst, 1);
4152 
 
4153 
          /* Initialize memory by storing the first byte.  */
4154 
          emit_move_insn (adjust_address (dst, QImode, 0), val);
4155 
 
4156 
          /* If count is 1 we are done.  */
4157 
          emit_cmp_and_jump_insns (count, const1_rtx,
4158 
                                   EQ, NULL_RTX, mode, 1, end_label);
4159 
 
4160 
          temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4161 
                               OPTAB_DIRECT);
4162 
        }
4163 
      if (temp != count)
4164 
        emit_move_insn (count, temp);
4165 
 
4166 
      temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4167 
                           OPTAB_DIRECT);
4168 
      if (temp != blocks)
4169 
        emit_move_insn (blocks, temp);
4170 
 
4171 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4172 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4173 
 
4174 
      emit_label (loop_start_label);
4175 
 
4176 
      if (TARGET_Z10
4177 
          && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4178 
        {
4179 
          /* Issue a write prefetch for the +4 cache line.  */
4180 
          rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4181 
                                                     GEN_INT (1024)),
4182 
                                       const1_rtx, const0_rtx);
4183 
          emit_insn (prefetch);
4184 
          PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4185 
        }
4186 
 
4187 
      if (val == const0_rtx)
4188 
        emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4189 
      else
4190 
        emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4191 
      s390_load_address (dst_addr,
4192 
                         gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4193 
 
4194 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4195 
                           OPTAB_DIRECT);
4196 
      if (temp != blocks)
4197 
        emit_move_insn (blocks, temp);
4198 
 
4199 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4200 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4201 
 
4202 
      emit_jump (loop_start_label);
4203 
      emit_label (loop_end_label);
4204 
 
4205 
      if (val == const0_rtx)
4206 
        emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4207 
      else
4208 
        emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4209 
      emit_label (end_label);
4210 
    }
4211 
}
4212 
 
4213 
/* Emit code to compare LEN bytes at OP0 with those at OP1,
4214 
   and return the result in TARGET.  */
4215 
 
4216 
void
4217 
s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4218 
{
4219 
  rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4220 
  rtx tmp;
4221 
 
4222 
  /* As the result of CMPINT is inverted compared to what we need,
4223 
     we have to swap the operands.  */
4224 
  tmp = op0; op0 = op1; op1 = tmp;
4225 
 
4226 
  if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4227 
    {
4228 
      if (INTVAL (len) > 0)
4229 
        {
4230 
          emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4231 
          emit_insn (gen_cmpint (target, ccreg));
4232 
        }
4233 
      else
4234 
        emit_move_insn (target, const0_rtx);
4235 
    }
4236 
  else if (TARGET_MVCLE)
4237 
    {
4238 
      emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4239 
      emit_insn (gen_cmpint (target, ccreg));
4240 
    }
4241 
  else
4242 
    {
4243 
      rtx addr0, addr1, count, blocks, temp;
4244 
      rtx loop_start_label = gen_label_rtx ();
4245 
      rtx loop_end_label = gen_label_rtx ();
4246 
      rtx end_label = gen_label_rtx ();
4247 
      enum machine_mode mode;
4248 
 
4249 
      mode = GET_MODE (len);
4250 
      if (mode == VOIDmode)
4251 
        mode = Pmode;
4252 
 
4253 
      addr0 = gen_reg_rtx (Pmode);
4254 
      addr1 = gen_reg_rtx (Pmode);
4255 
      count = gen_reg_rtx (mode);
4256 
      blocks = gen_reg_rtx (mode);
4257 
 
4258 
      convert_move (count, len, 1);
4259 
      emit_cmp_and_jump_insns (count, const0_rtx,
4260 
                               EQ, NULL_RTX, mode, 1, end_label);
4261 
 
4262 
      emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4263 
      emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4264 
      op0 = change_address (op0, VOIDmode, addr0);
4265 
      op1 = change_address (op1, VOIDmode, addr1);
4266 
 
4267 
      temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4268 
                           OPTAB_DIRECT);
4269 
      if (temp != count)
4270 
        emit_move_insn (count, temp);
4271 
 
4272 
      temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4273 
                           OPTAB_DIRECT);
4274 
      if (temp != blocks)
4275 
        emit_move_insn (blocks, temp);
4276 
 
4277 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4278 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4279 
 
4280 
      emit_label (loop_start_label);
4281 
 
4282 
      if (TARGET_Z10
4283 
          && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4284 
        {
4285 
          rtx prefetch;
4286 
 
4287 
          /* Issue a read prefetch for the +2 cache line of operand 1.  */
4288 
          prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4289 
                                   const0_rtx, const0_rtx);
4290 
          emit_insn (prefetch);
4291 
          PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4292 
 
4293 
          /* Issue a read prefetch for the +2 cache line of operand 2.  */
4294 
          prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4295 
                                   const0_rtx, const0_rtx);
4296 
          emit_insn (prefetch);
4297 
          PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4298 
        }
4299 
 
4300 
      emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4301 
      temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4302 
      temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4303 
                        gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4304 
      temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4305 
      emit_jump_insn (temp);
4306 
 
4307 
      s390_load_address (addr0,
4308 
                         gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4309 
      s390_load_address (addr1,
4310 
                         gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4311 
 
4312 
      temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4313 
                           OPTAB_DIRECT);
4314 
      if (temp != blocks)
4315 
        emit_move_insn (blocks, temp);
4316 
 
4317 
      emit_cmp_and_jump_insns (blocks, const0_rtx,
4318 
                               EQ, NULL_RTX, mode, 1, loop_end_label);
4319 
 
4320 
      emit_jump (loop_start_label);
4321 
      emit_label (loop_end_label);
4322 
 
4323 
      emit_insn (gen_cmpmem_short (op0, op1,
4324 
                                   convert_to_mode (Pmode, count, 1)));
4325 
      emit_label (end_label);
4326 
 
4327 
      emit_insn (gen_cmpint (target, ccreg));
4328 
    }
4329 
}
4330 
 
4331 
 
4332 
/* Expand conditional increment or decrement using alc/slb instructions.
4333 
   Should generate code setting DST to either SRC or SRC + INCREMENT,
4334 
   depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4335 
   Returns true if successful, false otherwise.
4336 
 
4337 
   That makes it possible to implement some if-constructs without jumps e.g.:
4338 
   (borrow = CC0 | CC1 and carry = CC2 | CC3)
4339 
   unsigned int a, b, c;
4340 
   if (a < b)  c++; -> CCU  b > a  -> CC2;    c += carry;
4341 
   if (a < b)  c--; -> CCL3 a - b  -> borrow; c -= borrow;
4342 
   if (a <= b) c++; -> CCL3 b - a  -> borrow; c += carry;
4343 
   if (a <= b) c--; -> CCU  a <= b -> borrow; c -= borrow;
4344 
 
4345 
   Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4346 
   if (a == b) c++; -> CCL3 a ^= b; 0 - a  -> borrow;    c += carry;
4347 
   if (a == b) c--; -> CCU  a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4348 
   if (a != b) c++; -> CCU  a ^= b; a > 0  -> CC2;       c += carry;
4349 
   if (a != b) c--; -> CCL3 a ^= b; 0 - a  -> borrow;    c -= borrow; */
4350 
 
4351 
bool
4352 
s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4353 
                   rtx dst, rtx src, rtx increment)
4354 
{
4355 
  enum machine_mode cmp_mode;
4356 
  enum machine_mode cc_mode;
4357 
  rtx op_res;
4358 
  rtx insn;
4359 
  rtvec p;
4360 
  int ret;
4361 
 
4362 
  if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4363 
      && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4364 
    cmp_mode = SImode;
4365 
  else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4366 
           && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4367 
    cmp_mode = DImode;
4368 
  else
4369 
    return false;
4370 
 
4371 
  /* Try ADD LOGICAL WITH CARRY.  */
4372 
  if (increment == const1_rtx)
4373 
    {
4374 
      /* Determine CC mode to use.  */
4375 
      if (cmp_code == EQ || cmp_code == NE)
4376 
        {
4377 
          if (cmp_op1 != const0_rtx)
4378 
            {
4379 
              cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4380 
                                             NULL_RTX, 0, OPTAB_WIDEN);
4381 
              cmp_op1 = const0_rtx;
4382 
            }
4383 
 
4384 
          cmp_code = cmp_code == EQ ? LEU : GTU;
4385 
        }
4386 
 
4387 
      if (cmp_code == LTU || cmp_code == LEU)
4388 
        {
4389 
          rtx tem = cmp_op0;
4390 
          cmp_op0 = cmp_op1;
4391 
          cmp_op1 = tem;
4392 
          cmp_code = swap_condition (cmp_code);
4393 
        }
4394 
 
4395 
      switch (cmp_code)
4396 
        {
4397 
          case GTU:
4398 
            cc_mode = CCUmode;
4399 
            break;
4400 
 
4401 
          case GEU:
4402 
            cc_mode = CCL3mode;
4403 
            break;
4404 
 
4405 
          default:
4406 
            return false;
4407 
        }
4408 
 
4409 
      /* Emit comparison instruction pattern. */
4410 
      if (!register_operand (cmp_op0, cmp_mode))
4411 
        cmp_op0 = force_reg (cmp_mode, cmp_op0);
4412 
 
4413 
      insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4414 
                          gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4415 
      /* We use insn_invalid_p here to add clobbers if required.  */
4416 
      ret = insn_invalid_p (emit_insn (insn));
4417 
      gcc_assert (!ret);
4418 
 
4419 
      /* Emit ALC instruction pattern.  */
4420 
      op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4421 
                               gen_rtx_REG (cc_mode, CC_REGNUM),
4422 
                               const0_rtx);
4423 
 
4424 
      if (src != const0_rtx)
4425 
        {
4426 
          if (!register_operand (src, GET_MODE (dst)))
4427 
            src = force_reg (GET_MODE (dst), src);
4428 
 
4429 
          op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4430 
          op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4431 
        }
4432 
 
4433 
      p = rtvec_alloc (2);
4434 
      RTVEC_ELT (p, 0) =
4435 
        gen_rtx_SET (VOIDmode, dst, op_res);
4436 
      RTVEC_ELT (p, 1) =
4437 
        gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4438 
      emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4439 
 
4440 
      return true;
4441 
    }
4442 
 
4443 
  /* Try SUBTRACT LOGICAL WITH BORROW.  */
4444 
  if (increment == constm1_rtx)
4445 
    {
4446 
      /* Determine CC mode to use.  */
4447 
      if (cmp_code == EQ || cmp_code == NE)
4448 
        {
4449 
          if (cmp_op1 != const0_rtx)
4450 
            {
4451 
              cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4452 
                                             NULL_RTX, 0, OPTAB_WIDEN);
4453 
              cmp_op1 = const0_rtx;
4454 
            }
4455 
 
4456 
          cmp_code = cmp_code == EQ ? LEU : GTU;
4457 
        }
4458 
 
4459 
      if (cmp_code == GTU || cmp_code == GEU)
4460 
        {
4461 
          rtx tem = cmp_op0;
4462 
          cmp_op0 = cmp_op1;
4463 
          cmp_op1 = tem;
4464 
          cmp_code = swap_condition (cmp_code);
4465 
        }
4466 
 
4467 
      switch (cmp_code)
4468 
        {
4469 
          case LEU:
4470 
            cc_mode = CCUmode;
4471 
            break;
4472 
 
4473 
          case LTU:
4474 
            cc_mode = CCL3mode;
4475 
            break;
4476 
 
4477 
          default:
4478 
            return false;
4479 
        }
4480 
 
4481 
      /* Emit comparison instruction pattern. */
4482 
      if (!register_operand (cmp_op0, cmp_mode))
4483 
        cmp_op0 = force_reg (cmp_mode, cmp_op0);
4484 
 
4485 
      insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4486 
                          gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4487 
      /* We use insn_invalid_p here to add clobbers if required.  */
4488 
      ret = insn_invalid_p (emit_insn (insn));
4489 
      gcc_assert (!ret);
4490 
 
4491 
      /* Emit SLB instruction pattern.  */
4492 
      if (!register_operand (src, GET_MODE (dst)))
4493 
        src = force_reg (GET_MODE (dst), src);
4494 
 
4495 
      op_res = gen_rtx_MINUS (GET_MODE (dst),
4496 
                              gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4497 
                              gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4498 
                                              gen_rtx_REG (cc_mode, CC_REGNUM),
4499 
                                              const0_rtx));
4500 
      p = rtvec_alloc (2);
4501 
      RTVEC_ELT (p, 0) =
4502 
        gen_rtx_SET (VOIDmode, dst, op_res);
4503 
      RTVEC_ELT (p, 1) =
4504 
        gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4505 
      emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4506 
 
4507 
      return true;
4508 
    }
4509 
 
4510 
  return false;
4511 
}
4512 
 
4513 
/* Expand code for the insv template. Return true if successful.  */
4514 
 
4515 
bool
4516 
s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4517 
{
4518 
  int bitsize = INTVAL (op1);
4519 
  int bitpos = INTVAL (op2);
4520 
 
4521 
  /* On z10 we can use the risbg instruction to implement insv.  */
4522 
  if (TARGET_Z10
4523 
      && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4524 
          || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4525 
    {
4526 
      rtx op;
4527 
      rtx clobber;
4528 
 
4529 
      op = gen_rtx_SET (GET_MODE(src),
4530 
                        gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4531 
                        src);
4532 
      clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4533 
      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4534 
 
4535 
      return true;
4536 
    }
4537 
 
4538 
  /* We need byte alignment.  */
4539 
  if (bitsize % BITS_PER_UNIT)
4540 
    return false;
4541 
 
4542 
  if (bitpos == 0
4543 
      && memory_operand (dest, VOIDmode)
4544 
      && (register_operand (src, word_mode)
4545 
          || const_int_operand (src, VOIDmode)))
4546 
    {
4547 
      /* Emit standard pattern if possible.  */
4548 
      enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4549 
      if (GET_MODE_BITSIZE (mode) == bitsize)
4550 
        emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4551 
 
4552 
      /* (set (ze (mem)) (const_int)).  */
4553 
      else if (const_int_operand (src, VOIDmode))
4554 
        {
4555 
          int size = bitsize / BITS_PER_UNIT;
4556 
          rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4557 
                                        GET_MODE_SIZE (word_mode) - size);
4558 
 
4559 
          dest = adjust_address (dest, BLKmode, 0);
4560 
          set_mem_size (dest, size);
4561 
          s390_expand_movmem (dest, src_mem, GEN_INT (size));
4562 
        }
4563 
 
4564 
      /* (set (ze (mem)) (reg)).  */
4565 
      else if (register_operand (src, word_mode))
4566 
        {
4567 
          if (bitsize <= GET_MODE_BITSIZE (SImode))
4568 
            emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4569 
                                                  const0_rtx), src);
4570 
          else
4571 
            {
4572 
              /* Emit st,stcmh sequence.  */
4573 
              int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4574 
              int size = stcmh_width / BITS_PER_UNIT;
4575 
 
4576 
              emit_move_insn (adjust_address (dest, SImode, size),
4577 
                              gen_lowpart (SImode, src));
4578 
              set_mem_size (dest, size);
4579 
              emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4580 
                                                    (stcmh_width), const0_rtx),
4581 
                              gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4582 
                                                (GET_MODE_BITSIZE (SImode))));
4583 
            }
4584 
        }
4585 
      else
4586 
        return false;
4587 
 
4588 
      return true;
4589 
    }
4590 
 
4591 
  /* (set (ze (reg)) (const_int)).  */
4592 
  if (TARGET_ZARCH
4593 
      && register_operand (dest, word_mode)
4594 
      && (bitpos % 16) == 0
4595 
      && (bitsize % 16) == 0
4596 
      && const_int_operand (src, VOIDmode))
4597 
    {
4598 
      HOST_WIDE_INT val = INTVAL (src);
4599 
      int regpos = bitpos + bitsize;
4600 
 
4601 
      while (regpos > bitpos)
4602 
        {
4603 
          enum machine_mode putmode;
4604 
          int putsize;
4605 
 
4606 
          if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4607 
            putmode = SImode;
4608 
          else
4609 
            putmode = HImode;
4610 
 
4611 
          putsize = GET_MODE_BITSIZE (putmode);
4612 
          regpos -= putsize;
4613 
          emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4614 
                                                GEN_INT (putsize),
4615 
                                                GEN_INT (regpos)),
4616 
                          gen_int_mode (val, putmode));
4617 
          val >>= putsize;
4618 
        }
4619 
      gcc_assert (regpos == bitpos);
4620 
      return true;
4621 
    }
4622 
 
4623 
  return false;
4624 
}
4625 
 
4626 
/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4627 
   register that holds VAL of mode MODE shifted by COUNT bits.  */
4628 
 
4629 
static inline rtx
4630 
s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4631 
{
4632 
  val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4633 
                             NULL_RTX, 1, OPTAB_DIRECT);
4634 
  return expand_simple_binop (SImode, ASHIFT, val, count,
4635 
                              NULL_RTX, 1, OPTAB_DIRECT);
4636 
}
4637 
 
4638 
/* Structure to hold the initial parameters for a compare_and_swap operation
4639 
   in HImode and QImode.  */
4640 
 
4641 
struct alignment_context
4642 
{
4643 
  rtx memsi;      /* SI aligned memory location.  */
4644 
  rtx shift;      /* Bit offset with regard to lsb.  */
4645 
  rtx modemask;   /* Mask of the HQImode shifted by SHIFT bits.  */
4646 
  rtx modemaski;  /* ~modemask */
4647 
  bool aligned;   /* True if memory is aligned, false else.  */
4648 
};
4649 
 
4650 
/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4651 
   structure AC for transparent simplifying, if the memory alignment is known
4652 
   to be at least 32bit.  MEM is the memory location for the actual operation
4653 
   and MODE its mode.  */
4654 
 
4655 
static void
4656 
init_alignment_context (struct alignment_context *ac, rtx mem,
4657 
                        enum machine_mode mode)
4658 
{
4659 
  ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4660 
  ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4661 
 
4662 
  if (ac->aligned)
4663 
    ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned.  */
4664 
  else
4665 
    {
4666 
      /* Alignment is unknown.  */
4667 
      rtx byteoffset, addr, align;
4668 
 
4669 
      /* Force the address into a register.  */
4670 
      addr = force_reg (Pmode, XEXP (mem, 0));
4671 
 
4672 
      /* Align it to SImode.  */
4673 
      align = expand_simple_binop (Pmode, AND, addr,
4674 
                                   GEN_INT (-GET_MODE_SIZE (SImode)),
4675 
                                   NULL_RTX, 1, OPTAB_DIRECT);
4676 
      /* Generate MEM.  */
4677 
      ac->memsi = gen_rtx_MEM (SImode, align);
4678 
      MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4679 
      set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4680 
      set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4681 
 
4682 
      /* Calculate shiftcount.  */
4683 
      byteoffset = expand_simple_binop (Pmode, AND, addr,
4684 
                                        GEN_INT (GET_MODE_SIZE (SImode) - 1),
4685 
                                        NULL_RTX, 1, OPTAB_DIRECT);
4686 
      /* As we already have some offset, evaluate the remaining distance.  */
4687 
      ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4688 
                                      NULL_RTX, 1, OPTAB_DIRECT);
4689 
 
4690 
    }
4691 
  /* Shift is the byte count, but we need the bitcount.  */
4692 
  ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4693 
                                  NULL_RTX, 1, OPTAB_DIRECT);
4694 
  /* Calculate masks.  */
4695 
  ac->modemask = expand_simple_binop (SImode, ASHIFT,
4696 
                                     GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4697 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4698 
  ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4699 
}
4700 
 
4701 
/* Expand an atomic compare and swap operation for HImode and QImode.  MEM is
4702 
   the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4703 
   to set if CMP == MEM.
4704 
   CMP is never in memory for compare_and_swap_cc because
4705 
   expand_bool_compare_and_swap puts it into a register for later compare.  */
4706 
 
4707 
void
4708 
s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4709 
{
4710 
  struct alignment_context ac;
4711 
  rtx cmpv, newv, val, resv, cc;
4712 
  rtx res = gen_reg_rtx (SImode);
4713 
  rtx csloop = gen_label_rtx ();
4714 
  rtx csend = gen_label_rtx ();
4715 
 
4716 
  gcc_assert (register_operand (target, VOIDmode));
4717 
  gcc_assert (MEM_P (mem));
4718 
 
4719 
  init_alignment_context (&ac, mem, mode);
4720 
 
4721 
  /* Shift the values to the correct bit positions.  */
4722 
  if (!(ac.aligned && MEM_P (cmp)))
4723 
    cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4724 
  if (!(ac.aligned && MEM_P (new_rtx)))
4725 
    new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4726 
 
4727 
  /* Load full word.  Subsequent loads are performed by CS.  */
4728 
  val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4729 
                             NULL_RTX, 1, OPTAB_DIRECT);
4730 
 
4731 
  /* Start CS loop.  */
4732 
  emit_label (csloop);
4733 
  /* val = "<mem>00..0<mem>"
4734 
   * cmp = "00..0<cmp>00..0"
4735 
   * new = "00..0<new>00..0"
4736 
   */
4737 
 
4738 
  /* Patch cmp and new with val at correct position.  */
4739 
  if (ac.aligned && MEM_P (cmp))
4740 
    {
4741 
      cmpv = force_reg (SImode, val);
4742 
      store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0,
4743 
                       0, 0, SImode, cmp);
4744 
    }
4745 
  else
4746 
    cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4747 
                                                   NULL_RTX, 1, OPTAB_DIRECT));
4748 
  if (ac.aligned && MEM_P (new_rtx))
4749 
    {
4750 
      newv = force_reg (SImode, val);
4751 
      store_bit_field (newv, GET_MODE_BITSIZE (mode), 0,
4752 
                       0, 0, SImode, new_rtx);
4753 
    }
4754 
  else
4755 
    newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4756 
                                                   NULL_RTX, 1, OPTAB_DIRECT));
4757 
 
4758 
  /* Jump to end if we're done (likely?).  */
4759 
  s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4760 
                                                     cmpv, newv));
4761 
 
4762 
  /* Check for changes outside mode.  */
4763 
  resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4764 
                              NULL_RTX, 1, OPTAB_DIRECT);
4765 
  cc = s390_emit_compare (NE, resv, val);
4766 
  emit_move_insn (val, resv);
4767 
  /* Loop internal if so.  */
4768 
  s390_emit_jump (csloop, cc);
4769 
 
4770 
  emit_label (csend);
4771 
 
4772 
  /* Return the correct part of the bitfield.  */
4773 
  convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4774 
                                             NULL_RTX, 1, OPTAB_DIRECT), 1);
4775 
}
4776 
 
4777 
/* Expand an atomic operation CODE of mode MODE.  MEM is the memory location
4778 
   and VAL the value to play with.  If AFTER is true then store the value
4779 
   MEM holds after the operation, if AFTER is false then store the value MEM
4780 
   holds before the operation.  If TARGET is zero then discard that value, else
4781 
   store it to TARGET.  */
4782 
 
4783 
void
4784 
s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4785 
                    rtx target, rtx mem, rtx val, bool after)
4786 
{
4787 
  struct alignment_context ac;
4788 
  rtx cmp;
4789 
  rtx new_rtx = gen_reg_rtx (SImode);
4790 
  rtx orig = gen_reg_rtx (SImode);
4791 
  rtx csloop = gen_label_rtx ();
4792 
 
4793 
  gcc_assert (!target || register_operand (target, VOIDmode));
4794 
  gcc_assert (MEM_P (mem));
4795 
 
4796 
  init_alignment_context (&ac, mem, mode);
4797 
 
4798 
  /* Shift val to the correct bit positions.
4799 
     Preserve "icm", but prevent "ex icm".  */
4800 
  if (!(ac.aligned && code == SET && MEM_P (val)))
4801 
    val = s390_expand_mask_and_shift (val, mode, ac.shift);
4802 
 
4803 
  /* Further preparation insns.  */
4804 
  if (code == PLUS || code == MINUS)
4805 
    emit_move_insn (orig, val);
4806 
  else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4807 
    val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4808 
                               NULL_RTX, 1, OPTAB_DIRECT);
4809 
 
4810 
  /* Load full word.  Subsequent loads are performed by CS.  */
4811 
  cmp = force_reg (SImode, ac.memsi);
4812 
 
4813 
  /* Start CS loop.  */
4814 
  emit_label (csloop);
4815 
  emit_move_insn (new_rtx, cmp);
4816 
 
4817 
  /* Patch new with val at correct position.  */
4818 
  switch (code)
4819 
    {
4820 
    case PLUS:
4821 
    case MINUS:
4822 
      val = expand_simple_binop (SImode, code, new_rtx, orig,
4823 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4824 
      val = expand_simple_binop (SImode, AND, val, ac.modemask,
4825 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4826 
      /* FALLTHRU */
4827 
    case SET:
4828 
      if (ac.aligned && MEM_P (val))
4829 
        store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
4830 
                         0, 0, SImode, val);
4831 
      else
4832 
        {
4833 
          new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4834 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4835 
          new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4836 
                                     NULL_RTX, 1, OPTAB_DIRECT);
4837 
        }
4838 
      break;
4839 
    case AND:
4840 
    case IOR:
4841 
    case XOR:
4842 
      new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4843 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4844 
      break;
4845 
    case MULT: /* NAND */
4846 
      new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4847 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4848 
      new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4849 
                                 NULL_RTX, 1, OPTAB_DIRECT);
4850 
      break;
4851 
    default:
4852 
      gcc_unreachable ();
4853 
    }
4854 
 
4855 
  s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4856 
                                                      ac.memsi, cmp, new_rtx));
4857 
 
4858 
  /* Return the correct part of the bitfield.  */
4859 
  if (target)
4860 
    convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4861 
                                               after ? new_rtx : cmp, ac.shift,
4862 
                                               NULL_RTX, 1, OPTAB_DIRECT), 1);
4863 
}
4864 
 
4865 
/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4866 
   We need to emit DTP-relative relocations.  */
4867 
 
4868 
static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4869 
 
4870 
static void
4871 
s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4872 
{
4873 
  switch (size)
4874 
    {
4875 
    case 4:
4876 
      fputs ("\t.long\t", file);
4877 
      break;
4878 
    case 8:
4879 
      fputs ("\t.quad\t", file);
4880 
      break;
4881 
    default:
4882 
      gcc_unreachable ();
4883 
    }
4884 
  output_addr_const (file, x);
4885 
  fputs ("@DTPOFF", file);
4886 
}
4887 
 
4888 
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4889 
/* Implement TARGET_MANGLE_TYPE.  */
4890 
 
4891 
static const char *
4892 
s390_mangle_type (const_tree type)
4893 
{
4894 
  if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4895 
      && TARGET_LONG_DOUBLE_128)
4896 
    return "g";
4897 
 
4898 
  /* For all other types, use normal C++ mangling.  */
4899 
  return NULL;
4900 
}
4901 
#endif
4902 
 
4903 
/* In the name of slightly smaller debug output, and to cater to
4904 
   general assembler lossage, recognize various UNSPEC sequences
4905 
   and turn them back into a direct symbol reference.  */
4906 
 
4907 
static rtx
4908 
s390_delegitimize_address (rtx orig_x)
4909 
{
4910 
  rtx x, y;
4911 
 
4912 
  orig_x = delegitimize_mem_from_attrs (orig_x);
4913 
  x = orig_x;
4914 
 
4915 
  /* Extract the symbol ref from:
4916 
     (plus:SI (reg:SI 12 %r12)
4917 
              (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4918 
                                    UNSPEC_GOTOFF/PLTOFF)))
4919 
     and
4920 
     (plus:SI (reg:SI 12 %r12)
4921 
              (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4922 
                                             UNSPEC_GOTOFF/PLTOFF)
4923 
                                 (const_int 4 [0x4]))))  */
4924 
  if (GET_CODE (x) == PLUS
4925 
      && REG_P (XEXP (x, 0))
4926 
      && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
4927 
      && GET_CODE (XEXP (x, 1)) == CONST)
4928 
    {
4929 
      HOST_WIDE_INT offset = 0;
4930 
 
4931 
      /* The const operand.  */
4932 
      y = XEXP (XEXP (x, 1), 0);
4933 
 
4934 
      if (GET_CODE (y) == PLUS
4935 
          && GET_CODE (XEXP (y, 1)) == CONST_INT)
4936 
        {
4937 
          offset = INTVAL (XEXP (y, 1));
4938 
          y = XEXP (y, 0);
4939 
        }
4940 
 
4941 
      if (GET_CODE (y) == UNSPEC
4942 
          && (XINT (y, 1) == UNSPEC_GOTOFF
4943 
              || XINT (y, 1) == UNSPEC_PLTOFF))
4944 
        return plus_constant (XVECEXP (y, 0, 0), offset);
4945 
    }
4946 
 
4947 
  if (GET_CODE (x) != MEM)
4948 
    return orig_x;
4949 
 
4950 
  x = XEXP (x, 0);
4951 
  if (GET_CODE (x) == PLUS
4952 
      && GET_CODE (XEXP (x, 1)) == CONST
4953 
      && GET_CODE (XEXP (x, 0)) == REG
4954 
      && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4955 
    {
4956 
      y = XEXP (XEXP (x, 1), 0);
4957 
      if (GET_CODE (y) == UNSPEC
4958 
          && XINT (y, 1) == UNSPEC_GOT)
4959 
        y = XVECEXP (y, 0, 0);
4960 
      else
4961 
        return orig_x;
4962 
    }
4963 
  else if (GET_CODE (x) == CONST)
4964 
    {
4965 
      /* Extract the symbol ref from:
4966 
         (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4967 
                                       UNSPEC_PLT/GOTENT)))  */
4968 
 
4969 
      y = XEXP (x, 0);
4970 
      if (GET_CODE (y) == UNSPEC
4971 
          && (XINT (y, 1) == UNSPEC_GOTENT
4972 
              || XINT (y, 1) == UNSPEC_PLT))
4973 
        y = XVECEXP (y, 0, 0);
4974 
      else
4975 
        return orig_x;
4976 
    }
4977 
  else
4978 
    return orig_x;
4979 
 
4980 
  if (GET_MODE (orig_x) != Pmode)
4981 
    {
4982 
      if (GET_MODE (orig_x) == BLKmode)
4983 
        return orig_x;
4984 
      y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
4985 
      if (y == NULL_RTX)
4986 
        return orig_x;
4987 
    }
4988 
  return y;
4989 
}
4990 
 
4991 
/* Output operand OP to stdio stream FILE.
4992 
   OP is an address (register + offset) which is not used to address data;
4993 
   instead the rightmost bits are interpreted as the value.  */
4994 
 
4995 
static void
4996 
print_shift_count_operand (FILE *file, rtx op)
4997 
{
4998 
  HOST_WIDE_INT offset;
4999 
  rtx base;
5000 
 
5001 
  /* Extract base register and offset.  */
5002 
  if (!s390_decompose_shift_count (op, &base, &offset))
5003 
    gcc_unreachable ();
5004 
 
5005 
  /* Sanity check.  */
5006 
  if (base)
5007 
    {
5008 
      gcc_assert (GET_CODE (base) == REG);
5009 
      gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5010 
      gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5011 
    }
5012 
 
5013 
  /* Offsets are constricted to twelve bits.  */
5014 
  fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5015 
  if (base)
5016 
    fprintf (file, "(%s)", reg_names[REGNO (base)]);
5017 
}
5018 
 
5019 
/* See 'get_some_local_dynamic_name'.  */
5020 
 
5021 
static int
5022 
get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5023 
{
5024 
  rtx x = *px;
5025 
 
5026 
  if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5027 
    {
5028 
      x = get_pool_constant (x);
5029 
      return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5030 
    }
5031 
 
5032 
  if (GET_CODE (x) == SYMBOL_REF
5033 
      && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5034 
    {
5035 
      cfun->machine->some_ld_name = XSTR (x, 0);
5036 
      return 1;
5037 
    }
5038 
 
5039 
  return 0;
5040 
}
5041 
 
5042 
/* Locate some local-dynamic symbol still in use by this function
5043 
   so that we can print its name in local-dynamic base patterns.  */
5044 
 
5045 
static const char *
5046 
get_some_local_dynamic_name (void)
5047 
{
5048 
  rtx insn;
5049 
 
5050 
  if (cfun->machine->some_ld_name)
5051 
    return cfun->machine->some_ld_name;
5052 
 
5053 
  for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5054 
    if (INSN_P (insn)
5055 
        && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5056 
      return cfun->machine->some_ld_name;
5057 
 
5058 
  gcc_unreachable ();
5059 
}
5060 
 
5061 
/* Output machine-dependent UNSPECs occurring in address constant X
5062 
   in assembler syntax to stdio stream FILE.  Returns true if the
5063 
   constant X could be recognized, false otherwise.  */
5064 
 
5065 
static bool
5066 
s390_output_addr_const_extra (FILE *file, rtx x)
5067 
{
5068 
  if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5069 
    switch (XINT (x, 1))
5070 
      {
5071 
      case UNSPEC_GOTENT:
5072 
        output_addr_const (file, XVECEXP (x, 0, 0));
5073 
        fprintf (file, "@GOTENT");
5074 
        return true;
5075 
      case UNSPEC_GOT:
5076 
        output_addr_const (file, XVECEXP (x, 0, 0));
5077 
        fprintf (file, "@GOT");
5078 
        return true;
5079 
      case UNSPEC_GOTOFF:
5080 
        output_addr_const (file, XVECEXP (x, 0, 0));
5081 
        fprintf (file, "@GOTOFF");
5082 
        return true;
5083 
      case UNSPEC_PLT:
5084 
        output_addr_const (file, XVECEXP (x, 0, 0));
5085 
        fprintf (file, "@PLT");
5086 
        return true;
5087 
      case UNSPEC_PLTOFF:
5088 
        output_addr_const (file, XVECEXP (x, 0, 0));
5089 
        fprintf (file, "@PLTOFF");
5090 
        return true;
5091 
      case UNSPEC_TLSGD:
5092 
        output_addr_const (file, XVECEXP (x, 0, 0));
5093 
        fprintf (file, "@TLSGD");
5094 
        return true;
5095 
      case UNSPEC_TLSLDM:
5096 
        assemble_name (file, get_some_local_dynamic_name ());
5097 
        fprintf (file, "@TLSLDM");
5098 
        return true;
5099 
      case UNSPEC_DTPOFF:
5100 
        output_addr_const (file, XVECEXP (x, 0, 0));
5101 
        fprintf (file, "@DTPOFF");
5102 
        return true;
5103 
      case UNSPEC_NTPOFF:
5104 
        output_addr_const (file, XVECEXP (x, 0, 0));
5105 
        fprintf (file, "@NTPOFF");
5106 
        return true;
5107 
      case UNSPEC_GOTNTPOFF:
5108 
        output_addr_const (file, XVECEXP (x, 0, 0));
5109 
        fprintf (file, "@GOTNTPOFF");
5110 
        return true;
5111 
      case UNSPEC_INDNTPOFF:
5112 
        output_addr_const (file, XVECEXP (x, 0, 0));
5113 
        fprintf (file, "@INDNTPOFF");
5114 
        return true;
5115 
      }
5116 
 
5117 
  if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5118 
    switch (XINT (x, 1))
5119 
      {
5120 
      case UNSPEC_POOL_OFFSET:
5121 
        x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5122 
        output_addr_const (file, x);
5123 
        return true;
5124 
      }
5125 
  return false;
5126 
}
5127 
 
5128 
/* Output address operand ADDR in assembler syntax to
5129 
   stdio stream FILE.  */
5130 
 
5131 
void
5132 
print_operand_address (FILE *file, rtx addr)
5133 
{
5134 
  struct s390_address ad;
5135 
 
5136 
  if (s390_symref_operand_p (addr, NULL, NULL))
5137 
    {
5138 
      if (!TARGET_Z10)
5139 
        {
5140 
          output_operand_lossage ("symbolic memory references are "
5141 
                                  "only supported on z10 or later");
5142 
          return;
5143 
        }
5144 
      output_addr_const (file, addr);
5145 
      return;
5146 
    }
5147 
 
5148 
  if (!s390_decompose_address (addr, &ad)
5149 
      || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5150 
      || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5151 
    output_operand_lossage ("cannot decompose address");
5152 
 
5153 
  if (ad.disp)
5154 
    output_addr_const (file, ad.disp);
5155 
  else
5156 
    fprintf (file, "0");
5157 
 
5158 
  if (ad.base && ad.indx)
5159 
    fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5160 
                              reg_names[REGNO (ad.base)]);
5161 
  else if (ad.base)
5162 
    fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5163 
}
5164 
 
5165 
/* Output operand X in assembler syntax to stdio stream FILE.
5166 
   CODE specified the format flag.  The following format flags
5167 
   are recognized:
5168 
 
5169 
    'C': print opcode suffix for branch condition.
5170 
    'D': print opcode suffix for inverse branch condition.
5171 
    'E': print opcode suffix for branch on index instruction.
5172 
    'J': print tls_load/tls_gdcall/tls_ldcall suffix
5173 
    'G': print the size of the operand in bytes.
5174 
    'O': print only the displacement of a memory reference.
5175 
    'R': print only the base register of a memory reference.
5176 
    'S': print S-type memory reference (base+displacement).
5177 
    'N': print the second word of a DImode operand.
5178 
    'M': print the second word of a TImode operand.
5179 
    'Y': print shift count operand.
5180 
 
5181 
    'b': print integer X as if it's an unsigned byte.
5182 
    'c': print integer X as if it's an signed byte.
5183 
    'x': print integer X as if it's an unsigned halfword.
5184 
    'h': print integer X as if it's a signed halfword.
5185 
    'i': print the first nonzero HImode part of X.
5186 
    'j': print the first HImode part unequal to -1 of X.
5187 
    'k': print the first nonzero SImode part of X.
5188 
    'm': print the first SImode part unequal to -1 of X.
5189 
    'o': print integer X as if it's an unsigned 32bit word.  */
5190 
 
5191 
void
5192 
print_operand (FILE *file, rtx x, int code)
5193 
{
5194 
  switch (code)
5195 
    {
5196 
    case 'C':
5197 
      fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5198 
      return;
5199 
 
5200 
    case 'D':
5201 
      fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5202 
      return;
5203 
 
5204 
    case 'E':
5205 
      if (GET_CODE (x) == LE)
5206 
        fprintf (file, "l");
5207 
      else if (GET_CODE (x) == GT)
5208 
        fprintf (file, "h");
5209 
      else
5210 
        output_operand_lossage ("invalid comparison operator "
5211 
                                "for 'E' output modifier");
5212 
      return;
5213 
 
5214 
    case 'J':
5215 
      if (GET_CODE (x) == SYMBOL_REF)
5216 
        {
5217 
          fprintf (file, "%s", ":tls_load:");
5218 
          output_addr_const (file, x);
5219 
        }
5220 
      else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5221 
        {
5222 
          fprintf (file, "%s", ":tls_gdcall:");
5223 
          output_addr_const (file, XVECEXP (x, 0, 0));
5224 
        }
5225 
      else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5226 
        {
5227 
          fprintf (file, "%s", ":tls_ldcall:");
5228 
          assemble_name (file, get_some_local_dynamic_name ());
5229 
        }
5230 
      else
5231 
        output_operand_lossage ("invalid reference for 'J' output modifier");
5232 
      return;
5233 
 
5234 
    case 'G':
5235 
      fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5236 
      return;
5237 
 
5238 
    case 'O':
5239 
      {
5240 
        struct s390_address ad;
5241 
        int ret;
5242 
 
5243 
        if (!MEM_P (x))
5244 
          {
5245 
            output_operand_lossage ("memory reference expected for "
5246 
                                    "'O' output modifier");
5247 
            return;
5248 
          }
5249 
 
5250 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
5251 
 
5252 
        if (!ret
5253 
            || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5254 
            || ad.indx)
5255 
          {
5256 
            output_operand_lossage ("invalid address for 'O' output modifier");
5257 
            return;
5258 
          }
5259 
 
5260 
        if (ad.disp)
5261 
          output_addr_const (file, ad.disp);
5262 
        else
5263 
          fprintf (file, "0");
5264 
      }
5265 
      return;
5266 
 
5267 
    case 'R':
5268 
      {
5269 
        struct s390_address ad;
5270 
        int ret;
5271 
 
5272 
        if (!MEM_P (x))
5273 
          {
5274 
            output_operand_lossage ("memory reference expected for "
5275 
                                    "'R' output modifier");
5276 
            return;
5277 
          }
5278 
 
5279 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
5280 
 
5281 
        if (!ret
5282 
            || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5283 
            || ad.indx)
5284 
          {
5285 
            output_operand_lossage ("invalid address for 'R' output modifier");
5286 
            return;
5287 
          }
5288 
 
5289 
        if (ad.base)
5290 
          fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5291 
        else
5292 
          fprintf (file, "0");
5293 
      }
5294 
      return;
5295 
 
5296 
    case 'S':
5297 
      {
5298 
        struct s390_address ad;
5299 
        int ret;
5300 
 
5301 
        if (!MEM_P (x))
5302 
          {
5303 
            output_operand_lossage ("memory reference expected for "
5304 
                                    "'S' output modifier");
5305 
            return;
5306 
          }
5307 
        ret = s390_decompose_address (XEXP (x, 0), &ad);
5308 
 
5309 
        if (!ret
5310 
            || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5311 
            || ad.indx)
5312 
          {
5313 
            output_operand_lossage ("invalid address for 'S' output modifier");
5314 
            return;
5315 
          }
5316 
 
5317 
        if (ad.disp)
5318 
          output_addr_const (file, ad.disp);
5319 
        else
5320 
          fprintf (file, "0");
5321 
 
5322 
        if (ad.base)
5323 
          fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5324 
      }
5325 
      return;
5326 
 
5327 
    case 'N':
5328 
      if (GET_CODE (x) == REG)
5329 
        x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5330 
      else if (GET_CODE (x) == MEM)
5331 
        x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5332 
      else
5333 
        output_operand_lossage ("register or memory expression expected "
5334 
                                "for 'N' output modifier");
5335 
      break;
5336 
 
5337 
    case 'M':
5338 
      if (GET_CODE (x) == REG)
5339 
        x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5340 
      else if (GET_CODE (x) == MEM)
5341 
        x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5342 
      else
5343 
        output_operand_lossage ("register or memory expression expected "
5344 
                                "for 'M' output modifier");
5345 
      break;
5346 
 
5347 
    case 'Y':
5348 
      print_shift_count_operand (file, x);
5349 
      return;
5350 
    }
5351 
 
5352 
  switch (GET_CODE (x))
5353 
    {
5354 
    case REG:
5355 
      fprintf (file, "%s", reg_names[REGNO (x)]);
5356 
      break;
5357 
 
5358 
    case MEM:
5359 
      output_address (XEXP (x, 0));
5360 
      break;
5361 
 
5362 
    case CONST:
5363 
    case CODE_LABEL:
5364 
    case LABEL_REF:
5365 
    case SYMBOL_REF:
5366 
      output_addr_const (file, x);
5367 
      break;
5368 
 
5369 
    case CONST_INT:
5370 
      if (code == 'b')
5371 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5372 
      else if (code == 'c')
5373 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5374 
      else if (code == 'x')
5375 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5376 
      else if (code == 'h')
5377 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5378 
      else if (code == 'i')
5379 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5380 
                 s390_extract_part (x, HImode, 0));
5381 
      else if (code == 'j')
5382 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5383 
                 s390_extract_part (x, HImode, -1));
5384 
      else if (code == 'k')
5385 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5386 
                 s390_extract_part (x, SImode, 0));
5387 
      else if (code == 'm')
5388 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5389 
                 s390_extract_part (x, SImode, -1));
5390 
      else if (code == 'o')
5391 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5392 
      else
5393 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5394 
      break;
5395 
 
5396 
    case CONST_DOUBLE:
5397 
      gcc_assert (GET_MODE (x) == VOIDmode);
5398 
      if (code == 'b')
5399 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5400 
      else if (code == 'x')
5401 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5402 
      else if (code == 'h')
5403 
        fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5404 
                 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5405 
      else
5406 
        {
5407 
          if (code == 0)
5408 
            output_operand_lossage ("invalid constant - try using "
5409 
                                    "an output modifier");
5410 
          else
5411 
            output_operand_lossage ("invalid constant for output modifier '%c'",
5412 
                                    code);
5413 
        }
5414 
      break;
5415 
 
5416 
    default:
5417 
      if (code == 0)
5418 
        output_operand_lossage ("invalid expression - try using "
5419 
                                "an output modifier");
5420 
      else
5421 
        output_operand_lossage ("invalid expression for output "
5422 
                                "modifier '%c'", code);
5423 
      break;
5424 
    }
5425 
}
5426 
 
5427 
/* Target hook for assembling integer objects.  We need to define it
5428 
   here to work a round a bug in some versions of GAS, which couldn't
5429 
   handle values smaller than INT_MIN when printed in decimal.  */
5430 
 
5431 
static bool
5432 
s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5433 
{
5434 
  if (size == 8 && aligned_p
5435 
      && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5436 
    {
5437 
      fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5438 
               INTVAL (x));
5439 
      return true;
5440 
    }
5441 
  return default_assemble_integer (x, size, aligned_p);
5442 
}
5443 
 
5444 
/* Returns true if register REGNO is used  for forming
5445 
   a memory address in expression X.  */
5446 
 
5447 
static bool
5448 
reg_used_in_mem_p (int regno, rtx x)
5449 
{
5450 
  enum rtx_code code = GET_CODE (x);
5451 
  int i, j;
5452 
  const char *fmt;
5453 
 
5454 
  if (code == MEM)
5455 
    {
5456 
      if (refers_to_regno_p (regno, regno+1,
5457 
                             XEXP (x, 0), 0))
5458 
        return true;
5459 
    }
5460 
  else if (code == SET
5461 
           && GET_CODE (SET_DEST (x)) == PC)
5462 
    {
5463 
      if (refers_to_regno_p (regno, regno+1,
5464 
                             SET_SRC (x), 0))
5465 
        return true;
5466 
    }
5467 
 
5468 
  fmt = GET_RTX_FORMAT (code);
5469 
  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5470 
    {
5471 
      if (fmt[i] == 'e'
5472 
          && reg_used_in_mem_p (regno, XEXP (x, i)))
5473 
        return true;
5474 
 
5475 
      else if (fmt[i] == 'E')
5476 
        for (j = 0; j < XVECLEN (x, i); j++)
5477 
          if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5478 
            return true;
5479 
    }
5480 
  return false;
5481 
}
5482 
 
5483 
/* Returns true if expression DEP_RTX sets an address register
5484 
   used by instruction INSN to address memory.  */
5485 
 
5486 
static bool
5487 
addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5488 
{
5489 
  rtx target, pat;
5490 
 
5491 
  if (GET_CODE (dep_rtx) == INSN)
5492 
      dep_rtx = PATTERN (dep_rtx);
5493 
 
5494 
  if (GET_CODE (dep_rtx) == SET)
5495 
    {
5496 
      target = SET_DEST (dep_rtx);
5497 
      if (GET_CODE (target) == STRICT_LOW_PART)
5498 
        target = XEXP (target, 0);
5499 
      while (GET_CODE (target) == SUBREG)
5500 
        target = SUBREG_REG (target);
5501 
 
5502 
      if (GET_CODE (target) == REG)
5503 
        {
5504 
          int regno = REGNO (target);
5505 
 
5506 
          if (s390_safe_attr_type (insn) == TYPE_LA)
5507 
            {
5508 
              pat = PATTERN (insn);
5509 
              if (GET_CODE (pat) == PARALLEL)
5510 
                {
5511 
                  gcc_assert (XVECLEN (pat, 0) == 2);
5512 
                  pat = XVECEXP (pat, 0, 0);
5513 
                }
5514 
              gcc_assert (GET_CODE (pat) == SET);
5515 
              return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5516 
            }
5517 
          else if (get_attr_atype (insn) == ATYPE_AGEN)
5518 
            return reg_used_in_mem_p (regno, PATTERN (insn));
5519 
        }
5520 
    }
5521 
  return false;
5522 
}
5523 
 
5524 
/* Return 1, if dep_insn sets register used in insn in the agen unit.  */
5525 
 
5526 
int
5527 
s390_agen_dep_p (rtx dep_insn, rtx insn)
5528 
{
5529 
  rtx dep_rtx = PATTERN (dep_insn);
5530 
  int i;
5531 
 
5532 
  if (GET_CODE (dep_rtx) == SET
5533 
      && addr_generation_dependency_p (dep_rtx, insn))
5534 
    return 1;
5535 
  else if (GET_CODE (dep_rtx) == PARALLEL)
5536 
    {
5537 
      for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5538 
        {
5539 
          if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5540 
            return 1;
5541 
        }
5542 
    }
5543 
  return 0;
5544 
}
5545 
 
5546 
 
5547 
/* A C statement (sans semicolon) to update the integer scheduling priority
5548 
   INSN_PRIORITY (INSN).  Increase the priority to execute the INSN earlier,
5549 
   reduce the priority to execute INSN later.  Do not define this macro if
5550 
   you do not need to adjust the scheduling priorities of insns.
5551 
 
5552 
   A STD instruction should be scheduled earlier,
5553 
   in order to use the bypass.  */
5554 
static int
5555 
s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5556 
{
5557 
  if (! INSN_P (insn))
5558 
    return priority;
5559 
 
5560 
  if (s390_tune != PROCESSOR_2084_Z990
5561 
      && s390_tune != PROCESSOR_2094_Z9_109
5562 
      && s390_tune != PROCESSOR_2097_Z10
5563 
      && s390_tune != PROCESSOR_2817_Z196)
5564 
    return priority;
5565 
 
5566 
  switch (s390_safe_attr_type (insn))
5567 
    {
5568 
      case TYPE_FSTOREDF:
5569 
      case TYPE_FSTORESF:
5570 
        priority = priority << 3;
5571 
        break;
5572 
      case TYPE_STORE:
5573 
      case TYPE_STM:
5574 
        priority = priority << 1;
5575 
        break;
5576 
      default:
5577 
        break;
5578 
    }
5579 
  return priority;
5580 
}
5581 
 
5582 
 
5583 
/* The number of instructions that can be issued per cycle.  */
5584 
 
5585 
static int
5586 
s390_issue_rate (void)
5587 
{
5588 
  switch (s390_tune)
5589 
    {
5590 
    case PROCESSOR_2084_Z990:
5591 
    case PROCESSOR_2094_Z9_109:
5592 
    case PROCESSOR_2817_Z196:
5593 
      return 3;
5594 
    case PROCESSOR_2097_Z10:
5595 
      return 2;
5596 
    default:
5597 
      return 1;
5598 
    }
5599 
}
5600 
 
5601 
static int
5602 
s390_first_cycle_multipass_dfa_lookahead (void)
5603 
{
5604 
  return 4;
5605 
}
5606 
 
5607 
/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5608 
   Fix up MEMs as required.  */
5609 
 
5610 
static void
5611 
annotate_constant_pool_refs (rtx *x)
5612 
{
5613 
  int i, j;
5614 
  const char *fmt;
5615 
 
5616 
  gcc_assert (GET_CODE (*x) != SYMBOL_REF
5617 
              || !CONSTANT_POOL_ADDRESS_P (*x));
5618 
 
5619 
  /* Literal pool references can only occur inside a MEM ...  */
5620 
  if (GET_CODE (*x) == MEM)
5621 
    {
5622 
      rtx memref = XEXP (*x, 0);
5623 
 
5624 
      if (GET_CODE (memref) == SYMBOL_REF
5625 
          && CONSTANT_POOL_ADDRESS_P (memref))
5626 
        {
5627 
          rtx base = cfun->machine->base_reg;
5628 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5629 
                                     UNSPEC_LTREF);
5630 
 
5631 
          *x = replace_equiv_address (*x, addr);
5632 
          return;
5633 
        }
5634 
 
5635 
      if (GET_CODE (memref) == CONST
5636 
          && GET_CODE (XEXP (memref, 0)) == PLUS
5637 
          && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5638 
          && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5639 
          && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5640 
        {
5641 
          HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5642 
          rtx sym = XEXP (XEXP (memref, 0), 0);
5643 
          rtx base = cfun->machine->base_reg;
5644 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5645 
                                     UNSPEC_LTREF);
5646 
 
5647 
          *x = replace_equiv_address (*x, plus_constant (addr, off));
5648 
          return;
5649 
        }
5650 
    }
5651 
 
5652 
  /* ... or a load-address type pattern.  */
5653 
  if (GET_CODE (*x) == SET)
5654 
    {
5655 
      rtx addrref = SET_SRC (*x);
5656 
 
5657 
      if (GET_CODE (addrref) == SYMBOL_REF
5658 
          && CONSTANT_POOL_ADDRESS_P (addrref))
5659 
        {
5660 
          rtx base = cfun->machine->base_reg;
5661 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5662 
                                     UNSPEC_LTREF);
5663 
 
5664 
          SET_SRC (*x) = addr;
5665 
          return;
5666 
        }
5667 
 
5668 
      if (GET_CODE (addrref) == CONST
5669 
          && GET_CODE (XEXP (addrref, 0)) == PLUS
5670 
          && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5671 
          && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5672 
          && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5673 
        {
5674 
          HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5675 
          rtx sym = XEXP (XEXP (addrref, 0), 0);
5676 
          rtx base = cfun->machine->base_reg;
5677 
          rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5678 
                                     UNSPEC_LTREF);
5679 
 
5680 
          SET_SRC (*x) = plus_constant (addr, off);
5681 
          return;
5682 
        }
5683 
    }
5684 
 
5685 
  /* Annotate LTREL_BASE as well.  */
5686 
  if (GET_CODE (*x) == UNSPEC
5687 
      && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5688 
    {
5689 
      rtx base = cfun->machine->base_reg;
5690 
      *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5691 
                                  UNSPEC_LTREL_BASE);
5692 
      return;
5693 
    }
5694 
 
5695 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
5696 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5697 
    {
5698 
      if (fmt[i] == 'e')
5699 
        {
5700 
          annotate_constant_pool_refs (&XEXP (*x, i));
5701 
        }
5702 
      else if (fmt[i] == 'E')
5703 
        {
5704 
          for (j = 0; j < XVECLEN (*x, i); j++)
5705 
            annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5706 
        }
5707 
    }
5708 
}
5709 
 
5710 
/* Split all branches that exceed the maximum distance.
5711 
   Returns true if this created a new literal pool entry.  */
5712 
 
5713 
static int
5714 
s390_split_branches (void)
5715 
{
5716 
  rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5717 
  int new_literal = 0, ret;
5718 
  rtx insn, pat, tmp, target;
5719 
  rtx *label;
5720 
 
5721 
  /* We need correct insn addresses.  */
5722 
 
5723 
  shorten_branches (get_insns ());
5724 
 
5725 
  /* Find all branches that exceed 64KB, and split them.  */
5726 
 
5727 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5728 
    {
5729 
      if (GET_CODE (insn) != JUMP_INSN)
5730 
        continue;
5731 
 
5732 
      pat = PATTERN (insn);
5733 
      if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5734 
        pat = XVECEXP (pat, 0, 0);
5735 
      if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5736 
        continue;
5737 
 
5738 
      if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5739 
        {
5740 
          label = &SET_SRC (pat);
5741 
        }
5742 
      else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5743 
        {
5744 
          if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5745 
            label = &XEXP (SET_SRC (pat), 1);
5746 
          else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5747 
            label = &XEXP (SET_SRC (pat), 2);
5748 
          else
5749 
            continue;
5750 
        }
5751 
      else
5752 
        continue;
5753 
 
5754 
      if (get_attr_length (insn) <= 4)
5755 
        continue;
5756 
 
5757 
      /* We are going to use the return register as scratch register,
5758 
         make sure it will be saved/restored by the prologue/epilogue.  */
5759 
      cfun_frame_layout.save_return_addr_p = 1;
5760 
 
5761 
      if (!flag_pic)
5762 
        {
5763 
          new_literal = 1;
5764 
          tmp = force_const_mem (Pmode, *label);
5765 
          tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5766 
          INSN_ADDRESSES_NEW (tmp, -1);
5767 
          annotate_constant_pool_refs (&PATTERN (tmp));
5768 
 
5769 
          target = temp_reg;
5770 
        }
5771 
      else
5772 
        {
5773 
          new_literal = 1;
5774 
          target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5775 
                                   UNSPEC_LTREL_OFFSET);
5776 
          target = gen_rtx_CONST (Pmode, target);
5777 
          target = force_const_mem (Pmode, target);
5778 
          tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5779 
          INSN_ADDRESSES_NEW (tmp, -1);
5780 
          annotate_constant_pool_refs (&PATTERN (tmp));
5781 
 
5782 
          target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5783 
                                                        cfun->machine->base_reg),
5784 
                                   UNSPEC_LTREL_BASE);
5785 
          target = gen_rtx_PLUS (Pmode, temp_reg, target);
5786 
        }
5787 
 
5788 
      ret = validate_change (insn, label, target, 0);
5789 
      gcc_assert (ret);
5790 
    }
5791 
 
5792 
  return new_literal;
5793 
}
5794 
 
5795 
 
5796 
/* Find an annotated literal pool symbol referenced in RTX X,
5797 
   and store it at REF.  Will abort if X contains references to
5798 
   more than one such pool symbol; multiple references to the same
5799 
   symbol are allowed, however.
5800 
 
5801 
   The rtx pointed to by REF must be initialized to NULL_RTX
5802 
   by the caller before calling this routine.  */
5803 
 
5804 
static void
5805 
find_constant_pool_ref (rtx x, rtx *ref)
5806 
{
5807 
  int i, j;
5808 
  const char *fmt;
5809 
 
5810 
  /* Ignore LTREL_BASE references.  */
5811 
  if (GET_CODE (x) == UNSPEC
5812 
      && XINT (x, 1) == UNSPEC_LTREL_BASE)
5813 
    return;
5814 
  /* Likewise POOL_ENTRY insns.  */
5815 
  if (GET_CODE (x) == UNSPEC_VOLATILE
5816 
      && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5817 
    return;
5818 
 
5819 
  gcc_assert (GET_CODE (x) != SYMBOL_REF
5820 
              || !CONSTANT_POOL_ADDRESS_P (x));
5821 
 
5822 
  if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5823 
    {
5824 
      rtx sym = XVECEXP (x, 0, 0);
5825 
      gcc_assert (GET_CODE (sym) == SYMBOL_REF
5826 
                  && CONSTANT_POOL_ADDRESS_P (sym));
5827 
 
5828 
      if (*ref == NULL_RTX)
5829 
        *ref = sym;
5830 
      else
5831 
        gcc_assert (*ref == sym);
5832 
 
5833 
      return;
5834 
    }
5835 
 
5836 
  fmt = GET_RTX_FORMAT (GET_CODE (x));
5837 
  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5838 
    {
5839 
      if (fmt[i] == 'e')
5840 
        {
5841 
          find_constant_pool_ref (XEXP (x, i), ref);
5842 
        }
5843 
      else if (fmt[i] == 'E')
5844 
        {
5845 
          for (j = 0; j < XVECLEN (x, i); j++)
5846 
            find_constant_pool_ref (XVECEXP (x, i, j), ref);
5847 
        }
5848 
    }
5849 
}
5850 
 
5851 
/* Replace every reference to the annotated literal pool
5852 
   symbol REF in X by its base plus OFFSET.  */
5853 
 
5854 
static void
5855 
replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5856 
{
5857 
  int i, j;
5858 
  const char *fmt;
5859 
 
5860 
  gcc_assert (*x != ref);
5861 
 
5862 
  if (GET_CODE (*x) == UNSPEC
5863 
      && XINT (*x, 1) == UNSPEC_LTREF
5864 
      && XVECEXP (*x, 0, 0) == ref)
5865 
    {
5866 
      *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5867 
      return;
5868 
    }
5869 
 
5870 
  if (GET_CODE (*x) == PLUS
5871 
      && GET_CODE (XEXP (*x, 1)) == CONST_INT
5872 
      && GET_CODE (XEXP (*x, 0)) == UNSPEC
5873 
      && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5874 
      && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5875 
    {
5876 
      rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5877 
      *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5878 
      return;
5879 
    }
5880 
 
5881 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
5882 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5883 
    {
5884 
      if (fmt[i] == 'e')
5885 
        {
5886 
          replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5887 
        }
5888 
      else if (fmt[i] == 'E')
5889 
        {
5890 
          for (j = 0; j < XVECLEN (*x, i); j++)
5891 
            replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5892 
        }
5893 
    }
5894 
}
5895 
 
5896 
/* Check whether X contains an UNSPEC_LTREL_BASE.
5897 
   Return its constant pool symbol if found, NULL_RTX otherwise.  */
5898 
 
5899 
static rtx
5900 
find_ltrel_base (rtx x)
5901 
{
5902 
  int i, j;
5903 
  const char *fmt;
5904 
 
5905 
  if (GET_CODE (x) == UNSPEC
5906 
      && XINT (x, 1) == UNSPEC_LTREL_BASE)
5907 
    return XVECEXP (x, 0, 0);
5908 
 
5909 
  fmt = GET_RTX_FORMAT (GET_CODE (x));
5910 
  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5911 
    {
5912 
      if (fmt[i] == 'e')
5913 
        {
5914 
          rtx fnd = find_ltrel_base (XEXP (x, i));
5915 
          if (fnd)
5916 
            return fnd;
5917 
        }
5918 
      else if (fmt[i] == 'E')
5919 
        {
5920 
          for (j = 0; j < XVECLEN (x, i); j++)
5921 
            {
5922 
              rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5923 
              if (fnd)
5924 
                return fnd;
5925 
            }
5926 
        }
5927 
    }
5928 
 
5929 
  return NULL_RTX;
5930 
}
5931 
 
5932 
/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base.  */
5933 
 
5934 
static void
5935 
replace_ltrel_base (rtx *x)
5936 
{
5937 
  int i, j;
5938 
  const char *fmt;
5939 
 
5940 
  if (GET_CODE (*x) == UNSPEC
5941 
      && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5942 
    {
5943 
      *x = XVECEXP (*x, 0, 1);
5944 
      return;
5945 
    }
5946 
 
5947 
  fmt = GET_RTX_FORMAT (GET_CODE (*x));
5948 
  for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5949 
    {
5950 
      if (fmt[i] == 'e')
5951 
        {
5952 
          replace_ltrel_base (&XEXP (*x, i));
5953 
        }
5954 
      else if (fmt[i] == 'E')
5955 
        {
5956 
          for (j = 0; j < XVECLEN (*x, i); j++)
5957 
            replace_ltrel_base (&XVECEXP (*x, i, j));
5958 
        }
5959 
    }
5960 
}
5961 
 
5962 
 
5963 
/* We keep a list of constants which we have to add to internal
5964 
   constant tables in the middle of large functions.  */
5965 
 
5966 
#define NR_C_MODES 11
5967 
enum machine_mode constant_modes[NR_C_MODES] =
5968 
{
5969 
  TFmode, TImode, TDmode,
5970 
  DFmode, DImode, DDmode,
5971 
  SFmode, SImode, SDmode,
5972 
  HImode,
5973 
  QImode
5974 
};
5975 
 
5976 
struct constant
5977 
{
5978 
  struct constant *next;
5979 
  rtx value;
5980 
  rtx label;
5981 
};
5982 
 
5983 
struct constant_pool
5984 
{
5985 
  struct constant_pool *next;
5986 
  rtx first_insn;
5987 
  rtx pool_insn;
5988 
  bitmap insns;
5989 
  rtx emit_pool_after;
5990 
 
5991 
  struct constant *constants[NR_C_MODES];
5992 
  struct constant *execute;
5993 
  rtx label;
5994 
  int size;
5995 
};
5996 
 
5997 
/* Allocate new constant_pool structure.  */
5998 
 
5999 
static struct constant_pool *
6000 
s390_alloc_pool (void)
6001 
{
6002 
  struct constant_pool *pool;
6003 
  int i;
6004 
 
6005 
  pool = (struct constant_pool *) xmalloc (sizeof *pool);
6006 
  pool->next = NULL;
6007 
  for (i = 0; i < NR_C_MODES; i++)
6008 
    pool->constants[i] = NULL;
6009 
 
6010 
  pool->execute = NULL;
6011 
  pool->label = gen_label_rtx ();
6012 
  pool->first_insn = NULL_RTX;
6013 
  pool->pool_insn = NULL_RTX;
6014 
  pool->insns = BITMAP_ALLOC (NULL);
6015 
  pool->size = 0;
6016 
  pool->emit_pool_after = NULL_RTX;
6017 
 
6018 
  return pool;
6019 
}
6020 
 
6021 
/* Create new constant pool covering instructions starting at INSN
6022 
   and chain it to the end of POOL_LIST.  */
6023 
 
6024 
static struct constant_pool *
6025 
s390_start_pool (struct constant_pool **pool_list, rtx insn)
6026 
{
6027 
  struct constant_pool *pool, **prev;
6028 
 
6029 
  pool = s390_alloc_pool ();
6030 
  pool->first_insn = insn;
6031 
 
6032 
  for (prev = pool_list; *prev; prev = &(*prev)->next)
6033 
    ;
6034 
  *prev = pool;
6035 
 
6036 
  return pool;
6037 
}
6038 
 
6039 
/* End range of instructions covered by POOL at INSN and emit
6040 
   placeholder insn representing the pool.  */
6041 
 
6042 
static void
6043 
s390_end_pool (struct constant_pool *pool, rtx insn)
6044 
{
6045 
  rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6046 
 
6047 
  if (!insn)
6048 
    insn = get_last_insn ();
6049 
 
6050 
  pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6051 
  INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6052 
}
6053 
 
6054 
/* Add INSN to the list of insns covered by POOL.  */
6055 
 
6056 
static void
6057 
s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6058 
{
6059 
  bitmap_set_bit (pool->insns, INSN_UID (insn));
6060 
}
6061 
 
6062 
/* Return pool out of POOL_LIST that covers INSN.  */
6063 
 
6064 
static struct constant_pool *
6065 
s390_find_pool (struct constant_pool *pool_list, rtx insn)
6066 
{
6067 
  struct constant_pool *pool;
6068 
 
6069 
  for (pool = pool_list; pool; pool = pool->next)
6070 
    if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6071 
      break;
6072 
 
6073 
  return pool;
6074 
}
6075 
 
6076 
/* Add constant VAL of mode MODE to the constant pool POOL.  */
6077 
 
6078 
static void
6079 
s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6080 
{
6081 
  struct constant *c;
6082 
  int i;
6083 
 
6084 
  for (i = 0; i < NR_C_MODES; i++)
6085 
    if (constant_modes[i] == mode)
6086 
      break;
6087 
  gcc_assert (i != NR_C_MODES);
6088 
 
6089 
  for (c = pool->constants[i]; c != NULL; c = c->next)
6090 
    if (rtx_equal_p (val, c->value))
6091 
      break;
6092 
 
6093 
  if (c == NULL)
6094 
    {
6095 
      c = (struct constant *) xmalloc (sizeof *c);
6096 
      c->value = val;
6097 
      c->label = gen_label_rtx ();
6098 
      c->next = pool->constants[i];
6099 
      pool->constants[i] = c;
6100 
      pool->size += GET_MODE_SIZE (mode);
6101 
    }
6102 
}
6103 
 
6104 
/* Return an rtx that represents the offset of X from the start of
6105 
   pool POOL.  */
6106 
 
6107 
static rtx
6108 
s390_pool_offset (struct constant_pool *pool, rtx x)
6109 
{
6110 
  rtx label;
6111 
 
6112 
  label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6113 
  x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6114 
                      UNSPEC_POOL_OFFSET);
6115 
  return gen_rtx_CONST (GET_MODE (x), x);
6116 
}
6117 
 
6118 
/* Find constant VAL of mode MODE in the constant pool POOL.
6119 
   Return an RTX describing the distance from the start of
6120 
   the pool to the location of the new constant.  */
6121 
 
6122 
static rtx
6123 
s390_find_constant (struct constant_pool *pool, rtx val,
6124 
                    enum machine_mode mode)
6125 
{
6126 
  struct constant *c;
6127 
  int i;
6128 
 
6129 
  for (i = 0; i < NR_C_MODES; i++)
6130 
    if (constant_modes[i] == mode)
6131 
      break;
6132 
  gcc_assert (i != NR_C_MODES);
6133 
 
6134 
  for (c = pool->constants[i]; c != NULL; c = c->next)
6135 
    if (rtx_equal_p (val, c->value))
6136 
      break;
6137 
 
6138 
  gcc_assert (c);
6139 
 
6140 
  return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6141 
}
6142 
 
6143 
/* Check whether INSN is an execute.  Return the label_ref to its
6144 
   execute target template if so, NULL_RTX otherwise.  */
6145 
 
6146 
static rtx
6147 
s390_execute_label (rtx insn)
6148 
{
6149 
  if (GET_CODE (insn) == INSN
6150 
      && GET_CODE (PATTERN (insn)) == PARALLEL
6151 
      && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6152 
      && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6153 
    return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6154 
 
6155 
  return NULL_RTX;
6156 
}
6157 
 
6158 
/* Add execute target for INSN to the constant pool POOL.  */
6159 
 
6160 
static void
6161 
s390_add_execute (struct constant_pool *pool, rtx insn)
6162 
{
6163 
  struct constant *c;
6164 
 
6165 
  for (c = pool->execute; c != NULL; c = c->next)
6166 
    if (INSN_UID (insn) == INSN_UID (c->value))
6167 
      break;
6168 
 
6169 
  if (c == NULL)
6170 
    {
6171 
      c = (struct constant *) xmalloc (sizeof *c);
6172 
      c->value = insn;
6173 
      c->label = gen_label_rtx ();
6174 
      c->next = pool->execute;
6175 
      pool->execute = c;
6176 
      pool->size += 6;
6177 
    }
6178 
}
6179 
 
6180 
/* Find execute target for INSN in the constant pool POOL.
6181 
   Return an RTX describing the distance from the start of
6182 
   the pool to the location of the execute target.  */
6183 
 
6184 
static rtx
6185 
s390_find_execute (struct constant_pool *pool, rtx insn)
6186 
{
6187 
  struct constant *c;
6188 
 
6189 
  for (c = pool->execute; c != NULL; c = c->next)
6190 
    if (INSN_UID (insn) == INSN_UID (c->value))
6191 
      break;
6192 
 
6193 
  gcc_assert (c);
6194 
 
6195 
  return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6196 
}
6197 
 
6198 
/* For an execute INSN, extract the execute target template.  */
6199 
 
6200 
static rtx
6201 
s390_execute_target (rtx insn)
6202 
{
6203 
  rtx pattern = PATTERN (insn);
6204 
  gcc_assert (s390_execute_label (insn));
6205 
 
6206 
  if (XVECLEN (pattern, 0) == 2)
6207 
    {
6208 
      pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6209 
    }
6210 
  else
6211 
    {
6212 
      rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6213 
      int i;
6214 
 
6215 
      for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6216 
        RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6217 
 
6218 
      pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6219 
    }
6220 
 
6221 
  return pattern;
6222 
}
6223 
 
6224 
/* Indicate that INSN cannot be duplicated.  This is the case for
6225 
   execute insns that carry a unique label.  */
6226 
 
6227 
static bool
6228 
s390_cannot_copy_insn_p (rtx insn)
6229 
{
6230 
  rtx label = s390_execute_label (insn);
6231 
  return label && label != const0_rtx;
6232 
}
6233 
 
6234 
/* Dump out the constants in POOL.  If REMOTE_LABEL is true,
6235 
   do not emit the pool base label.  */
6236 
 
6237 
static void
6238 
s390_dump_pool (struct constant_pool *pool, bool remote_label)
6239 
{
6240 
  struct constant *c;
6241 
  rtx insn = pool->pool_insn;
6242 
  int i;
6243 
 
6244 
  /* Switch to rodata section.  */
6245 
  if (TARGET_CPU_ZARCH)
6246 
    {
6247 
      insn = emit_insn_after (gen_pool_section_start (), insn);
6248 
      INSN_ADDRESSES_NEW (insn, -1);
6249 
    }
6250 
 
6251 
  /* Ensure minimum pool alignment.  */
6252 
  if (TARGET_CPU_ZARCH)
6253 
    insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6254 
  else
6255 
    insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6256 
  INSN_ADDRESSES_NEW (insn, -1);
6257 
 
6258 
  /* Emit pool base label.  */
6259 
  if (!remote_label)
6260 
    {
6261 
      insn = emit_label_after (pool->label, insn);
6262 
      INSN_ADDRESSES_NEW (insn, -1);
6263 
    }
6264 
 
6265 
  /* Dump constants in descending alignment requirement order,
6266 
     ensuring proper alignment for every constant.  */
6267 
  for (i = 0; i < NR_C_MODES; i++)
6268 
    for (c = pool->constants[i]; c; c = c->next)
6269 
      {
6270 
        /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references.  */
6271 
        rtx value = copy_rtx (c->value);
6272 
        if (GET_CODE (value) == CONST
6273 
            && GET_CODE (XEXP (value, 0)) == UNSPEC
6274 
            && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6275 
            && XVECLEN (XEXP (value, 0), 0) == 1)
6276 
          value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6277 
 
6278 
        insn = emit_label_after (c->label, insn);
6279 
        INSN_ADDRESSES_NEW (insn, -1);
6280 
 
6281 
        value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6282 
                                         gen_rtvec (1, value),
6283 
                                         UNSPECV_POOL_ENTRY);
6284 
        insn = emit_insn_after (value, insn);
6285 
        INSN_ADDRESSES_NEW (insn, -1);
6286 
      }
6287 
 
6288 
  /* Ensure minimum alignment for instructions.  */
6289 
  insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6290 
  INSN_ADDRESSES_NEW (insn, -1);
6291 
 
6292 
  /* Output in-pool execute template insns.  */
6293 
  for (c = pool->execute; c; c = c->next)
6294 
    {
6295 
      insn = emit_label_after (c->label, insn);
6296 
      INSN_ADDRESSES_NEW (insn, -1);
6297 
 
6298 
      insn = emit_insn_after (s390_execute_target (c->value), insn);
6299 
      INSN_ADDRESSES_NEW (insn, -1);
6300 
    }
6301 
 
6302 
  /* Switch back to previous section.  */
6303 
  if (TARGET_CPU_ZARCH)
6304 
    {
6305 
      insn = emit_insn_after (gen_pool_section_end (), insn);
6306 
      INSN_ADDRESSES_NEW (insn, -1);
6307 
    }
6308 
 
6309 
  insn = emit_barrier_after (insn);
6310 
  INSN_ADDRESSES_NEW (insn, -1);
6311 
 
6312 
  /* Remove placeholder insn.  */
6313 
  remove_insn (pool->pool_insn);
6314 
}
6315 
 
6316 
/* Free all memory used by POOL.  */
6317 
 
6318 
static void
6319 
s390_free_pool (struct constant_pool *pool)
6320 
{
6321 
  struct constant *c, *next;
6322 
  int i;
6323 
 
6324 
  for (i = 0; i < NR_C_MODES; i++)
6325 
    for (c = pool->constants[i]; c; c = next)
6326 
      {
6327 
        next = c->next;
6328 
        free (c);
6329 
      }
6330 
 
6331 
  for (c = pool->execute; c; c = next)
6332 
    {
6333 
      next = c->next;
6334 
      free (c);
6335 
    }
6336 
 
6337 
  BITMAP_FREE (pool->insns);
6338 
  free (pool);
6339 
}
6340 
 
6341 
 
6342 
/* Collect main literal pool.  Return NULL on overflow.  */
6343 
 
6344 
static struct constant_pool *
6345 
s390_mainpool_start (void)
6346 
{
6347 
  struct constant_pool *pool;
6348 
  rtx insn;
6349 
 
6350 
  pool = s390_alloc_pool ();
6351 
 
6352 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6353 
    {
6354 
      if (GET_CODE (insn) == INSN
6355 
          && GET_CODE (PATTERN (insn)) == SET
6356 
          && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6357 
          && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6358 
        {
6359 
          gcc_assert (!pool->pool_insn);
6360 
          pool->pool_insn = insn;
6361 
        }
6362 
 
6363 
      if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6364 
        {
6365 
          s390_add_execute (pool, insn);
6366 
        }
6367 
      else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6368 
        {
6369 
          rtx pool_ref = NULL_RTX;
6370 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
6371 
          if (pool_ref)
6372 
            {
6373 
              rtx constant = get_pool_constant (pool_ref);
6374 
              enum machine_mode mode = get_pool_mode (pool_ref);
6375 
              s390_add_constant (pool, constant, mode);
6376 
            }
6377 
        }
6378 
 
6379 
      /* If hot/cold partitioning is enabled we have to make sure that
6380 
         the literal pool is emitted in the same section where the
6381 
         initialization of the literal pool base pointer takes place.
6382 
         emit_pool_after is only used in the non-overflow case on non
6383 
         Z cpus where we can emit the literal pool at the end of the
6384 
         function body within the text section.  */
6385 
      if (NOTE_P (insn)
6386 
          && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6387 
          && !pool->emit_pool_after)
6388 
        pool->emit_pool_after = PREV_INSN (insn);
6389 
    }
6390 
 
6391 
  gcc_assert (pool->pool_insn || pool->size == 0);
6392 
 
6393 
  if (pool->size >= 4096)
6394 
    {
6395 
      /* We're going to chunkify the pool, so remove the main
6396 
         pool placeholder insn.  */
6397 
      remove_insn (pool->pool_insn);
6398 
 
6399 
      s390_free_pool (pool);
6400 
      pool = NULL;
6401 
    }
6402 
 
6403 
  /* If the functions ends with the section where the literal pool
6404 
     should be emitted set the marker to its end.  */
6405 
  if (pool && !pool->emit_pool_after)
6406 
    pool->emit_pool_after = get_last_insn ();
6407 
 
6408 
  return pool;
6409 
}
6410 
 
6411 
/* POOL holds the main literal pool as collected by s390_mainpool_start.
6412 
   Modify the current function to output the pool constants as well as
6413 
   the pool register setup instruction.  */
6414 
 
6415 
static void
6416 
s390_mainpool_finish (struct constant_pool *pool)
6417 
{
6418 
  rtx base_reg = cfun->machine->base_reg;
6419 
  rtx insn;
6420 
 
6421 
  /* If the pool is empty, we're done.  */
6422 
  if (pool->size == 0)
6423 
    {
6424 
      /* We don't actually need a base register after all.  */
6425 
      cfun->machine->base_reg = NULL_RTX;
6426 
 
6427 
      if (pool->pool_insn)
6428 
        remove_insn (pool->pool_insn);
6429 
      s390_free_pool (pool);
6430 
      return;
6431 
    }
6432 
 
6433 
  /* We need correct insn addresses.  */
6434 
  shorten_branches (get_insns ());
6435 
 
6436 
  /* On zSeries, we use a LARL to load the pool register.  The pool is
6437 
     located in the .rodata section, so we emit it after the function.  */
6438 
  if (TARGET_CPU_ZARCH)
6439 
    {
6440 
      insn = gen_main_base_64 (base_reg, pool->label);
6441 
      insn = emit_insn_after (insn, pool->pool_insn);
6442 
      INSN_ADDRESSES_NEW (insn, -1);
6443 
      remove_insn (pool->pool_insn);
6444 
 
6445 
      insn = get_last_insn ();
6446 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6447 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6448 
 
6449 
      s390_dump_pool (pool, 0);
6450 
    }
6451 
 
6452 
  /* On S/390, if the total size of the function's code plus literal pool
6453 
     does not exceed 4096 bytes, we use BASR to set up a function base
6454 
     pointer, and emit the literal pool at the end of the function.  */
6455 
  else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6456 
           + pool->size + 8 /* alignment slop */ < 4096)
6457 
    {
6458 
      insn = gen_main_base_31_small (base_reg, pool->label);
6459 
      insn = emit_insn_after (insn, pool->pool_insn);
6460 
      INSN_ADDRESSES_NEW (insn, -1);
6461 
      remove_insn (pool->pool_insn);
6462 
 
6463 
      insn = emit_label_after (pool->label, insn);
6464 
      INSN_ADDRESSES_NEW (insn, -1);
6465 
 
6466 
      /* emit_pool_after will be set by s390_mainpool_start to the
6467 
         last insn of the section where the literal pool should be
6468 
         emitted.  */
6469 
      insn = pool->emit_pool_after;
6470 
 
6471 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6472 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6473 
 
6474 
      s390_dump_pool (pool, 1);
6475 
    }
6476 
 
6477 
  /* Otherwise, we emit an inline literal pool and use BASR to branch
6478 
     over it, setting up the pool register at the same time.  */
6479 
  else
6480 
    {
6481 
      rtx pool_end = gen_label_rtx ();
6482 
 
6483 
      insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6484 
      insn = emit_jump_insn_after (insn, pool->pool_insn);
6485 
      JUMP_LABEL (insn) = pool_end;
6486 
      INSN_ADDRESSES_NEW (insn, -1);
6487 
      remove_insn (pool->pool_insn);
6488 
 
6489 
      insn = emit_label_after (pool->label, insn);
6490 
      INSN_ADDRESSES_NEW (insn, -1);
6491 
 
6492 
      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6493 
      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6494 
 
6495 
      insn = emit_label_after (pool_end, pool->pool_insn);
6496 
      INSN_ADDRESSES_NEW (insn, -1);
6497 
 
6498 
      s390_dump_pool (pool, 1);
6499 
    }
6500 
 
6501 
 
6502 
  /* Replace all literal pool references.  */
6503 
 
6504 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6505 
    {
6506 
      if (INSN_P (insn))
6507 
        replace_ltrel_base (&PATTERN (insn));
6508 
 
6509 
      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6510 
        {
6511 
          rtx addr, pool_ref = NULL_RTX;
6512 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
6513 
          if (pool_ref)
6514 
            {
6515 
              if (s390_execute_label (insn))
6516 
                addr = s390_find_execute (pool, insn);
6517 
              else
6518 
                addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6519 
                                                 get_pool_mode (pool_ref));
6520 
 
6521 
              replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6522 
              INSN_CODE (insn) = -1;
6523 
            }
6524 
        }
6525 
    }
6526 
 
6527 
 
6528 
  /* Free the pool.  */
6529 
  s390_free_pool (pool);
6530 
}
6531 
 
6532 
/* POOL holds the main literal pool as collected by s390_mainpool_start.
6533 
   We have decided we cannot use this pool, so revert all changes
6534 
   to the current function that were done by s390_mainpool_start.  */
6535 
static void
6536 
s390_mainpool_cancel (struct constant_pool *pool)
6537 
{
6538 
  /* We didn't actually change the instruction stream, so simply
6539 
     free the pool memory.  */
6540 
  s390_free_pool (pool);
6541 
}
6542 
 
6543 
 
6544 
/* Chunkify the literal pool.  */
6545 
 
6546 
#define S390_POOL_CHUNK_MIN     0xc00
6547 
#define S390_POOL_CHUNK_MAX     0xe00
6548 
 
6549 
static struct constant_pool *
6550 
s390_chunkify_start (void)
6551 
{
6552 
  struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6553 
  int extra_size = 0;
6554 
  bitmap far_labels;
6555 
  rtx pending_ltrel = NULL_RTX;
6556 
  rtx insn;
6557 
 
6558 
  rtx (*gen_reload_base) (rtx, rtx) =
6559 
    TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6560 
 
6561 
 
6562 
  /* We need correct insn addresses.  */
6563 
 
6564 
  shorten_branches (get_insns ());
6565 
 
6566 
  /* Scan all insns and move literals to pool chunks.  */
6567 
 
6568 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6569 
    {
6570 
      bool section_switch_p = false;
6571 
 
6572 
      /* Check for pending LTREL_BASE.  */
6573 
      if (INSN_P (insn))
6574 
        {
6575 
          rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6576 
          if (ltrel_base)
6577 
            {
6578 
              gcc_assert (ltrel_base == pending_ltrel);
6579 
              pending_ltrel = NULL_RTX;
6580 
            }
6581 
        }
6582 
 
6583 
      if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6584 
        {
6585 
          if (!curr_pool)
6586 
            curr_pool = s390_start_pool (&pool_list, insn);
6587 
 
6588 
          s390_add_execute (curr_pool, insn);
6589 
          s390_add_pool_insn (curr_pool, insn);
6590 
        }
6591 
      else if (GET_CODE (insn) == INSN || CALL_P (insn))
6592 
        {
6593 
          rtx pool_ref = NULL_RTX;
6594 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
6595 
          if (pool_ref)
6596 
            {
6597 
              rtx constant = get_pool_constant (pool_ref);
6598 
              enum machine_mode mode = get_pool_mode (pool_ref);
6599 
 
6600 
              if (!curr_pool)
6601 
                curr_pool = s390_start_pool (&pool_list, insn);
6602 
 
6603 
              s390_add_constant (curr_pool, constant, mode);
6604 
              s390_add_pool_insn (curr_pool, insn);
6605 
 
6606 
              /* Don't split the pool chunk between a LTREL_OFFSET load
6607 
                 and the corresponding LTREL_BASE.  */
6608 
              if (GET_CODE (constant) == CONST
6609 
                  && GET_CODE (XEXP (constant, 0)) == UNSPEC
6610 
                  && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6611 
                {
6612 
                  gcc_assert (!pending_ltrel);
6613 
                  pending_ltrel = pool_ref;
6614 
                }
6615 
            }
6616 
        }
6617 
 
6618 
      if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6619 
        {
6620 
          if (curr_pool)
6621 
            s390_add_pool_insn (curr_pool, insn);
6622 
          /* An LTREL_BASE must follow within the same basic block.  */
6623 
          gcc_assert (!pending_ltrel);
6624 
        }
6625 
 
6626 
      if (NOTE_P (insn))
6627 
        switch (NOTE_KIND (insn))
6628 
          {
6629 
          case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6630 
            section_switch_p = true;
6631 
            break;
6632 
          case NOTE_INSN_VAR_LOCATION:
6633 
          case NOTE_INSN_CALL_ARG_LOCATION:
6634 
            continue;
6635 
          default:
6636 
            break;
6637 
          }
6638 
 
6639 
      if (!curr_pool
6640 
          || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6641 
          || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6642 
        continue;
6643 
 
6644 
      if (TARGET_CPU_ZARCH)
6645 
        {
6646 
          if (curr_pool->size < S390_POOL_CHUNK_MAX)
6647 
            continue;
6648 
 
6649 
          s390_end_pool (curr_pool, NULL_RTX);
6650 
          curr_pool = NULL;
6651 
        }
6652 
      else
6653 
        {
6654 
          int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6655 
                           - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6656 
                         + extra_size;
6657 
 
6658 
          /* We will later have to insert base register reload insns.
6659 
             Those will have an effect on code size, which we need to
6660 
             consider here.  This calculation makes rather pessimistic
6661 
             worst-case assumptions.  */
6662 
          if (GET_CODE (insn) == CODE_LABEL)
6663 
            extra_size += 6;
6664 
 
6665 
          if (chunk_size < S390_POOL_CHUNK_MIN
6666 
              && curr_pool->size < S390_POOL_CHUNK_MIN
6667 
              && !section_switch_p)
6668 
            continue;
6669 
 
6670 
          /* Pool chunks can only be inserted after BARRIERs ...  */
6671 
          if (GET_CODE (insn) == BARRIER)
6672 
            {
6673 
              s390_end_pool (curr_pool, insn);
6674 
              curr_pool = NULL;
6675 
              extra_size = 0;
6676 
            }
6677 
 
6678 
          /* ... so if we don't find one in time, create one.  */
6679 
          else if (chunk_size > S390_POOL_CHUNK_MAX
6680 
                   || curr_pool->size > S390_POOL_CHUNK_MAX
6681 
                   || section_switch_p)
6682 
            {
6683 
              rtx label, jump, barrier, next, prev;
6684 
 
6685 
              if (!section_switch_p)
6686 
                {
6687 
                  /* We can insert the barrier only after a 'real' insn.  */
6688 
                  if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6689 
                    continue;
6690 
                  if (get_attr_length (insn) == 0)
6691 
                    continue;
6692 
                  /* Don't separate LTREL_BASE from the corresponding
6693 
                     LTREL_OFFSET load.  */
6694 
                  if (pending_ltrel)
6695 
                    continue;
6696 
                  next = insn;
6697 
                  do
6698 
                    {
6699 
                      insn = next;
6700 
                      next = NEXT_INSN (insn);
6701 
                    }
6702 
                  while (next
6703 
                         && NOTE_P (next)
6704 
                         && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6705 
                             || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6706 
                }
6707 
              else
6708 
                {
6709 
                  gcc_assert (!pending_ltrel);
6710 
 
6711 
                  /* The old pool has to end before the section switch
6712 
                     note in order to make it part of the current
6713 
                     section.  */
6714 
                  insn = PREV_INSN (insn);
6715 
                }
6716 
 
6717 
              label = gen_label_rtx ();
6718 
              prev = insn;
6719 
              if (prev && NOTE_P (prev))
6720 
                prev = prev_nonnote_insn (prev);
6721 
              if (prev)
6722 
                jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
6723 
                                                    INSN_LOCATOR (prev));
6724 
              else
6725 
                jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
6726 
              barrier = emit_barrier_after (jump);
6727 
              insn = emit_label_after (label, barrier);
6728 
              JUMP_LABEL (jump) = label;
6729 
              LABEL_NUSES (label) = 1;
6730 
 
6731 
              INSN_ADDRESSES_NEW (jump, -1);
6732 
              INSN_ADDRESSES_NEW (barrier, -1);
6733 
              INSN_ADDRESSES_NEW (insn, -1);
6734 
 
6735 
              s390_end_pool (curr_pool, barrier);
6736 
              curr_pool = NULL;
6737 
              extra_size = 0;
6738 
            }
6739 
        }
6740 
    }
6741 
 
6742 
  if (curr_pool)
6743 
    s390_end_pool (curr_pool, NULL_RTX);
6744 
  gcc_assert (!pending_ltrel);
6745 
 
6746 
  /* Find all labels that are branched into
6747 
     from an insn belonging to a different chunk.  */
6748 
 
6749 
  far_labels = BITMAP_ALLOC (NULL);
6750 
 
6751 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6752 
    {
6753 
      /* Labels marked with LABEL_PRESERVE_P can be target
6754 
         of non-local jumps, so we have to mark them.
6755 
         The same holds for named labels.
6756 
 
6757 
         Don't do that, however, if it is the label before
6758 
         a jump table.  */
6759 
 
6760 
      if (GET_CODE (insn) == CODE_LABEL
6761 
          && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6762 
        {
6763 
          rtx vec_insn = next_real_insn (insn);
6764 
          rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6765 
                        PATTERN (vec_insn) : NULL_RTX;
6766 
          if (!vec_pat
6767 
              || !(GET_CODE (vec_pat) == ADDR_VEC
6768 
                   || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6769 
            bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6770 
        }
6771 
 
6772 
      /* If we have a direct jump (conditional or unconditional)
6773 
         or a casesi jump, check all potential targets.  */
6774 
      else if (GET_CODE (insn) == JUMP_INSN)
6775 
        {
6776 
          rtx pat = PATTERN (insn);
6777 
          if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6778 
            pat = XVECEXP (pat, 0, 0);
6779 
 
6780 
          if (GET_CODE (pat) == SET)
6781 
            {
6782 
              rtx label = JUMP_LABEL (insn);
6783 
              if (label)
6784 
                {
6785 
                  if (s390_find_pool (pool_list, label)
6786 
                      != s390_find_pool (pool_list, insn))
6787 
                    bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6788 
                }
6789 
            }
6790 
          else if (GET_CODE (pat) == PARALLEL
6791 
                   && XVECLEN (pat, 0) == 2
6792 
                   && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6793 
                   && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6794 
                   && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6795 
            {
6796 
              /* Find the jump table used by this casesi jump.  */
6797 
              rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6798 
              rtx vec_insn = next_real_insn (vec_label);
6799 
              rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6800 
                            PATTERN (vec_insn) : NULL_RTX;
6801 
              if (vec_pat
6802 
                  && (GET_CODE (vec_pat) == ADDR_VEC
6803 
                      || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6804 
                {
6805 
                  int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6806 
 
6807 
                  for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6808 
                    {
6809 
                      rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6810 
 
6811 
                      if (s390_find_pool (pool_list, label)
6812 
                          != s390_find_pool (pool_list, insn))
6813 
                        bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6814 
                    }
6815 
                }
6816 
            }
6817 
        }
6818 
    }
6819 
 
6820 
  /* Insert base register reload insns before every pool.  */
6821 
 
6822 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6823 
    {
6824 
      rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6825 
                                      curr_pool->label);
6826 
      rtx insn = curr_pool->first_insn;
6827 
      INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6828 
    }
6829 
 
6830 
  /* Insert base register reload insns at every far label.  */
6831 
 
6832 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6833 
    if (GET_CODE (insn) == CODE_LABEL
6834 
        && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6835 
      {
6836 
        struct constant_pool *pool = s390_find_pool (pool_list, insn);
6837 
        if (pool)
6838 
          {
6839 
            rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6840 
                                            pool->label);
6841 
            INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6842 
          }
6843 
      }
6844 
 
6845 
 
6846 
  BITMAP_FREE (far_labels);
6847 
 
6848 
 
6849 
  /* Recompute insn addresses.  */
6850 
 
6851 
  init_insn_lengths ();
6852 
  shorten_branches (get_insns ());
6853 
 
6854 
  return pool_list;
6855 
}
6856 
 
6857 
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6858 
   After we have decided to use this list, finish implementing
6859 
   all changes to the current function as required.  */
6860 
 
6861 
static void
6862 
s390_chunkify_finish (struct constant_pool *pool_list)
6863 
{
6864 
  struct constant_pool *curr_pool = NULL;
6865 
  rtx insn;
6866 
 
6867 
 
6868 
  /* Replace all literal pool references.  */
6869 
 
6870 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6871 
    {
6872 
      if (INSN_P (insn))
6873 
        replace_ltrel_base (&PATTERN (insn));
6874 
 
6875 
      curr_pool = s390_find_pool (pool_list, insn);
6876 
      if (!curr_pool)
6877 
        continue;
6878 
 
6879 
      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6880 
        {
6881 
          rtx addr, pool_ref = NULL_RTX;
6882 
          find_constant_pool_ref (PATTERN (insn), &pool_ref);
6883 
          if (pool_ref)
6884 
            {
6885 
              if (s390_execute_label (insn))
6886 
                addr = s390_find_execute (curr_pool, insn);
6887 
              else
6888 
                addr = s390_find_constant (curr_pool,
6889 
                                           get_pool_constant (pool_ref),
6890 
                                           get_pool_mode (pool_ref));
6891 
 
6892 
              replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6893 
              INSN_CODE (insn) = -1;
6894 
            }
6895 
        }
6896 
    }
6897 
 
6898 
  /* Dump out all literal pools.  */
6899 
 
6900 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6901 
    s390_dump_pool (curr_pool, 0);
6902 
 
6903 
  /* Free pool list.  */
6904 
 
6905 
  while (pool_list)
6906 
    {
6907 
      struct constant_pool *next = pool_list->next;
6908 
      s390_free_pool (pool_list);
6909 
      pool_list = next;
6910 
    }
6911 
}
6912 
 
6913 
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6914 
   We have decided we cannot use this list, so revert all changes
6915 
   to the current function that were done by s390_chunkify_start.  */
6916 
 
6917 
static void
6918 
s390_chunkify_cancel (struct constant_pool *pool_list)
6919 
{
6920 
  struct constant_pool *curr_pool = NULL;
6921 
  rtx insn;
6922 
 
6923 
  /* Remove all pool placeholder insns.  */
6924 
 
6925 
  for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6926 
    {
6927 
      /* Did we insert an extra barrier?  Remove it.  */
6928 
      rtx barrier = PREV_INSN (curr_pool->pool_insn);
6929 
      rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6930 
      rtx label = NEXT_INSN (curr_pool->pool_insn);
6931 
 
6932 
      if (jump && GET_CODE (jump) == JUMP_INSN
6933 
          && barrier && GET_CODE (barrier) == BARRIER
6934 
          && label && GET_CODE (label) == CODE_LABEL
6935 
          && GET_CODE (PATTERN (jump)) == SET
6936 
          && SET_DEST (PATTERN (jump)) == pc_rtx
6937 
          && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6938 
          && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6939 
        {
6940 
          remove_insn (jump);
6941 
          remove_insn (barrier);
6942 
          remove_insn (label);
6943 
        }
6944 
 
6945 
      remove_insn (curr_pool->pool_insn);
6946 
    }
6947 
 
6948 
  /* Remove all base register reload insns.  */
6949 
 
6950 
  for (insn = get_insns (); insn; )
6951 
    {
6952 
      rtx next_insn = NEXT_INSN (insn);
6953 
 
6954 
      if (GET_CODE (insn) == INSN
6955 
          && GET_CODE (PATTERN (insn)) == SET
6956 
          && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6957 
          && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6958 
        remove_insn (insn);
6959 
 
6960 
      insn = next_insn;
6961 
    }
6962 
 
6963 
  /* Free pool list.  */
6964 
 
6965 
  while (pool_list)
6966 
    {
6967 
      struct constant_pool *next = pool_list->next;
6968 
      s390_free_pool (pool_list);
6969 
      pool_list = next;
6970 
    }
6971 
}
6972 
 
6973 
/* Output the constant pool entry EXP in mode MODE with alignment ALIGN.  */
6974 
 
6975 
void
6976 
s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6977 
{
6978 
  REAL_VALUE_TYPE r;
6979 
 
6980 
  switch (GET_MODE_CLASS (mode))
6981 
    {
6982 
    case MODE_FLOAT:
6983 
    case MODE_DECIMAL_FLOAT:
6984 
      gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6985 
 
6986 
      REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6987 
      assemble_real (r, mode, align);
6988 
      break;
6989 
 
6990 
    case MODE_INT:
6991 
      assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6992 
      mark_symbol_refs_as_used (exp);
6993 
      break;
6994 
 
6995 
    default:
6996 
      gcc_unreachable ();
6997 
    }
6998 
}
6999 
 
7000 
 
7001 
/* Return an RTL expression representing the value of the return address
7002 
   for the frame COUNT steps up from the current frame.  FRAME is the
7003 
   frame pointer of that frame.  */
7004 
 
7005 
rtx
7006 
s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7007 
{
7008 
  int offset;
7009 
  rtx addr;
7010 
 
7011 
  /* Without backchain, we fail for all but the current frame.  */
7012 
 
7013 
  if (!TARGET_BACKCHAIN && count > 0)
7014 
    return NULL_RTX;
7015 
 
7016 
  /* For the current frame, we need to make sure the initial
7017 
     value of RETURN_REGNUM is actually saved.  */
7018 
 
7019 
  if (count == 0)
7020 
    {
7021 
      /* On non-z architectures branch splitting could overwrite r14.  */
7022 
      if (TARGET_CPU_ZARCH)
7023 
        return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7024 
      else
7025 
        {
7026 
          cfun_frame_layout.save_return_addr_p = true;
7027 
          return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7028 
        }
7029 
    }
7030 
 
7031 
  if (TARGET_PACKED_STACK)
7032 
    offset = -2 * UNITS_PER_LONG;
7033 
  else
7034 
    offset = RETURN_REGNUM * UNITS_PER_LONG;
7035 
 
7036 
  addr = plus_constant (frame, offset);
7037 
  addr = memory_address (Pmode, addr);
7038 
  return gen_rtx_MEM (Pmode, addr);
7039 
}
7040 
 
7041 
/* Return an RTL expression representing the back chain stored in
7042 
   the current stack frame.  */
7043 
 
7044 
rtx
7045 
s390_back_chain_rtx (void)
7046 
{
7047 
  rtx chain;
7048 
 
7049 
  gcc_assert (TARGET_BACKCHAIN);
7050 
 
7051 
  if (TARGET_PACKED_STACK)
7052 
    chain = plus_constant (stack_pointer_rtx,
7053 
                           STACK_POINTER_OFFSET - UNITS_PER_LONG);
7054 
  else
7055 
    chain = stack_pointer_rtx;
7056 
 
7057 
  chain = gen_rtx_MEM (Pmode, chain);
7058 
  return chain;
7059 
}
7060 
 
7061 
/* Find first call clobbered register unused in a function.
7062 
   This could be used as base register in a leaf function
7063 
   or for holding the return address before epilogue.  */
7064 
 
7065 
static int
7066 
find_unused_clobbered_reg (void)
7067 
{
7068 
  int i;
7069 
  for (i = 0; i < 6; i++)
7070 
    if (!df_regs_ever_live_p (i))
7071 
      return i;
7072 
  return 0;
7073 
}
7074 
 
7075 
 
7076 
/* Helper function for s390_regs_ever_clobbered.  Sets the fields in DATA for all
7077 
   clobbered hard regs in SETREG.  */
7078 
 
7079 
static void
7080 
s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7081 
{
7082 
  int *regs_ever_clobbered = (int *)data;
7083 
  unsigned int i, regno;
7084 
  enum machine_mode mode = GET_MODE (setreg);
7085 
 
7086 
  if (GET_CODE (setreg) == SUBREG)
7087 
    {
7088 
      rtx inner = SUBREG_REG (setreg);
7089 
      if (!GENERAL_REG_P (inner))
7090 
        return;
7091 
      regno = subreg_regno (setreg);
7092 
    }
7093 
  else if (GENERAL_REG_P (setreg))
7094 
    regno = REGNO (setreg);
7095 
  else
7096 
    return;
7097 
 
7098 
  for (i = regno;
7099 
       i < regno + HARD_REGNO_NREGS (regno, mode);
7100 
       i++)
7101 
    regs_ever_clobbered[i] = 1;
7102 
}
7103 
 
7104 
/* Walks through all basic blocks of the current function looking
7105 
   for clobbered hard regs using s390_reg_clobbered_rtx.  The fields
7106 
   of the passed integer array REGS_EVER_CLOBBERED are set to one for
7107 
   each of those regs.  */
7108 
 
7109 
static void
7110 
s390_regs_ever_clobbered (int *regs_ever_clobbered)
7111 
{
7112 
  basic_block cur_bb;
7113 
  rtx cur_insn;
7114 
  unsigned int i;
7115 
 
7116 
  memset (regs_ever_clobbered, 0, 16 * sizeof (int));
7117 
 
7118 
  /* For non-leaf functions we have to consider all call clobbered regs to be
7119 
     clobbered.  */
7120 
  if (!current_function_is_leaf)
7121 
    {
7122 
      for (i = 0; i < 16; i++)
7123 
        regs_ever_clobbered[i] = call_really_used_regs[i];
7124 
    }
7125 
 
7126 
  /* Make the "magic" eh_return registers live if necessary.  For regs_ever_live
7127 
     this work is done by liveness analysis (mark_regs_live_at_end).
7128 
     Special care is needed for functions containing landing pads.  Landing pads
7129 
     may use the eh registers, but the code which sets these registers is not
7130 
     contained in that function.  Hence s390_regs_ever_clobbered is not able to
7131 
     deal with this automatically.  */
7132 
  if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7133 
    for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7134 
      if (crtl->calls_eh_return
7135 
          || (cfun->machine->has_landing_pad_p
7136 
              && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7137 
        regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7138 
 
7139 
  /* For nonlocal gotos all call-saved registers have to be saved.
7140 
     This flag is also set for the unwinding code in libgcc.
7141 
     See expand_builtin_unwind_init.  For regs_ever_live this is done by
7142 
     reload.  */
7143 
  if (cfun->has_nonlocal_label)
7144 
    for (i = 0; i < 16; i++)
7145 
      if (!call_really_used_regs[i])
7146 
        regs_ever_clobbered[i] = 1;
7147 
 
7148 
  FOR_EACH_BB (cur_bb)
7149 
    {
7150 
      FOR_BB_INSNS (cur_bb, cur_insn)
7151 
        {
7152 
          if (INSN_P (cur_insn))
7153 
            note_stores (PATTERN (cur_insn),
7154 
                         s390_reg_clobbered_rtx,
7155 
                         regs_ever_clobbered);
7156 
        }
7157 
    }
7158 
}
7159 
 
7160 
/* Determine the frame area which actually has to be accessed
7161 
   in the function epilogue. The values are stored at the
7162 
   given pointers AREA_BOTTOM (address of the lowest used stack
7163 
   address) and AREA_TOP (address of the first item which does
7164 
   not belong to the stack frame).  */
7165 
 
7166 
static void
7167 
s390_frame_area (int *area_bottom, int *area_top)
7168 
{
7169 
  int b, t;
7170 
  int i;
7171 
 
7172 
  b = INT_MAX;
7173 
  t = INT_MIN;
7174 
 
7175 
  if (cfun_frame_layout.first_restore_gpr != -1)
7176 
    {
7177 
      b = (cfun_frame_layout.gprs_offset
7178 
           + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7179 
      t = b + (cfun_frame_layout.last_restore_gpr
7180 
               - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7181 
    }
7182 
 
7183 
  if (TARGET_64BIT && cfun_save_high_fprs_p)
7184 
    {
7185 
      b = MIN (b, cfun_frame_layout.f8_offset);
7186 
      t = MAX (t, (cfun_frame_layout.f8_offset
7187 
                   + cfun_frame_layout.high_fprs * 8));
7188 
    }
7189 
 
7190 
  if (!TARGET_64BIT)
7191 
    for (i = 2; i < 4; i++)
7192 
      if (cfun_fpr_bit_p (i))
7193 
        {
7194 
          b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
7195 
          t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
7196 
        }
7197 
 
7198 
  *area_bottom = b;
7199 
  *area_top = t;
7200 
}
7201 
 
7202 
/* Fill cfun->machine with info about register usage of current function.
7203 
   Return in CLOBBERED_REGS which GPRs are currently considered set.  */
7204 
 
7205 
static void
7206 
s390_register_info (int clobbered_regs[])
7207 
{
7208 
  int i, j;
7209 
 
7210 
  /* fprs 8 - 15 are call saved for 64 Bit ABI.  */
7211 
  cfun_frame_layout.fpr_bitmap = 0;
7212 
  cfun_frame_layout.high_fprs = 0;
7213 
  if (TARGET_64BIT)
7214 
    for (i = 24; i < 32; i++)
7215 
      if (df_regs_ever_live_p (i) && !global_regs[i])
7216 
        {
7217 
          cfun_set_fpr_bit (i - 16);
7218 
          cfun_frame_layout.high_fprs++;
7219 
        }
7220 
 
7221 
  /* Find first and last gpr to be saved.  We trust regs_ever_live
7222 
     data, except that we don't save and restore global registers.
7223 
 
7224 
     Also, all registers with special meaning to the compiler need
7225 
     to be handled extra.  */
7226 
 
7227 
  s390_regs_ever_clobbered (clobbered_regs);
7228 
 
7229 
  for (i = 0; i < 16; i++)
7230 
    clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
7231 
 
7232 
  if (frame_pointer_needed)
7233 
    clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
7234 
 
7235 
  if (flag_pic)
7236 
    clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7237 
      |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7238 
 
7239 
  clobbered_regs[BASE_REGNUM]
7240 
    |= (cfun->machine->base_reg
7241 
        && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7242 
 
7243 
  clobbered_regs[RETURN_REGNUM]
7244 
    |= (!current_function_is_leaf
7245 
        || TARGET_TPF_PROFILING
7246 
        || cfun->machine->split_branches_pending_p
7247 
        || cfun_frame_layout.save_return_addr_p
7248 
        || crtl->calls_eh_return
7249 
        || cfun->stdarg);
7250 
 
7251 
  clobbered_regs[STACK_POINTER_REGNUM]
7252 
    |= (!current_function_is_leaf
7253 
        || TARGET_TPF_PROFILING
7254 
        || cfun_save_high_fprs_p
7255 
        || get_frame_size () > 0
7256 
        || cfun->calls_alloca
7257 
        || cfun->stdarg);
7258 
 
7259 
  for (i = 6; i < 16; i++)
7260 
    if (df_regs_ever_live_p (i) || clobbered_regs[i])
7261 
      break;
7262 
  for (j = 15; j > i; j--)
7263 
    if (df_regs_ever_live_p (j) || clobbered_regs[j])
7264 
      break;
7265 
 
7266 
  if (i == 16)
7267 
    {
7268 
      /* Nothing to save/restore.  */
7269 
      cfun_frame_layout.first_save_gpr_slot = -1;
7270 
      cfun_frame_layout.last_save_gpr_slot = -1;
7271 
      cfun_frame_layout.first_save_gpr = -1;
7272 
      cfun_frame_layout.first_restore_gpr = -1;
7273 
      cfun_frame_layout.last_save_gpr = -1;
7274 
      cfun_frame_layout.last_restore_gpr = -1;
7275 
    }
7276 
  else
7277 
    {
7278 
      /* Save slots for gprs from i to j.  */
7279 
      cfun_frame_layout.first_save_gpr_slot = i;
7280 
      cfun_frame_layout.last_save_gpr_slot = j;
7281 
 
7282 
      for (i = cfun_frame_layout.first_save_gpr_slot;
7283 
           i < cfun_frame_layout.last_save_gpr_slot + 1;
7284 
           i++)
7285 
        if (clobbered_regs[i])
7286 
          break;
7287 
 
7288 
      for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7289 
        if (clobbered_regs[j])
7290 
          break;
7291 
 
7292 
      if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7293 
        {
7294 
          /* Nothing to save/restore.  */
7295 
          cfun_frame_layout.first_save_gpr = -1;
7296 
          cfun_frame_layout.first_restore_gpr = -1;
7297 
          cfun_frame_layout.last_save_gpr = -1;
7298 
          cfun_frame_layout.last_restore_gpr = -1;
7299 
        }
7300 
      else
7301 
        {
7302 
          /* Save / Restore from gpr i to j.  */
7303 
          cfun_frame_layout.first_save_gpr = i;
7304 
          cfun_frame_layout.first_restore_gpr = i;
7305 
          cfun_frame_layout.last_save_gpr = j;
7306 
          cfun_frame_layout.last_restore_gpr = j;
7307 
        }
7308 
    }
7309 
 
7310 
  if (cfun->stdarg)
7311 
    {
7312 
      /* Varargs functions need to save gprs 2 to 6.  */
7313 
      if (cfun->va_list_gpr_size
7314 
          && crtl->args.info.gprs < GP_ARG_NUM_REG)
7315 
        {
7316 
          int min_gpr = crtl->args.info.gprs;
7317 
          int max_gpr = min_gpr + cfun->va_list_gpr_size;
7318 
          if (max_gpr > GP_ARG_NUM_REG)
7319 
            max_gpr = GP_ARG_NUM_REG;
7320 
 
7321 
          if (cfun_frame_layout.first_save_gpr == -1
7322 
              || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7323 
            {
7324 
              cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7325 
              cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7326 
            }
7327 
 
7328 
          if (cfun_frame_layout.last_save_gpr == -1
7329 
              || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7330 
            {
7331 
              cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7332 
              cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7333 
            }
7334 
        }
7335 
 
7336 
      /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved.  */
7337 
      if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7338 
          && crtl->args.info.fprs < FP_ARG_NUM_REG)
7339 
        {
7340 
          int min_fpr = crtl->args.info.fprs;
7341 
          int max_fpr = min_fpr + cfun->va_list_fpr_size;
7342 
          if (max_fpr > FP_ARG_NUM_REG)
7343 
            max_fpr = FP_ARG_NUM_REG;
7344 
 
7345 
          /* ??? This is currently required to ensure proper location
7346 
             of the fpr save slots within the va_list save area.  */
7347 
          if (TARGET_PACKED_STACK)
7348 
            min_fpr = 0;
7349 
 
7350 
          for (i = min_fpr; i < max_fpr; i++)
7351 
            cfun_set_fpr_bit (i);
7352 
        }
7353 
    }
7354 
 
7355 
  if (!TARGET_64BIT)
7356 
    for (i = 2; i < 4; i++)
7357 
      if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7358 
        cfun_set_fpr_bit (i);
7359 
}
7360 
 
7361 
/* Fill cfun->machine with info about frame of current function.  */
7362 
 
7363 
static void
7364 
s390_frame_info (void)
7365 
{
7366 
  int i;
7367 
 
7368 
  cfun_frame_layout.frame_size = get_frame_size ();
7369 
  if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7370 
    fatal_error ("total size of local variables exceeds architecture limit");
7371 
 
7372 
  if (!TARGET_PACKED_STACK)
7373 
    {
7374 
      cfun_frame_layout.backchain_offset = 0;
7375 
      cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7376 
      cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7377 
      cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7378 
      cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7379 
                                       * UNITS_PER_LONG);
7380 
    }
7381 
  else if (TARGET_BACKCHAIN) /* kernel stack layout */
7382 
    {
7383 
      cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7384 
                                            - UNITS_PER_LONG);
7385 
      cfun_frame_layout.gprs_offset
7386 
        = (cfun_frame_layout.backchain_offset
7387 
           - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7388 
           * UNITS_PER_LONG);
7389 
 
7390 
      if (TARGET_64BIT)
7391 
        {
7392 
          cfun_frame_layout.f4_offset
7393 
            = (cfun_frame_layout.gprs_offset
7394 
               - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7395 
 
7396 
          cfun_frame_layout.f0_offset
7397 
            = (cfun_frame_layout.f4_offset
7398 
               - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7399 
        }
7400 
      else
7401 
        {
7402 
          /* On 31 bit we have to care about alignment of the
7403 
             floating point regs to provide fastest access.  */
7404 
          cfun_frame_layout.f0_offset
7405 
            = ((cfun_frame_layout.gprs_offset
7406 
                & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7407 
               - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7408 
 
7409 
          cfun_frame_layout.f4_offset
7410 
            = (cfun_frame_layout.f0_offset
7411 
               - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7412 
        }
7413 
    }
7414 
  else /* no backchain */
7415 
    {
7416 
      cfun_frame_layout.f4_offset
7417 
        = (STACK_POINTER_OFFSET
7418 
           - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7419 
 
7420 
      cfun_frame_layout.f0_offset
7421 
        = (cfun_frame_layout.f4_offset
7422 
           - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7423 
 
7424 
      cfun_frame_layout.gprs_offset
7425 
        = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7426 
    }
7427 
 
7428 
  if (current_function_is_leaf
7429 
      && !TARGET_TPF_PROFILING
7430 
      && cfun_frame_layout.frame_size == 0
7431 
      && !cfun_save_high_fprs_p
7432 
      && !cfun->calls_alloca
7433 
      && !cfun->stdarg)
7434 
    return;
7435 
 
7436 
  if (!TARGET_PACKED_STACK)
7437 
    cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7438 
                                     + crtl->outgoing_args_size
7439 
                                     + cfun_frame_layout.high_fprs * 8);
7440 
  else
7441 
    {
7442 
      if (TARGET_BACKCHAIN)
7443 
        cfun_frame_layout.frame_size += UNITS_PER_LONG;
7444 
 
7445 
      /* No alignment trouble here because f8-f15 are only saved under
7446 
         64 bit.  */
7447 
      cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7448 
                                               cfun_frame_layout.f4_offset),
7449 
                                          cfun_frame_layout.gprs_offset)
7450 
                                     - cfun_frame_layout.high_fprs * 8);
7451 
 
7452 
      cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7453 
 
7454 
      for (i = 0; i < 8; i++)
7455 
        if (cfun_fpr_bit_p (i))
7456 
          cfun_frame_layout.frame_size += 8;
7457 
 
7458 
      cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7459 
 
7460 
      /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7461 
         the frame size to sustain 8 byte alignment of stack frames.  */
7462 
      cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7463 
                                       STACK_BOUNDARY / BITS_PER_UNIT - 1)
7464 
                                      & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7465 
 
7466 
      cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7467 
    }
7468 
}
7469 
 
7470 
/* Generate frame layout.  Fills in register and frame data for the current
7471 
   function in cfun->machine.  This routine can be called multiple times;
7472 
   it will re-do the complete frame layout every time.  */
7473 
 
7474 
static void
7475 
s390_init_frame_layout (void)
7476 
{
7477 
  HOST_WIDE_INT frame_size;
7478 
  int base_used;
7479 
  int clobbered_regs[16];
7480 
 
7481 
  /* On S/390 machines, we may need to perform branch splitting, which
7482 
     will require both base and return address register.  We have no
7483 
     choice but to assume we're going to need them until right at the
7484 
     end of the machine dependent reorg phase.  */
7485 
  if (!TARGET_CPU_ZARCH)
7486 
    cfun->machine->split_branches_pending_p = true;
7487 
 
7488 
  do
7489 
    {
7490 
      frame_size = cfun_frame_layout.frame_size;
7491 
 
7492 
      /* Try to predict whether we'll need the base register.  */
7493 
      base_used = cfun->machine->split_branches_pending_p
7494 
                  || crtl->uses_const_pool
7495 
                  || (!DISP_IN_RANGE (frame_size)
7496 
                      && !CONST_OK_FOR_K (frame_size));
7497 
 
7498 
      /* Decide which register to use as literal pool base.  In small
7499 
         leaf functions, try to use an unused call-clobbered register
7500 
         as base register to avoid save/restore overhead.  */
7501 
      if (!base_used)
7502 
        cfun->machine->base_reg = NULL_RTX;
7503 
      else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7504 
        cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7505 
      else
7506 
        cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7507 
 
7508 
      s390_register_info (clobbered_regs);
7509 
      s390_frame_info ();
7510 
    }
7511 
  while (frame_size != cfun_frame_layout.frame_size);
7512 
}
7513 
 
7514 
/* Update frame layout.  Recompute actual register save data based on
7515 
   current info and update regs_ever_live for the special registers.
7516 
   May be called multiple times, but may never cause *more* registers
7517 
   to be saved than s390_init_frame_layout allocated room for.  */
7518 
 
7519 
static void
7520 
s390_update_frame_layout (void)
7521 
{
7522 
  int clobbered_regs[16];
7523 
 
7524 
  s390_register_info (clobbered_regs);
7525 
 
7526 
  df_set_regs_ever_live (BASE_REGNUM,
7527 
                         clobbered_regs[BASE_REGNUM] ? true : false);
7528 
  df_set_regs_ever_live (RETURN_REGNUM,
7529 
                         clobbered_regs[RETURN_REGNUM] ? true : false);
7530 
  df_set_regs_ever_live (STACK_POINTER_REGNUM,
7531 
                         clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7532 
 
7533 
  if (cfun->machine->base_reg)
7534 
    df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7535 
}
7536 
 
7537 
/* Return true if it is legal to put a value with MODE into REGNO.  */
7538 
 
7539 
bool
7540 
s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7541 
{
7542 
  switch (REGNO_REG_CLASS (regno))
7543 
    {
7544 
    case FP_REGS:
7545 
      if (REGNO_PAIR_OK (regno, mode))
7546 
        {
7547 
          if (mode == SImode || mode == DImode)
7548 
            return true;
7549 
 
7550 
          if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7551 
            return true;
7552 
        }
7553 
      break;
7554 
    case ADDR_REGS:
7555 
      if (FRAME_REGNO_P (regno) && mode == Pmode)
7556 
        return true;
7557 
 
7558 
      /* fallthrough */
7559 
    case GENERAL_REGS:
7560 
      if (REGNO_PAIR_OK (regno, mode))
7561 
        {
7562 
          if (TARGET_ZARCH
7563 
              || (mode != TFmode && mode != TCmode && mode != TDmode))
7564 
            return true;
7565 
        }
7566 
      break;
7567 
    case CC_REGS:
7568 
      if (GET_MODE_CLASS (mode) == MODE_CC)
7569 
        return true;
7570 
      break;
7571 
    case ACCESS_REGS:
7572 
      if (REGNO_PAIR_OK (regno, mode))
7573 
        {
7574 
          if (mode == SImode || mode == Pmode)
7575 
            return true;
7576 
        }
7577 
      break;
7578 
    default:
7579 
      return false;
7580 
    }
7581 
 
7582 
  return false;
7583 
}
7584 
 
7585 
/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
7586 
 
7587 
bool
7588 
s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7589 
{
7590 
   /* Once we've decided upon a register to use as base register, it must
7591 
      no longer be used for any other purpose.  */
7592 
  if (cfun->machine->base_reg)
7593 
    if (REGNO (cfun->machine->base_reg) == old_reg
7594 
        || REGNO (cfun->machine->base_reg) == new_reg)
7595 
      return false;
7596 
 
7597 
  return true;
7598 
}
7599 
 
7600 
/* Maximum number of registers to represent a value of mode MODE
7601 
   in a register of class RCLASS.  */
7602 
 
7603 
int
7604 
s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7605 
{
7606 
  switch (rclass)
7607 
    {
7608 
    case FP_REGS:
7609 
      if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7610 
        return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7611 
      else
7612 
        return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7613 
    case ACCESS_REGS:
7614 
      return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7615 
    default:
7616 
      break;
7617 
    }
7618 
  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7619 
}
7620 
 
7621 
/* Return true if register FROM can be eliminated via register TO.  */
7622 
 
7623 
static bool
7624 
s390_can_eliminate (const int from, const int to)
7625 
{
7626 
  /* On zSeries machines, we have not marked the base register as fixed.
7627 
     Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7628 
     If a function requires the base register, we say here that this
7629 
     elimination cannot be performed.  This will cause reload to free
7630 
     up the base register (as if it were fixed).  On the other hand,
7631 
     if the current function does *not* require the base register, we
7632 
     say here the elimination succeeds, which in turn allows reload
7633 
     to allocate the base register for any other purpose.  */
7634 
  if (from == BASE_REGNUM && to == BASE_REGNUM)
7635 
    {
7636 
      if (TARGET_CPU_ZARCH)
7637 
        {
7638 
          s390_init_frame_layout ();
7639 
          return cfun->machine->base_reg == NULL_RTX;
7640 
        }
7641 
 
7642 
      return false;
7643 
    }
7644 
 
7645 
  /* Everything else must point into the stack frame.  */
7646 
  gcc_assert (to == STACK_POINTER_REGNUM
7647 
              || to == HARD_FRAME_POINTER_REGNUM);
7648 
 
7649 
  gcc_assert (from == FRAME_POINTER_REGNUM
7650 
              || from == ARG_POINTER_REGNUM
7651 
              || from == RETURN_ADDRESS_POINTER_REGNUM);
7652 
 
7653 
  /* Make sure we actually saved the return address.  */
7654 
  if (from == RETURN_ADDRESS_POINTER_REGNUM)
7655 
    if (!crtl->calls_eh_return
7656 
        && !cfun->stdarg
7657 
        && !cfun_frame_layout.save_return_addr_p)
7658 
      return false;
7659 
 
7660 
  return true;
7661 
}
7662 
 
7663 
/* Return offset between register FROM and TO initially after prolog.  */
7664 
 
7665 
HOST_WIDE_INT
7666 
s390_initial_elimination_offset (int from, int to)
7667 
{
7668 
  HOST_WIDE_INT offset;
7669 
  int index;
7670 
 
7671 
  /* ??? Why are we called for non-eliminable pairs?  */
7672 
  if (!s390_can_eliminate (from, to))
7673 
    return 0;
7674 
 
7675 
  switch (from)
7676 
    {
7677 
    case FRAME_POINTER_REGNUM:
7678 
      offset = (get_frame_size()
7679 
                + STACK_POINTER_OFFSET
7680 
                + crtl->outgoing_args_size);
7681 
      break;
7682 
 
7683 
    case ARG_POINTER_REGNUM:
7684 
      s390_init_frame_layout ();
7685 
      offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7686 
      break;
7687 
 
7688 
    case RETURN_ADDRESS_POINTER_REGNUM:
7689 
      s390_init_frame_layout ();
7690 
      index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7691 
      gcc_assert (index >= 0);
7692 
      offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7693 
      offset += index * UNITS_PER_LONG;
7694 
      break;
7695 
 
7696 
    case BASE_REGNUM:
7697 
      offset = 0;
7698 
      break;
7699 
 
7700 
    default:
7701 
      gcc_unreachable ();
7702 
    }
7703 
 
7704 
  return offset;
7705 
}
7706 
 
7707 
/* Emit insn to save fpr REGNUM at offset OFFSET relative
7708 
   to register BASE.  Return generated insn.  */
7709 
 
7710 
static rtx
7711 
save_fpr (rtx base, int offset, int regnum)
7712 
{
7713 
  rtx addr;
7714 
  addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7715 
 
7716 
  if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7717 
    set_mem_alias_set (addr, get_varargs_alias_set ());
7718 
  else
7719 
    set_mem_alias_set (addr, get_frame_alias_set ());
7720 
 
7721 
  return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7722 
}
7723 
 
7724 
/* Emit insn to restore fpr REGNUM from offset OFFSET relative
7725 
   to register BASE.  Return generated insn.  */
7726 
 
7727 
static rtx
7728 
restore_fpr (rtx base, int offset, int regnum)
7729 
{
7730 
  rtx addr;
7731 
  addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7732 
  set_mem_alias_set (addr, get_frame_alias_set ());
7733 
 
7734 
  return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7735 
}
7736 
 
7737 
/* Return true if REGNO is a global register, but not one
7738 
   of the special ones that need to be saved/restored in anyway.  */
7739 
 
7740 
static inline bool
7741 
global_not_special_regno_p (int regno)
7742 
{
7743 
  return (global_regs[regno]
7744 
          /* These registers are special and need to be
7745 
             restored in any case.  */
7746 
          && !(regno == STACK_POINTER_REGNUM
7747 
               || regno == RETURN_REGNUM
7748 
               || regno == BASE_REGNUM
7749 
               || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7750 
}
7751 
 
7752 
/* Generate insn to save registers FIRST to LAST into
7753 
   the register save area located at offset OFFSET
7754 
   relative to register BASE.  */
7755 
 
7756 
static rtx
7757 
save_gprs (rtx base, int offset, int first, int last)
7758 
{
7759 
  rtx addr, insn, note;
7760 
  int i;
7761 
 
7762 
  addr = plus_constant (base, offset);
7763 
  addr = gen_rtx_MEM (Pmode, addr);
7764 
 
7765 
  set_mem_alias_set (addr, get_frame_alias_set ());
7766 
 
7767 
  /* Special-case single register.  */
7768 
  if (first == last)
7769 
    {
7770 
      if (TARGET_64BIT)
7771 
        insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7772 
      else
7773 
        insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7774 
 
7775 
      if (!global_not_special_regno_p (first))
7776 
        RTX_FRAME_RELATED_P (insn) = 1;
7777 
      return insn;
7778 
    }
7779 
 
7780 
 
7781 
  insn = gen_store_multiple (addr,
7782 
                             gen_rtx_REG (Pmode, first),
7783 
                             GEN_INT (last - first + 1));
7784 
 
7785 
  if (first <= 6 && cfun->stdarg)
7786 
    for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7787 
      {
7788 
        rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7789 
 
7790 
        if (first + i <= 6)
7791 
          set_mem_alias_set (mem, get_varargs_alias_set ());
7792 
      }
7793 
 
7794 
  /* We need to set the FRAME_RELATED flag on all SETs
7795 
     inside the store-multiple pattern.
7796 
 
7797 
     However, we must not emit DWARF records for registers 2..5
7798 
     if they are stored for use by variable arguments ...
7799 
 
7800 
     ??? Unfortunately, it is not enough to simply not the
7801 
     FRAME_RELATED flags for those SETs, because the first SET
7802 
     of the PARALLEL is always treated as if it had the flag
7803 
     set, even if it does not.  Therefore we emit a new pattern
7804 
     without those registers as REG_FRAME_RELATED_EXPR note.  */
7805 
 
7806 
  if (first >= 6 && !global_not_special_regno_p (first))
7807 
    {
7808 
      rtx pat = PATTERN (insn);
7809 
 
7810 
      for (i = 0; i < XVECLEN (pat, 0); i++)
7811 
        if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7812 
            && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7813 
                                                                     0, i)))))
7814 
          RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7815 
 
7816 
      RTX_FRAME_RELATED_P (insn) = 1;
7817 
    }
7818 
  else if (last >= 6)
7819 
    {
7820 
      int start;
7821 
 
7822 
      for (start = first >= 6 ? first : 6; start <= last; start++)
7823 
        if (!global_not_special_regno_p (start))
7824 
          break;
7825 
 
7826 
      if (start > last)
7827 
        return insn;
7828 
 
7829 
      addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
7830 
      note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7831 
                                 gen_rtx_REG (Pmode, start),
7832 
                                 GEN_INT (last - start + 1));
7833 
      note = PATTERN (note);
7834 
 
7835 
      add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7836 
 
7837 
      for (i = 0; i < XVECLEN (note, 0); i++)
7838 
        if (GET_CODE (XVECEXP (note, 0, i)) == SET
7839 
            && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7840 
                                                                     0, i)))))
7841 
          RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7842 
 
7843 
      RTX_FRAME_RELATED_P (insn) = 1;
7844 
    }
7845 
 
7846 
  return insn;
7847 
}
7848 
 
7849 
/* Generate insn to restore registers FIRST to LAST from
7850 
   the register save area located at offset OFFSET
7851 
   relative to register BASE.  */
7852 
 
7853 
static rtx
7854 
restore_gprs (rtx base, int offset, int first, int last)
7855 
{
7856 
  rtx addr, insn;
7857 
 
7858 
  addr = plus_constant (base, offset);
7859 
  addr = gen_rtx_MEM (Pmode, addr);
7860 
  set_mem_alias_set (addr, get_frame_alias_set ());
7861 
 
7862 
  /* Special-case single register.  */
7863 
  if (first == last)
7864 
    {
7865 
      if (TARGET_64BIT)
7866 
        insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7867 
      else
7868 
        insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7869 
 
7870 
      return insn;
7871 
    }
7872 
 
7873 
  insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7874 
                            addr,
7875 
                            GEN_INT (last - first + 1));
7876 
  return insn;
7877 
}
7878 
 
7879 
/* Return insn sequence to load the GOT register.  */
7880 
 
7881 
static GTY(()) rtx got_symbol;
7882 
rtx
7883 
s390_load_got (void)
7884 
{
7885 
  rtx insns;
7886 
 
7887 
  /* We cannot use pic_offset_table_rtx here since we use this
7888 
     function also for non-pic if __tls_get_offset is called and in
7889 
     that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
7890 
     aren't usable.  */
7891 
  rtx got_rtx = gen_rtx_REG (Pmode, 12);
7892 
 
7893 
  if (!got_symbol)
7894 
    {
7895 
      got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7896 
      SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7897 
    }
7898 
 
7899 
  start_sequence ();
7900 
 
7901 
  if (TARGET_CPU_ZARCH)
7902 
    {
7903 
      emit_move_insn (got_rtx, got_symbol);
7904 
    }
7905 
  else
7906 
    {
7907 
      rtx offset;
7908 
 
7909 
      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7910 
                               UNSPEC_LTREL_OFFSET);
7911 
      offset = gen_rtx_CONST (Pmode, offset);
7912 
      offset = force_const_mem (Pmode, offset);
7913 
 
7914 
      emit_move_insn (got_rtx, offset);
7915 
 
7916 
      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7917 
                               UNSPEC_LTREL_BASE);
7918 
      offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
7919 
 
7920 
      emit_move_insn (got_rtx, offset);
7921 
    }
7922 
 
7923 
  insns = get_insns ();
7924 
  end_sequence ();
7925 
  return insns;
7926 
}
7927 
 
7928 
/* This ties together stack memory (MEM with an alias set of frame_alias_set)
7929 
   and the change to the stack pointer.  */
7930 
 
7931 
static void
7932 
s390_emit_stack_tie (void)
7933 
{
7934 
  rtx mem = gen_frame_mem (BLKmode,
7935 
                           gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7936 
 
7937 
  emit_insn (gen_stack_tie (mem));
7938 
}
7939 
 
7940 
/* Expand the prologue into a bunch of separate insns.  */
7941 
 
7942 
void
7943 
s390_emit_prologue (void)
7944 
{
7945 
  rtx insn, addr;
7946 
  rtx temp_reg;
7947 
  int i;
7948 
  int offset;
7949 
  int next_fpr = 0;
7950 
 
7951 
  /* Complete frame layout.  */
7952 
 
7953 
  s390_update_frame_layout ();
7954 
 
7955 
  /* Annotate all constant pool references to let the scheduler know
7956 
     they implicitly use the base register.  */
7957 
 
7958 
  push_topmost_sequence ();
7959 
 
7960 
  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7961 
    if (INSN_P (insn))
7962 
      {
7963 
        annotate_constant_pool_refs (&PATTERN (insn));
7964 
        df_insn_rescan (insn);
7965 
      }
7966 
 
7967 
  pop_topmost_sequence ();
7968 
 
7969 
  /* Choose best register to use for temp use within prologue.
7970 
     See below for why TPF must use the register 1.  */
7971 
 
7972 
  if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7973 
      && !current_function_is_leaf
7974 
      && !TARGET_TPF_PROFILING)
7975 
    temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7976 
  else
7977 
    temp_reg = gen_rtx_REG (Pmode, 1);
7978 
 
7979 
  /* Save call saved gprs.  */
7980 
  if (cfun_frame_layout.first_save_gpr != -1)
7981 
    {
7982 
      insn = save_gprs (stack_pointer_rtx,
7983 
                        cfun_frame_layout.gprs_offset +
7984 
                        UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
7985 
                                          - cfun_frame_layout.first_save_gpr_slot),
7986 
                        cfun_frame_layout.first_save_gpr,
7987 
                        cfun_frame_layout.last_save_gpr);
7988 
      emit_insn (insn);
7989 
    }
7990 
 
7991 
  /* Dummy insn to mark literal pool slot.  */
7992 
 
7993 
  if (cfun->machine->base_reg)
7994 
    emit_insn (gen_main_pool (cfun->machine->base_reg));
7995 
 
7996 
  offset = cfun_frame_layout.f0_offset;
7997 
 
7998 
  /* Save f0 and f2.  */
7999 
  for (i = 0; i < 2; i++)
8000 
    {
8001 
      if (cfun_fpr_bit_p (i))
8002 
        {
8003 
          save_fpr (stack_pointer_rtx, offset, i + 16);
8004 
          offset += 8;
8005 
        }
8006 
      else if (!TARGET_PACKED_STACK)
8007 
          offset += 8;
8008 
    }
8009 
 
8010 
  /* Save f4 and f6.  */
8011 
  offset = cfun_frame_layout.f4_offset;
8012 
  for (i = 2; i < 4; i++)
8013 
    {
8014 
      if (cfun_fpr_bit_p (i))
8015 
        {
8016 
          insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8017 
          offset += 8;
8018 
 
8019 
          /* If f4 and f6 are call clobbered they are saved due to stdargs and
8020 
             therefore are not frame related.  */
8021 
          if (!call_really_used_regs[i + 16])
8022 
            RTX_FRAME_RELATED_P (insn) = 1;
8023 
        }
8024 
      else if (!TARGET_PACKED_STACK)
8025 
        offset += 8;
8026 
    }
8027 
 
8028 
  if (TARGET_PACKED_STACK
8029 
      && cfun_save_high_fprs_p
8030 
      && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8031 
    {
8032 
      offset = (cfun_frame_layout.f8_offset
8033 
                + (cfun_frame_layout.high_fprs - 1) * 8);
8034 
 
8035 
      for (i = 15; i > 7 && offset >= 0; i--)
8036 
        if (cfun_fpr_bit_p (i))
8037 
          {
8038 
            insn = save_fpr (stack_pointer_rtx, offset, i + 16);
8039 
 
8040 
            RTX_FRAME_RELATED_P (insn) = 1;
8041 
            offset -= 8;
8042 
          }
8043 
      if (offset >= cfun_frame_layout.f8_offset)
8044 
        next_fpr = i + 16;
8045 
    }
8046 
 
8047 
  if (!TARGET_PACKED_STACK)
8048 
    next_fpr = cfun_save_high_fprs_p ? 31 : 0;
8049 
 
8050 
  if (flag_stack_usage_info)
8051 
    current_function_static_stack_size = cfun_frame_layout.frame_size;
8052 
 
8053 
  /* Decrement stack pointer.  */
8054 
 
8055 
  if (cfun_frame_layout.frame_size > 0)
8056 
    {
8057 
      rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8058 
      rtx real_frame_off;
8059 
 
8060 
      if (s390_stack_size)
8061 
        {
8062 
          HOST_WIDE_INT stack_guard;
8063 
 
8064 
          if (s390_stack_guard)
8065 
            stack_guard = s390_stack_guard;
8066 
          else
8067 
            {
8068 
              /* If no value for stack guard is provided the smallest power of 2
8069 
                 larger than the current frame size is chosen.  */
8070 
              stack_guard = 1;
8071 
              while (stack_guard < cfun_frame_layout.frame_size)
8072 
                stack_guard <<= 1;
8073 
            }
8074 
 
8075 
          if (cfun_frame_layout.frame_size >= s390_stack_size)
8076 
            {
8077 
              warning (0, "frame size of function %qs is %wd"
8078 
                       " bytes exceeding user provided stack limit of "
8079 
                       "%d bytes.  "
8080 
                       "An unconditional trap is added.",
8081 
                       current_function_name(), cfun_frame_layout.frame_size,
8082 
                       s390_stack_size);
8083 
              emit_insn (gen_trap ());
8084 
            }
8085 
          else
8086 
            {
8087 
              /* stack_guard has to be smaller than s390_stack_size.
8088 
                 Otherwise we would emit an AND with zero which would
8089 
                 not match the test under mask pattern.  */
8090 
              if (stack_guard >= s390_stack_size)
8091 
                {
8092 
                  warning (0, "frame size of function %qs is %wd"
8093 
                           " bytes which is more than half the stack size. "
8094 
                           "The dynamic check would not be reliable. "
8095 
                           "No check emitted for this function.",
8096 
                           current_function_name(),
8097 
                           cfun_frame_layout.frame_size);
8098 
                }
8099 
              else
8100 
                {
8101 
                  HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8102 
                                                    & ~(stack_guard - 1));
8103 
 
8104 
                  rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8105 
                                       GEN_INT (stack_check_mask));
8106 
                  if (TARGET_64BIT)
8107 
                    emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8108 
                                                         t, const0_rtx),
8109 
                                             t, const0_rtx, const0_rtx));
8110 
                  else
8111 
                    emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8112 
                                                         t, const0_rtx),
8113 
                                             t, const0_rtx, const0_rtx));
8114 
                }
8115 
            }
8116 
        }
8117 
 
8118 
      if (s390_warn_framesize > 0
8119 
          && cfun_frame_layout.frame_size >= s390_warn_framesize)
8120 
        warning (0, "frame size of %qs is %wd bytes",
8121 
                 current_function_name (), cfun_frame_layout.frame_size);
8122 
 
8123 
      if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8124 
        warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8125 
 
8126 
      /* Save incoming stack pointer into temp reg.  */
8127 
      if (TARGET_BACKCHAIN || next_fpr)
8128 
        insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8129 
 
8130 
      /* Subtract frame size from stack pointer.  */
8131 
 
8132 
      if (DISP_IN_RANGE (INTVAL (frame_off)))
8133 
        {
8134 
          insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8135 
                              gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8136 
                                            frame_off));
8137 
          insn = emit_insn (insn);
8138 
        }
8139 
      else
8140 
        {
8141 
          if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8142 
            frame_off = force_const_mem (Pmode, frame_off);
8143 
 
8144 
          insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8145 
          annotate_constant_pool_refs (&PATTERN (insn));
8146 
        }
8147 
 
8148 
      RTX_FRAME_RELATED_P (insn) = 1;
8149 
      real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8150 
      add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8151 
                    gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8152 
                                 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8153 
                                               real_frame_off)));
8154 
 
8155 
      /* Set backchain.  */
8156 
 
8157 
      if (TARGET_BACKCHAIN)
8158 
        {
8159 
          if (cfun_frame_layout.backchain_offset)
8160 
            addr = gen_rtx_MEM (Pmode,
8161 
                                plus_constant (stack_pointer_rtx,
8162 
                                  cfun_frame_layout.backchain_offset));
8163 
          else
8164 
            addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8165 
          set_mem_alias_set (addr, get_frame_alias_set ());
8166 
          insn = emit_insn (gen_move_insn (addr, temp_reg));
8167 
        }
8168 
 
8169 
      /* If we support non-call exceptions (e.g. for Java),
8170 
         we need to make sure the backchain pointer is set up
8171 
         before any possibly trapping memory access.  */
8172 
      if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8173 
        {
8174 
          addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8175 
          emit_clobber (addr);
8176 
        }
8177 
    }
8178 
 
8179 
  /* Save fprs 8 - 15 (64 bit ABI).  */
8180 
 
8181 
  if (cfun_save_high_fprs_p && next_fpr)
8182 
    {
8183 
      /* If the stack might be accessed through a different register
8184 
         we have to make sure that the stack pointer decrement is not
8185 
         moved below the use of the stack slots.  */
8186 
      s390_emit_stack_tie ();
8187 
 
8188 
      insn = emit_insn (gen_add2_insn (temp_reg,
8189 
                                       GEN_INT (cfun_frame_layout.f8_offset)));
8190 
 
8191 
      offset = 0;
8192 
 
8193 
      for (i = 24; i <= next_fpr; i++)
8194 
        if (cfun_fpr_bit_p (i - 16))
8195 
          {
8196 
            rtx addr = plus_constant (stack_pointer_rtx,
8197 
                                      cfun_frame_layout.frame_size
8198 
                                      + cfun_frame_layout.f8_offset
8199 
                                      + offset);
8200 
 
8201 
            insn = save_fpr (temp_reg, offset, i);
8202 
            offset += 8;
8203 
            RTX_FRAME_RELATED_P (insn) = 1;
8204 
            add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8205 
                          gen_rtx_SET (VOIDmode,
8206 
                                       gen_rtx_MEM (DFmode, addr),
8207 
                                       gen_rtx_REG (DFmode, i)));
8208 
          }
8209 
    }
8210 
 
8211 
  /* Set frame pointer, if needed.  */
8212 
 
8213 
  if (frame_pointer_needed)
8214 
    {
8215 
      insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8216 
      RTX_FRAME_RELATED_P (insn) = 1;
8217 
    }
8218 
 
8219 
  /* Set up got pointer, if needed.  */
8220 
 
8221 
  if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8222 
    {
8223 
      rtx insns = s390_load_got ();
8224 
 
8225 
      for (insn = insns; insn; insn = NEXT_INSN (insn))
8226 
        annotate_constant_pool_refs (&PATTERN (insn));
8227 
 
8228 
      emit_insn (insns);
8229 
    }
8230 
 
8231 
  if (TARGET_TPF_PROFILING)
8232 
    {
8233 
      /* Generate a BAS instruction to serve as a function
8234 
         entry intercept to facilitate the use of tracing
8235 
         algorithms located at the branch target.  */
8236 
      emit_insn (gen_prologue_tpf ());
8237 
 
8238 
      /* Emit a blockage here so that all code
8239 
         lies between the profiling mechanisms.  */
8240 
      emit_insn (gen_blockage ());
8241 
    }
8242 
}
8243 
 
8244 
/* Expand the epilogue into a bunch of separate insns.  */
8245 
 
8246 
void
8247 
s390_emit_epilogue (bool sibcall)
8248 
{
8249 
  rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8250 
  int area_bottom, area_top, offset = 0;
8251 
  int next_offset;
8252 
  rtvec p;
8253 
  int i;
8254 
 
8255 
  if (TARGET_TPF_PROFILING)
8256 
    {
8257 
 
8258 
      /* Generate a BAS instruction to serve as a function
8259 
         entry intercept to facilitate the use of tracing
8260 
         algorithms located at the branch target.  */
8261 
 
8262 
      /* Emit a blockage here so that all code
8263 
         lies between the profiling mechanisms.  */
8264 
      emit_insn (gen_blockage ());
8265 
 
8266 
      emit_insn (gen_epilogue_tpf ());
8267 
    }
8268 
 
8269 
  /* Check whether to use frame or stack pointer for restore.  */
8270 
 
8271 
  frame_pointer = (frame_pointer_needed
8272 
                   ? hard_frame_pointer_rtx : stack_pointer_rtx);
8273 
 
8274 
  s390_frame_area (&area_bottom, &area_top);
8275 
 
8276 
  /* Check whether we can access the register save area.
8277 
     If not, increment the frame pointer as required.  */
8278 
 
8279 
  if (area_top <= area_bottom)
8280 
    {
8281 
      /* Nothing to restore.  */
8282 
    }
8283 
  else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8284 
           && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8285 
    {
8286 
      /* Area is in range.  */
8287 
      offset = cfun_frame_layout.frame_size;
8288 
    }
8289 
  else
8290 
    {
8291 
      rtx insn, frame_off, cfa;
8292 
 
8293 
      offset = area_bottom < 0 ? -area_bottom : 0;
8294 
      frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8295 
 
8296 
      cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8297 
                         gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8298 
      if (DISP_IN_RANGE (INTVAL (frame_off)))
8299 
        {
8300 
          insn = gen_rtx_SET (VOIDmode, frame_pointer,
8301 
                              gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8302 
          insn = emit_insn (insn);
8303 
        }
8304 
      else
8305 
        {
8306 
          if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8307 
            frame_off = force_const_mem (Pmode, frame_off);
8308 
 
8309 
          insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8310 
          annotate_constant_pool_refs (&PATTERN (insn));
8311 
        }
8312 
      add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8313 
      RTX_FRAME_RELATED_P (insn) = 1;
8314 
    }
8315 
 
8316 
  /* Restore call saved fprs.  */
8317 
 
8318 
  if (TARGET_64BIT)
8319 
    {
8320 
      if (cfun_save_high_fprs_p)
8321 
        {
8322 
          next_offset = cfun_frame_layout.f8_offset;
8323 
          for (i = 24; i < 32; i++)
8324 
            {
8325 
              if (cfun_fpr_bit_p (i - 16))
8326 
                {
8327 
                  restore_fpr (frame_pointer,
8328 
                               offset + next_offset, i);
8329 
                  cfa_restores
8330 
                    = alloc_reg_note (REG_CFA_RESTORE,
8331 
                                      gen_rtx_REG (DFmode, i), cfa_restores);
8332 
                  next_offset += 8;
8333 
                }
8334 
            }
8335 
        }
8336 
 
8337 
    }
8338 
  else
8339 
    {
8340 
      next_offset = cfun_frame_layout.f4_offset;
8341 
      for (i = 18; i < 20; i++)
8342 
        {
8343 
          if (cfun_fpr_bit_p (i - 16))
8344 
            {
8345 
              restore_fpr (frame_pointer,
8346 
                           offset + next_offset, i);
8347 
              cfa_restores
8348 
                = alloc_reg_note (REG_CFA_RESTORE,
8349 
                                  gen_rtx_REG (DFmode, i), cfa_restores);
8350 
              next_offset += 8;
8351 
            }
8352 
          else if (!TARGET_PACKED_STACK)
8353 
            next_offset += 8;
8354 
        }
8355 
 
8356 
    }
8357 
 
8358 
  /* Return register.  */
8359 
 
8360 
  return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8361 
 
8362 
  /* Restore call saved gprs.  */
8363 
 
8364 
  if (cfun_frame_layout.first_restore_gpr != -1)
8365 
    {
8366 
      rtx insn, addr;
8367 
      int i;
8368 
 
8369 
      /* Check for global register and save them
8370 
         to stack location from where they get restored.  */
8371 
 
8372 
      for (i = cfun_frame_layout.first_restore_gpr;
8373 
           i <= cfun_frame_layout.last_restore_gpr;
8374 
           i++)
8375 
        {
8376 
          if (global_not_special_regno_p (i))
8377 
            {
8378 
              addr = plus_constant (frame_pointer,
8379 
                                    offset + cfun_frame_layout.gprs_offset
8380 
                                    + (i - cfun_frame_layout.first_save_gpr_slot)
8381 
                                    * UNITS_PER_LONG);
8382 
              addr = gen_rtx_MEM (Pmode, addr);
8383 
              set_mem_alias_set (addr, get_frame_alias_set ());
8384 
              emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8385 
            }
8386 
          else
8387 
            cfa_restores
8388 
              = alloc_reg_note (REG_CFA_RESTORE,
8389 
                                gen_rtx_REG (Pmode, i), cfa_restores);
8390 
        }
8391 
 
8392 
      if (! sibcall)
8393 
        {
8394 
          /* Fetch return address from stack before load multiple,
8395 
             this will do good for scheduling.  */
8396 
 
8397 
          if (cfun_frame_layout.save_return_addr_p
8398 
              || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8399 
                  && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8400 
            {
8401 
              int return_regnum = find_unused_clobbered_reg();
8402 
              if (!return_regnum)
8403 
                return_regnum = 4;
8404 
              return_reg = gen_rtx_REG (Pmode, return_regnum);
8405 
 
8406 
              addr = plus_constant (frame_pointer,
8407 
                                    offset + cfun_frame_layout.gprs_offset
8408 
                                    + (RETURN_REGNUM
8409 
                                       - cfun_frame_layout.first_save_gpr_slot)
8410 
                                    * UNITS_PER_LONG);
8411 
              addr = gen_rtx_MEM (Pmode, addr);
8412 
              set_mem_alias_set (addr, get_frame_alias_set ());
8413 
              emit_move_insn (return_reg, addr);
8414 
            }
8415 
        }
8416 
 
8417 
      insn = restore_gprs (frame_pointer,
8418 
                           offset + cfun_frame_layout.gprs_offset
8419 
                           + (cfun_frame_layout.first_restore_gpr
8420 
                              - cfun_frame_layout.first_save_gpr_slot)
8421 
                           * UNITS_PER_LONG,
8422 
                           cfun_frame_layout.first_restore_gpr,
8423 
                           cfun_frame_layout.last_restore_gpr);
8424 
      insn = emit_insn (insn);
8425 
      REG_NOTES (insn) = cfa_restores;
8426 
      add_reg_note (insn, REG_CFA_DEF_CFA,
8427 
                    plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8428 
      RTX_FRAME_RELATED_P (insn) = 1;
8429 
    }
8430 
 
8431 
  if (! sibcall)
8432 
    {
8433 
 
8434 
      /* Return to caller.  */
8435 
 
8436 
      p = rtvec_alloc (2);
8437 
 
8438 
      RTVEC_ELT (p, 0) = ret_rtx;
8439 
      RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8440 
      emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8441 
    }
8442 
}
8443 
 
8444 
 
8445 
/* Return the size in bytes of a function argument of
8446 
   type TYPE and/or mode MODE.  At least one of TYPE or
8447 
   MODE must be specified.  */
8448 
 
8449 
static int
8450 
s390_function_arg_size (enum machine_mode mode, const_tree type)
8451 
{
8452 
  if (type)
8453 
    return int_size_in_bytes (type);
8454 
 
8455 
  /* No type info available for some library calls ...  */
8456 
  if (mode != BLKmode)
8457 
    return GET_MODE_SIZE (mode);
8458 
 
8459 
  /* If we have neither type nor mode, abort */
8460 
  gcc_unreachable ();
8461 
}
8462 
 
8463 
/* Return true if a function argument of type TYPE and mode MODE
8464 
   is to be passed in a floating-point register, if available.  */
8465 
 
8466 
static bool
8467 
s390_function_arg_float (enum machine_mode mode, const_tree type)
8468 
{
8469 
  int size = s390_function_arg_size (mode, type);
8470 
  if (size > 8)
8471 
    return false;
8472 
 
8473 
  /* Soft-float changes the ABI: no floating-point registers are used.  */
8474 
  if (TARGET_SOFT_FLOAT)
8475 
    return false;
8476 
 
8477 
  /* No type info available for some library calls ...  */
8478 
  if (!type)
8479 
    return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8480 
 
8481 
  /* The ABI says that record types with a single member are treated
8482 
     just like that member would be.  */
8483 
  while (TREE_CODE (type) == RECORD_TYPE)
8484 
    {
8485 
      tree field, single = NULL_TREE;
8486 
 
8487 
      for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
8488 
        {
8489 
          if (TREE_CODE (field) != FIELD_DECL)
8490 
            continue;
8491 
 
8492 
          if (single == NULL_TREE)
8493 
            single = TREE_TYPE (field);
8494 
          else
8495 
            return false;
8496 
        }
8497 
 
8498 
      if (single == NULL_TREE)
8499 
        return false;
8500 
      else
8501 
        type = single;
8502 
    }
8503 
 
8504 
  return TREE_CODE (type) == REAL_TYPE;
8505 
}
8506 
 
8507 
/* Return true if a function argument of type TYPE and mode MODE
8508 
   is to be passed in an integer register, or a pair of integer
8509 
   registers, if available.  */
8510 
 
8511 
static bool
8512 
s390_function_arg_integer (enum machine_mode mode, const_tree type)
8513 
{
8514 
  int size = s390_function_arg_size (mode, type);
8515 
  if (size > 8)
8516 
    return false;
8517 
 
8518 
  /* No type info available for some library calls ...  */
8519 
  if (!type)
8520 
    return GET_MODE_CLASS (mode) == MODE_INT
8521 
           || (TARGET_SOFT_FLOAT &&  SCALAR_FLOAT_MODE_P (mode));
8522 
 
8523 
  /* We accept small integral (and similar) types.  */
8524 
  if (INTEGRAL_TYPE_P (type)
8525 
      || POINTER_TYPE_P (type)
8526 
      || TREE_CODE (type) == NULLPTR_TYPE
8527 
      || TREE_CODE (type) == OFFSET_TYPE
8528 
      || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8529 
    return true;
8530 
 
8531 
  /* We also accept structs of size 1, 2, 4, 8 that are not
8532 
     passed in floating-point registers.  */
8533 
  if (AGGREGATE_TYPE_P (type)
8534 
      && exact_log2 (size) >= 0
8535 
      && !s390_function_arg_float (mode, type))
8536 
    return true;
8537 
 
8538 
  return false;
8539 
}
8540 
 
8541 
/* Return 1 if a function argument of type TYPE and mode MODE
8542 
   is to be passed by reference.  The ABI specifies that only
8543 
   structures of size 1, 2, 4, or 8 bytes are passed by value,
8544 
   all other structures (and complex numbers) are passed by
8545 
   reference.  */
8546 
 
8547 
static bool
8548 
s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
8549 
                        enum machine_mode mode, const_tree type,
8550 
                        bool named ATTRIBUTE_UNUSED)
8551 
{
8552 
  int size = s390_function_arg_size (mode, type);
8553 
  if (size > 8)
8554 
    return true;
8555 
 
8556 
  if (type)
8557 
    {
8558 
      if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8559 
        return 1;
8560 
 
8561 
      if (TREE_CODE (type) == COMPLEX_TYPE
8562 
          || TREE_CODE (type) == VECTOR_TYPE)
8563 
        return 1;
8564 
    }
8565 
 
8566 
  return 0;
8567 
}
8568 
 
8569 
/* Update the data in CUM to advance over an argument of mode MODE and
8570 
   data type TYPE.  (TYPE is null for libcalls where that information
8571 
   may not be available.).  The boolean NAMED specifies whether the
8572 
   argument is a named argument (as opposed to an unnamed argument
8573 
   matching an ellipsis).  */
8574 
 
8575 
static void
8576 
s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
8577 
                           const_tree type, bool named ATTRIBUTE_UNUSED)
8578 
{
8579 
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8580 
 
8581 
  if (s390_function_arg_float (mode, type))
8582 
    {
8583 
      cum->fprs += 1;
8584 
    }
8585 
  else if (s390_function_arg_integer (mode, type))
8586 
    {
8587 
      int size = s390_function_arg_size (mode, type);
8588 
      cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
8589 
    }
8590 
  else
8591 
    gcc_unreachable ();
8592 
}
8593 
 
8594 
/* Define where to put the arguments to a function.
8595 
   Value is zero to push the argument on the stack,
8596 
   or a hard register in which to store the argument.
8597 
 
8598 
   MODE is the argument's machine mode.
8599 
   TYPE is the data type of the argument (as a tree).
8600 
    This is null for libcalls where that information may
8601 
    not be available.
8602 
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
8603 
    the preceding args and about the function being called.
8604 
   NAMED is nonzero if this argument is a named parameter
8605 
    (otherwise it is an extra parameter matching an ellipsis).
8606 
 
8607 
   On S/390, we use general purpose registers 2 through 6 to
8608 
   pass integer, pointer, and certain structure arguments, and
8609 
   floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8610 
   to pass floating point arguments.  All remaining arguments
8611 
   are pushed to the stack.  */
8612 
 
8613 
static rtx
8614 
s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8615 
                   const_tree type, bool named ATTRIBUTE_UNUSED)
8616 
{
8617 
  CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8618 
 
8619 
  if (s390_function_arg_float (mode, type))
8620 
    {
8621 
      if (cum->fprs + 1 > FP_ARG_NUM_REG)
8622 
        return 0;
8623 
      else
8624 
        return gen_rtx_REG (mode, cum->fprs + 16);
8625 
    }
8626 
  else if (s390_function_arg_integer (mode, type))
8627 
    {
8628 
      int size = s390_function_arg_size (mode, type);
8629 
      int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
8630 
 
8631 
      if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8632 
        return 0;
8633 
      else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
8634 
        return gen_rtx_REG (mode, cum->gprs + 2);
8635 
      else if (n_gprs == 2)
8636 
        {
8637 
          rtvec p = rtvec_alloc (2);
8638 
 
8639 
          RTVEC_ELT (p, 0)
8640 
            = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
8641 
                                         const0_rtx);
8642 
          RTVEC_ELT (p, 1)
8643 
            = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
8644 
                                         GEN_INT (4));
8645 
 
8646 
          return gen_rtx_PARALLEL (mode, p);
8647 
        }
8648 
    }
8649 
 
8650 
  /* After the real arguments, expand_call calls us once again
8651 
     with a void_type_node type.  Whatever we return here is
8652 
     passed as operand 2 to the call expanders.
8653 
 
8654 
     We don't need this feature ...  */
8655 
  else if (type == void_type_node)
8656 
    return const0_rtx;
8657 
 
8658 
  gcc_unreachable ();
8659 
}
8660 
 
8661 
/* Return true if return values of type TYPE should be returned
8662 
   in a memory buffer whose address is passed by the caller as
8663 
   hidden first argument.  */
8664 
 
8665 
static bool
8666 
s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8667 
{
8668 
  /* We accept small integral (and similar) types.  */
8669 
  if (INTEGRAL_TYPE_P (type)
8670 
      || POINTER_TYPE_P (type)
8671 
      || TREE_CODE (type) == OFFSET_TYPE
8672 
      || TREE_CODE (type) == REAL_TYPE)
8673 
    return int_size_in_bytes (type) > 8;
8674 
 
8675 
  /* Aggregates and similar constructs are always returned
8676 
     in memory.  */
8677 
  if (AGGREGATE_TYPE_P (type)
8678 
      || TREE_CODE (type) == COMPLEX_TYPE
8679 
      || TREE_CODE (type) == VECTOR_TYPE)
8680 
    return true;
8681 
 
8682 
  /* ??? We get called on all sorts of random stuff from
8683 
     aggregate_value_p.  We can't abort, but it's not clear
8684 
     what's safe to return.  Pretend it's a struct I guess.  */
8685 
  return true;
8686 
}
8687 
 
8688 
/* Function arguments and return values are promoted to word size.  */
8689 
 
8690 
static enum machine_mode
8691 
s390_promote_function_mode (const_tree type, enum machine_mode mode,
8692 
                            int *punsignedp,
8693 
                            const_tree fntype ATTRIBUTE_UNUSED,
8694 
                            int for_return ATTRIBUTE_UNUSED)
8695 
{
8696 
  if (INTEGRAL_MODE_P (mode)
8697 
      && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
8698 
    {
8699 
      if (type != NULL_TREE && POINTER_TYPE_P (type))
8700 
        *punsignedp = POINTERS_EXTEND_UNSIGNED;
8701 
      return Pmode;
8702 
    }
8703 
 
8704 
  return mode;
8705 
}
8706 
 
8707 
/* Define where to return a (scalar) value of type RET_TYPE.
8708 
   If RET_TYPE is null, define where to return a (scalar)
8709 
   value of mode MODE from a libcall.  */
8710 
 
8711 
static rtx
8712 
s390_function_and_libcall_value (enum machine_mode mode,
8713 
                                 const_tree ret_type,
8714 
                                 const_tree fntype_or_decl,
8715 
                                 bool outgoing ATTRIBUTE_UNUSED)
8716 
{
8717 
  /* For normal functions perform the promotion as
8718 
     promote_function_mode would do.  */
8719 
  if (ret_type)
8720 
    {
8721 
      int unsignedp = TYPE_UNSIGNED (ret_type);
8722 
      mode = promote_function_mode (ret_type, mode, &unsignedp,
8723 
                                    fntype_or_decl, 1);
8724 
    }
8725 
 
8726 
  gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8727 
  gcc_assert (GET_MODE_SIZE (mode) <= 8);
8728 
 
8729 
  if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8730 
    return gen_rtx_REG (mode, 16);
8731 
  else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
8732 
           || UNITS_PER_LONG == UNITS_PER_WORD)
8733 
    return gen_rtx_REG (mode, 2);
8734 
  else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
8735 
    {
8736 
      /* This case is triggered when returning a 64 bit value with
8737 
         -m31 -mzarch.  Although the value would fit into a single
8738 
         register it has to be forced into a 32 bit register pair in
8739 
         order to match the ABI.  */
8740 
      rtvec p = rtvec_alloc (2);
8741 
 
8742 
      RTVEC_ELT (p, 0)
8743 
        = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
8744 
      RTVEC_ELT (p, 1)
8745 
        = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
8746 
 
8747 
      return gen_rtx_PARALLEL (mode, p);
8748 
    }
8749 
 
8750 
  gcc_unreachable ();
8751 
}
8752 
 
8753 
/* Define where to return a scalar return value of type RET_TYPE.  */
8754 
 
8755 
static rtx
8756 
s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
8757 
                     bool outgoing)
8758 
{
8759 
  return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
8760 
                                          fn_decl_or_type, outgoing);
8761 
}
8762 
 
8763 
/* Define where to return a scalar libcall return value of mode
8764 
   MODE.  */
8765 
 
8766 
static rtx
8767 
s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8768 
{
8769 
  return s390_function_and_libcall_value (mode, NULL_TREE,
8770 
                                          NULL_TREE, true);
8771 
}
8772 
 
8773 
 
8774 
/* Create and return the va_list datatype.
8775 
 
8776 
   On S/390, va_list is an array type equivalent to
8777 
 
8778 
      typedef struct __va_list_tag
8779 
        {
8780 
            long __gpr;
8781 
            long __fpr;
8782 
            void *__overflow_arg_area;
8783 
            void *__reg_save_area;
8784 
        } va_list[1];
8785 
 
8786 
   where __gpr and __fpr hold the number of general purpose
8787 
   or floating point arguments used up to now, respectively,
8788 
   __overflow_arg_area points to the stack location of the
8789 
   next argument passed on the stack, and __reg_save_area
8790 
   always points to the start of the register area in the
8791 
   call frame of the current function.  The function prologue
8792 
   saves all registers used for argument passing into this
8793 
   area if the function uses variable arguments.  */
8794 
 
8795 
static tree
8796 
s390_build_builtin_va_list (void)
8797 
{
8798 
  tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8799 
 
8800 
  record = lang_hooks.types.make_type (RECORD_TYPE);
8801 
 
8802 
  type_decl =
8803 
    build_decl (BUILTINS_LOCATION,
8804 
                TYPE_DECL, get_identifier ("__va_list_tag"), record);
8805 
 
8806 
  f_gpr = build_decl (BUILTINS_LOCATION,
8807 
                      FIELD_DECL, get_identifier ("__gpr"),
8808 
                      long_integer_type_node);
8809 
  f_fpr = build_decl (BUILTINS_LOCATION,
8810 
                      FIELD_DECL, get_identifier ("__fpr"),
8811 
                      long_integer_type_node);
8812 
  f_ovf = build_decl (BUILTINS_LOCATION,
8813 
                      FIELD_DECL, get_identifier ("__overflow_arg_area"),
8814 
                      ptr_type_node);
8815 
  f_sav = build_decl (BUILTINS_LOCATION,
8816 
                      FIELD_DECL, get_identifier ("__reg_save_area"),
8817 
                      ptr_type_node);
8818 
 
8819 
  va_list_gpr_counter_field = f_gpr;
8820 
  va_list_fpr_counter_field = f_fpr;
8821 
 
8822 
  DECL_FIELD_CONTEXT (f_gpr) = record;
8823 
  DECL_FIELD_CONTEXT (f_fpr) = record;
8824 
  DECL_FIELD_CONTEXT (f_ovf) = record;
8825 
  DECL_FIELD_CONTEXT (f_sav) = record;
8826 
 
8827 
  TYPE_STUB_DECL (record) = type_decl;
8828 
  TYPE_NAME (record) = type_decl;
8829 
  TYPE_FIELDS (record) = f_gpr;
8830 
  DECL_CHAIN (f_gpr) = f_fpr;
8831 
  DECL_CHAIN (f_fpr) = f_ovf;
8832 
  DECL_CHAIN (f_ovf) = f_sav;
8833 
 
8834 
  layout_type (record);
8835 
 
8836 
  /* The correct type is an array type of one element.  */
8837 
  return build_array_type (record, build_index_type (size_zero_node));
8838 
}
8839 
 
8840 
/* Implement va_start by filling the va_list structure VALIST.
8841 
   STDARG_P is always true, and ignored.
8842 
   NEXTARG points to the first anonymous stack argument.
8843 
 
8844 
   The following global variables are used to initialize
8845 
   the va_list structure:
8846 
 
8847 
     crtl->args.info:
8848 
       holds number of gprs and fprs used for named arguments.
8849 
     crtl->args.arg_offset_rtx:
8850 
       holds the offset of the first anonymous stack argument
8851 
       (relative to the virtual arg pointer).  */
8852 
 
8853 
static void
8854 
s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8855 
{
8856 
  HOST_WIDE_INT n_gpr, n_fpr;
8857 
  int off;
8858 
  tree f_gpr, f_fpr, f_ovf, f_sav;
8859 
  tree gpr, fpr, ovf, sav, t;
8860 
 
8861 
  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8862 
  f_fpr = DECL_CHAIN (f_gpr);
8863 
  f_ovf = DECL_CHAIN (f_fpr);
8864 
  f_sav = DECL_CHAIN (f_ovf);
8865 
 
8866 
  valist = build_simple_mem_ref (valist);
8867 
  gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8868 
  fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8869 
  ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8870 
  sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8871 
 
8872 
  /* Count number of gp and fp argument registers used.  */
8873 
 
8874 
  n_gpr = crtl->args.info.gprs;
8875 
  n_fpr = crtl->args.info.fprs;
8876 
 
8877 
  if (cfun->va_list_gpr_size)
8878 
    {
8879 
      t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8880 
                  build_int_cst (NULL_TREE, n_gpr));
8881 
      TREE_SIDE_EFFECTS (t) = 1;
8882 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8883 
    }
8884 
 
8885 
  if (cfun->va_list_fpr_size)
8886 
    {
8887 
      t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8888 
                  build_int_cst (NULL_TREE, n_fpr));
8889 
      TREE_SIDE_EFFECTS (t) = 1;
8890 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8891 
    }
8892 
 
8893 
  /* Find the overflow area.  */
8894 
  if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8895 
      || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8896 
    {
8897 
      t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8898 
 
8899 
      off = INTVAL (crtl->args.arg_offset_rtx);
8900 
      off = off < 0 ? 0 : off;
8901 
      if (TARGET_DEBUG_ARG)
8902 
        fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8903 
                 (int)n_gpr, (int)n_fpr, off);
8904 
 
8905 
      t = fold_build_pointer_plus_hwi (t, off);
8906 
 
8907 
      t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8908 
      TREE_SIDE_EFFECTS (t) = 1;
8909 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8910 
    }
8911 
 
8912 
  /* Find the register save area.  */
8913 
  if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8914 
      || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8915 
    {
8916 
      t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8917 
      t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
8918 
 
8919 
      t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8920 
      TREE_SIDE_EFFECTS (t) = 1;
8921 
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8922 
    }
8923 
}
8924 
 
8925 
/* Implement va_arg by updating the va_list structure
8926 
   VALIST as required to retrieve an argument of type
8927 
   TYPE, and returning that argument.
8928 
 
8929 
   Generates code equivalent to:
8930 
 
8931 
   if (integral value) {
8932 
     if (size  <= 4 && args.gpr < 5 ||
8933 
         size  > 4 && args.gpr < 4 )
8934 
       ret = args.reg_save_area[args.gpr+8]
8935 
     else
8936 
       ret = *args.overflow_arg_area++;
8937 
   } else if (float value) {
8938 
     if (args.fgpr < 2)
8939 
       ret = args.reg_save_area[args.fpr+64]
8940 
     else
8941 
       ret = *args.overflow_arg_area++;
8942 
   } else if (aggregate value) {
8943 
     if (args.gpr < 5)
8944 
       ret = *args.reg_save_area[args.gpr]
8945 
     else
8946 
       ret = **args.overflow_arg_area++;
8947 
   } */
8948 
 
8949 
static tree
8950 
s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8951 
                      gimple_seq *post_p ATTRIBUTE_UNUSED)
8952 
{
8953 
  tree f_gpr, f_fpr, f_ovf, f_sav;
8954 
  tree gpr, fpr, ovf, sav, reg, t, u;
8955 
  int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8956 
  tree lab_false, lab_over, addr;
8957 
 
8958 
  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8959 
  f_fpr = DECL_CHAIN (f_gpr);
8960 
  f_ovf = DECL_CHAIN (f_fpr);
8961 
  f_sav = DECL_CHAIN (f_ovf);
8962 
 
8963 
  valist = build_va_arg_indirect_ref (valist);
8964 
  gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8965 
  fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8966 
  sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8967 
 
8968 
  /* The tree for args* cannot be shared between gpr/fpr and ovf since
8969 
     both appear on a lhs.  */
8970 
  valist = unshare_expr (valist);
8971 
  ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8972 
 
8973 
  size = int_size_in_bytes (type);
8974 
 
8975 
  if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8976 
    {
8977 
      if (TARGET_DEBUG_ARG)
8978 
        {
8979 
          fprintf (stderr, "va_arg: aggregate type");
8980 
          debug_tree (type);
8981 
        }
8982 
 
8983 
      /* Aggregates are passed by reference.  */
8984 
      indirect_p = 1;
8985 
      reg = gpr;
8986 
      n_reg = 1;
8987 
 
8988 
      /* kernel stack layout on 31 bit: It is assumed here that no padding
8989 
         will be added by s390_frame_info because for va_args always an even
8990 
         number of gprs has to be saved r15-r2 = 14 regs.  */
8991 
      sav_ofs = 2 * UNITS_PER_LONG;
8992 
      sav_scale = UNITS_PER_LONG;
8993 
      size = UNITS_PER_LONG;
8994 
      max_reg = GP_ARG_NUM_REG - n_reg;
8995 
    }
8996 
  else if (s390_function_arg_float (TYPE_MODE (type), type))
8997 
    {
8998 
      if (TARGET_DEBUG_ARG)
8999 
        {
9000 
          fprintf (stderr, "va_arg: float type");
9001 
          debug_tree (type);
9002 
        }
9003 
 
9004 
      /* FP args go in FP registers, if present.  */
9005 
      indirect_p = 0;
9006 
      reg = fpr;
9007 
      n_reg = 1;
9008 
      sav_ofs = 16 * UNITS_PER_LONG;
9009 
      sav_scale = 8;
9010 
      max_reg = FP_ARG_NUM_REG - n_reg;
9011 
    }
9012 
  else
9013 
    {
9014 
      if (TARGET_DEBUG_ARG)
9015 
        {
9016 
          fprintf (stderr, "va_arg: other type");
9017 
          debug_tree (type);
9018 
        }
9019 
 
9020 
      /* Otherwise into GP registers.  */
9021 
      indirect_p = 0;
9022 
      reg = gpr;
9023 
      n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9024 
 
9025 
      /* kernel stack layout on 31 bit: It is assumed here that no padding
9026 
         will be added by s390_frame_info because for va_args always an even
9027 
         number of gprs has to be saved r15-r2 = 14 regs.  */
9028 
      sav_ofs = 2 * UNITS_PER_LONG;
9029 
 
9030 
      if (size < UNITS_PER_LONG)
9031 
        sav_ofs += UNITS_PER_LONG - size;
9032 
 
9033 
      sav_scale = UNITS_PER_LONG;
9034 
      max_reg = GP_ARG_NUM_REG - n_reg;
9035 
    }
9036 
 
9037 
  /* Pull the value out of the saved registers ...  */
9038 
 
9039 
  lab_false = create_artificial_label (UNKNOWN_LOCATION);
9040 
  lab_over = create_artificial_label (UNKNOWN_LOCATION);
9041 
  addr = create_tmp_var (ptr_type_node, "addr");
9042 
 
9043 
  t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9044 
  t = build2 (GT_EXPR, boolean_type_node, reg, t);
9045 
  u = build1 (GOTO_EXPR, void_type_node, lab_false);
9046 
  t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9047 
  gimplify_and_add (t, pre_p);
9048 
 
9049 
  t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9050 
  u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9051 
              fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9052 
  t = fold_build_pointer_plus (t, u);
9053 
 
9054 
  gimplify_assign (addr, t, pre_p);
9055 
 
9056 
  gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9057 
 
9058 
  gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9059 
 
9060 
 
9061 
  /* ... Otherwise out of the overflow area.  */
9062 
 
9063 
  t = ovf;
9064 
  if (size < UNITS_PER_LONG)
9065 
    t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9066 
 
9067 
  gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9068 
 
9069 
  gimplify_assign (addr, t, pre_p);
9070 
 
9071 
  t = fold_build_pointer_plus_hwi (t, size);
9072 
  gimplify_assign (ovf, t, pre_p);
9073 
 
9074 
  gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9075 
 
9076 
 
9077 
  /* Increment register save count.  */
9078 
 
9079 
  u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9080 
              fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9081 
  gimplify_and_add (u, pre_p);
9082 
 
9083 
  if (indirect_p)
9084 
    {
9085 
      t = build_pointer_type_for_mode (build_pointer_type (type),
9086 
                                       ptr_mode, true);
9087 
      addr = fold_convert (t, addr);
9088 
      addr = build_va_arg_indirect_ref (addr);
9089 
    }
9090 
  else
9091 
    {
9092 
      t = build_pointer_type_for_mode (type, ptr_mode, true);
9093 
      addr = fold_convert (t, addr);
9094 
    }
9095 
 
9096 
  return build_va_arg_indirect_ref (addr);
9097 
}
9098 
 
9099 
 
9100 
/* Builtins.  */
9101 
 
9102 
enum s390_builtin
9103 
{
9104 
  S390_BUILTIN_THREAD_POINTER,
9105 
  S390_BUILTIN_SET_THREAD_POINTER,
9106 
 
9107 
  S390_BUILTIN_max
9108 
};
9109 
 
9110 
static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
9111 
  CODE_FOR_get_tp_64,
9112 
  CODE_FOR_set_tp_64
9113 
};
9114 
 
9115 
static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
9116 
  CODE_FOR_get_tp_31,
9117 
  CODE_FOR_set_tp_31
9118 
};
9119 
 
9120 
static void
9121 
s390_init_builtins (void)
9122 
{
9123 
  tree ftype;
9124 
 
9125 
  ftype = build_function_type_list (ptr_type_node, NULL_TREE);
9126 
  add_builtin_function ("__builtin_thread_pointer", ftype,
9127 
                        S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
9128 
                        NULL, NULL_TREE);
9129 
 
9130 
  ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
9131 
  add_builtin_function ("__builtin_set_thread_pointer", ftype,
9132 
                        S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
9133 
                        NULL, NULL_TREE);
9134 
}
9135 
 
9136 
/* Expand an expression EXP that calls a built-in function,
9137 
   with result going to TARGET if that's convenient
9138 
   (and in mode MODE if that's convenient).
9139 
   SUBTARGET may be used as the target for computing one of EXP's operands.
9140 
   IGNORE is nonzero if the value is to be ignored.  */
9141 
 
9142 
static rtx
9143 
s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9144 
                     enum machine_mode mode ATTRIBUTE_UNUSED,
9145 
                     int ignore ATTRIBUTE_UNUSED)
9146 
{
9147 
#define MAX_ARGS 2
9148 
 
9149 
  enum insn_code const *code_for_builtin =
9150 
    TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
9151 
 
9152 
  tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9153 
  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9154 
  enum insn_code icode;
9155 
  rtx op[MAX_ARGS], pat;
9156 
  int arity;
9157 
  bool nonvoid;
9158 
  tree arg;
9159 
  call_expr_arg_iterator iter;
9160 
 
9161 
  if (fcode >= S390_BUILTIN_max)
9162 
    internal_error ("bad builtin fcode");
9163 
  icode = code_for_builtin[fcode];
9164 
  if (icode == 0)
9165 
    internal_error ("bad builtin fcode");
9166 
 
9167 
  nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
9168 
 
9169 
  arity = 0;
9170 
  FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
9171 
    {
9172 
      const struct insn_operand_data *insn_op;
9173 
 
9174 
      if (arg == error_mark_node)
9175 
        return NULL_RTX;
9176 
      if (arity > MAX_ARGS)
9177 
        return NULL_RTX;
9178 
 
9179 
      insn_op = &insn_data[icode].operand[arity + nonvoid];
9180 
 
9181 
      op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
9182 
 
9183 
      if (!(*insn_op->predicate) (op[arity], insn_op->mode))
9184 
        op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
9185 
      arity++;
9186 
    }
9187 
 
9188 
  if (nonvoid)
9189 
    {
9190 
      enum machine_mode tmode = insn_data[icode].operand[0].mode;
9191 
      if (!target
9192 
          || GET_MODE (target) != tmode
9193 
          || !(*insn_data[icode].operand[0].predicate) (target, tmode))
9194 
        target = gen_reg_rtx (tmode);
9195 
    }
9196 
 
9197 
  switch (arity)
9198 
    {
9199 
    case 0:
9200 
      pat = GEN_FCN (icode) (target);
9201 
      break;
9202 
    case 1:
9203 
      if (nonvoid)
9204 
        pat = GEN_FCN (icode) (target, op[0]);
9205 
      else
9206 
        pat = GEN_FCN (icode) (op[0]);
9207 
      break;
9208 
    case 2:
9209 
      pat = GEN_FCN (icode) (target, op[0], op[1]);
9210 
      break;
9211 
    default:
9212 
      gcc_unreachable ();
9213 
    }
9214 
  if (!pat)
9215 
    return NULL_RTX;
9216 
  emit_insn (pat);
9217 
 
9218 
  if (nonvoid)
9219 
    return target;
9220 
  else
9221 
    return const0_rtx;
9222 
}
9223 
 
9224 
 
9225 
/* Output assembly code for the trampoline template to
9226 
   stdio stream FILE.
9227 
 
9228 
   On S/390, we use gpr 1 internally in the trampoline code;
9229 
   gpr 0 is used to hold the static chain.  */
9230 
 
9231 
static void
9232 
s390_asm_trampoline_template (FILE *file)
9233 
{
9234 
  rtx op[2];
9235 
  op[0] = gen_rtx_REG (Pmode, 0);
9236 
  op[1] = gen_rtx_REG (Pmode, 1);
9237 
 
9238 
  if (TARGET_64BIT)
9239 
    {
9240 
      output_asm_insn ("basr\t%1,0", op);         /* 2 byte */
9241 
      output_asm_insn ("lmg\t%0,%1,14(%1)", op);  /* 6 byte */
9242 
      output_asm_insn ("br\t%1", op);             /* 2 byte */
9243 
      ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
9244 
    }
9245 
  else
9246 
    {
9247 
      output_asm_insn ("basr\t%1,0", op);         /* 2 byte */
9248 
      output_asm_insn ("lm\t%0,%1,6(%1)", op);    /* 4 byte */
9249 
      output_asm_insn ("br\t%1", op);             /* 2 byte */
9250 
      ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
9251 
    }
9252 
}
9253 
 
9254 
/* Emit RTL insns to initialize the variable parts of a trampoline.
9255 
   FNADDR is an RTX for the address of the function's pure code.
9256 
   CXT is an RTX for the static chain value for the function.  */
9257 
 
9258 
static void
9259 
s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
9260 
{
9261 
  rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
9262 
  rtx mem;
9263 
 
9264 
  emit_block_move (m_tramp, assemble_trampoline_template (),
9265 
                   GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
9266 
 
9267 
  mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
9268 
  emit_move_insn (mem, cxt);
9269 
  mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
9270 
  emit_move_insn (mem, fnaddr);
9271 
}
9272 
 
9273 
/* Output assembler code to FILE to increment profiler label # LABELNO
9274 
   for profiling a function entry.  */
9275 
 
9276 
void
9277 
s390_function_profiler (FILE *file, int labelno)
9278 
{
9279 
  rtx op[7];
9280 
 
9281 
  char label[128];
9282 
  ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
9283 
 
9284 
  fprintf (file, "# function profiler \n");
9285 
 
9286 
  op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
9287 
  op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9288 
  op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
9289 
 
9290 
  op[2] = gen_rtx_REG (Pmode, 1);
9291 
  op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
9292 
  SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
9293 
 
9294 
  op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
9295 
  if (flag_pic)
9296 
    {
9297 
      op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
9298 
      op[4] = gen_rtx_CONST (Pmode, op[4]);
9299 
    }
9300 
 
9301 
  if (TARGET_64BIT)
9302 
    {
9303 
      output_asm_insn ("stg\t%0,%1", op);
9304 
      output_asm_insn ("larl\t%2,%3", op);
9305 
      output_asm_insn ("brasl\t%0,%4", op);
9306 
      output_asm_insn ("lg\t%0,%1", op);
9307 
    }
9308 
  else if (!flag_pic)
9309 
    {
9310 
      op[6] = gen_label_rtx ();
9311 
 
9312 
      output_asm_insn ("st\t%0,%1", op);
9313 
      output_asm_insn ("bras\t%2,%l6", op);
9314 
      output_asm_insn (".long\t%4", op);
9315 
      output_asm_insn (".long\t%3", op);
9316 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9317 
      output_asm_insn ("l\t%0,0(%2)", op);
9318 
      output_asm_insn ("l\t%2,4(%2)", op);
9319 
      output_asm_insn ("basr\t%0,%0", op);
9320 
      output_asm_insn ("l\t%0,%1", op);
9321 
    }
9322 
  else
9323 
    {
9324 
      op[5] = gen_label_rtx ();
9325 
      op[6] = gen_label_rtx ();
9326 
 
9327 
      output_asm_insn ("st\t%0,%1", op);
9328 
      output_asm_insn ("bras\t%2,%l6", op);
9329 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
9330 
      output_asm_insn (".long\t%4-%l5", op);
9331 
      output_asm_insn (".long\t%3-%l5", op);
9332 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
9333 
      output_asm_insn ("lr\t%0,%2", op);
9334 
      output_asm_insn ("a\t%0,0(%2)", op);
9335 
      output_asm_insn ("a\t%2,4(%2)", op);
9336 
      output_asm_insn ("basr\t%0,%0", op);
9337 
      output_asm_insn ("l\t%0,%1", op);
9338 
    }
9339 
}
9340 
 
9341 
/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9342 
   into its SYMBOL_REF_FLAGS.  */
9343 
 
9344 
static void
9345 
s390_encode_section_info (tree decl, rtx rtl, int first)
9346 
{
9347 
  default_encode_section_info (decl, rtl, first);
9348 
 
9349 
  if (TREE_CODE (decl) == VAR_DECL)
9350 
    {
9351 
      /* If a variable has a forced alignment to < 2 bytes, mark it
9352 
         with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9353 
         operand.  */
9354 
      if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
9355 
        SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
9356 
      if (!DECL_SIZE (decl)
9357 
          || !DECL_ALIGN (decl)
9358 
          || !host_integerp (DECL_SIZE (decl), 0)
9359 
          || (DECL_ALIGN (decl) <= 64
9360 
              && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
9361 
        SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9362 
    }
9363 
 
9364 
  /* Literal pool references don't have a decl so they are handled
9365 
     differently here.  We rely on the information in the MEM_ALIGN
9366 
     entry to decide upon natural alignment.  */
9367 
  if (MEM_P (rtl)
9368 
      && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9369 
      && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9370 
      && (MEM_ALIGN (rtl) == 0
9371 
          || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
9372 
          || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9373 
    SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9374 
}
9375 
 
9376 
/* Output thunk to FILE that implements a C++ virtual function call (with
9377 
   multiple inheritance) to FUNCTION.  The thunk adjusts the this pointer
9378 
   by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9379 
   stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9380 
   relative to the resulting this pointer.  */
9381 
 
9382 
static void
9383 
s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9384 
                      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9385 
                      tree function)
9386 
{
9387 
  rtx op[10];
9388 
  int nonlocal = 0;
9389 
 
9390 
  /* Make sure unwind info is emitted for the thunk if needed.  */
9391 
  final_start_function (emit_barrier (), file, 1);
9392 
 
9393 
  /* Operand 0 is the target function.  */
9394 
  op[0] = XEXP (DECL_RTL (function), 0);
9395 
  if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9396 
    {
9397 
      nonlocal = 1;
9398 
      op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9399 
                              TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9400 
      op[0] = gen_rtx_CONST (Pmode, op[0]);
9401 
    }
9402 
 
9403 
  /* Operand 1 is the 'this' pointer.  */
9404 
  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9405 
    op[1] = gen_rtx_REG (Pmode, 3);
9406 
  else
9407 
    op[1] = gen_rtx_REG (Pmode, 2);
9408 
 
9409 
  /* Operand 2 is the delta.  */
9410 
  op[2] = GEN_INT (delta);
9411 
 
9412 
  /* Operand 3 is the vcall_offset.  */
9413 
  op[3] = GEN_INT (vcall_offset);
9414 
 
9415 
  /* Operand 4 is the temporary register.  */
9416 
  op[4] = gen_rtx_REG (Pmode, 1);
9417 
 
9418 
  /* Operands 5 to 8 can be used as labels.  */
9419 
  op[5] = NULL_RTX;
9420 
  op[6] = NULL_RTX;
9421 
  op[7] = NULL_RTX;
9422 
  op[8] = NULL_RTX;
9423 
 
9424 
  /* Operand 9 can be used for temporary register.  */
9425 
  op[9] = NULL_RTX;
9426 
 
9427 
  /* Generate code.  */
9428 
  if (TARGET_64BIT)
9429 
    {
9430 
      /* Setup literal pool pointer if required.  */
9431 
      if ((!DISP_IN_RANGE (delta)
9432 
           && !CONST_OK_FOR_K (delta)
9433 
           && !CONST_OK_FOR_Os (delta))
9434 
          || (!DISP_IN_RANGE (vcall_offset)
9435 
              && !CONST_OK_FOR_K (vcall_offset)
9436 
              && !CONST_OK_FOR_Os (vcall_offset)))
9437 
        {
9438 
          op[5] = gen_label_rtx ();
9439 
          output_asm_insn ("larl\t%4,%5", op);
9440 
        }
9441 
 
9442 
      /* Add DELTA to this pointer.  */
9443 
      if (delta)
9444 
        {
9445 
          if (CONST_OK_FOR_J (delta))
9446 
            output_asm_insn ("la\t%1,%2(%1)", op);
9447 
          else if (DISP_IN_RANGE (delta))
9448 
            output_asm_insn ("lay\t%1,%2(%1)", op);
9449 
          else if (CONST_OK_FOR_K (delta))
9450 
            output_asm_insn ("aghi\t%1,%2", op);
9451 
          else if (CONST_OK_FOR_Os (delta))
9452 
            output_asm_insn ("agfi\t%1,%2", op);
9453 
          else
9454 
            {
9455 
              op[6] = gen_label_rtx ();
9456 
              output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9457 
            }
9458 
        }
9459 
 
9460 
      /* Perform vcall adjustment.  */
9461 
      if (vcall_offset)
9462 
        {
9463 
          if (DISP_IN_RANGE (vcall_offset))
9464 
            {
9465 
              output_asm_insn ("lg\t%4,0(%1)", op);
9466 
              output_asm_insn ("ag\t%1,%3(%4)", op);
9467 
            }
9468 
          else if (CONST_OK_FOR_K (vcall_offset))
9469 
            {
9470 
              output_asm_insn ("lghi\t%4,%3", op);
9471 
              output_asm_insn ("ag\t%4,0(%1)", op);
9472 
              output_asm_insn ("ag\t%1,0(%4)", op);
9473 
            }
9474 
          else if (CONST_OK_FOR_Os (vcall_offset))
9475 
            {
9476 
              output_asm_insn ("lgfi\t%4,%3", op);
9477 
              output_asm_insn ("ag\t%4,0(%1)", op);
9478 
              output_asm_insn ("ag\t%1,0(%4)", op);
9479 
            }
9480 
          else
9481 
            {
9482 
              op[7] = gen_label_rtx ();
9483 
              output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9484 
              output_asm_insn ("ag\t%4,0(%1)", op);
9485 
              output_asm_insn ("ag\t%1,0(%4)", op);
9486 
            }
9487 
        }
9488 
 
9489 
      /* Jump to target.  */
9490 
      output_asm_insn ("jg\t%0", op);
9491 
 
9492 
      /* Output literal pool if required.  */
9493 
      if (op[5])
9494 
        {
9495 
          output_asm_insn (".align\t4", op);
9496 
          targetm.asm_out.internal_label (file, "L",
9497 
                                          CODE_LABEL_NUMBER (op[5]));
9498 
        }
9499 
      if (op[6])
9500 
        {
9501 
          targetm.asm_out.internal_label (file, "L",
9502 
                                          CODE_LABEL_NUMBER (op[6]));
9503 
          output_asm_insn (".long\t%2", op);
9504 
        }
9505 
      if (op[7])
9506 
        {
9507 
          targetm.asm_out.internal_label (file, "L",
9508 
                                          CODE_LABEL_NUMBER (op[7]));
9509 
          output_asm_insn (".long\t%3", op);
9510 
        }
9511 
    }
9512 
  else
9513 
    {
9514 
      /* Setup base pointer if required.  */
9515 
      if (!vcall_offset
9516 
          || (!DISP_IN_RANGE (delta)
9517 
              && !CONST_OK_FOR_K (delta)
9518 
              && !CONST_OK_FOR_Os (delta))
9519 
          || (!DISP_IN_RANGE (delta)
9520 
              && !CONST_OK_FOR_K (vcall_offset)
9521 
              && !CONST_OK_FOR_Os (vcall_offset)))
9522 
        {
9523 
          op[5] = gen_label_rtx ();
9524 
          output_asm_insn ("basr\t%4,0", op);
9525 
          targetm.asm_out.internal_label (file, "L",
9526 
                                          CODE_LABEL_NUMBER (op[5]));
9527 
        }
9528 
 
9529 
      /* Add DELTA to this pointer.  */
9530 
      if (delta)
9531 
        {
9532 
          if (CONST_OK_FOR_J (delta))
9533 
            output_asm_insn ("la\t%1,%2(%1)", op);
9534 
          else if (DISP_IN_RANGE (delta))
9535 
            output_asm_insn ("lay\t%1,%2(%1)", op);
9536 
          else if (CONST_OK_FOR_K (delta))
9537 
            output_asm_insn ("ahi\t%1,%2", op);
9538 
          else if (CONST_OK_FOR_Os (delta))
9539 
            output_asm_insn ("afi\t%1,%2", op);
9540 
          else
9541 
            {
9542 
              op[6] = gen_label_rtx ();
9543 
              output_asm_insn ("a\t%1,%6-%5(%4)", op);
9544 
            }
9545 
        }
9546 
 
9547 
      /* Perform vcall adjustment.  */
9548 
      if (vcall_offset)
9549 
        {
9550 
          if (CONST_OK_FOR_J (vcall_offset))
9551 
            {
9552 
              output_asm_insn ("l\t%4,0(%1)", op);
9553 
              output_asm_insn ("a\t%1,%3(%4)", op);
9554 
            }
9555 
          else if (DISP_IN_RANGE (vcall_offset))
9556 
            {
9557 
              output_asm_insn ("l\t%4,0(%1)", op);
9558 
              output_asm_insn ("ay\t%1,%3(%4)", op);
9559 
            }
9560 
          else if (CONST_OK_FOR_K (vcall_offset))
9561 
            {
9562 
              output_asm_insn ("lhi\t%4,%3", op);
9563 
              output_asm_insn ("a\t%4,0(%1)", op);
9564 
              output_asm_insn ("a\t%1,0(%4)", op);
9565 
            }
9566 
          else if (CONST_OK_FOR_Os (vcall_offset))
9567 
            {
9568 
              output_asm_insn ("iilf\t%4,%3", op);
9569 
              output_asm_insn ("a\t%4,0(%1)", op);
9570 
              output_asm_insn ("a\t%1,0(%4)", op);
9571 
            }
9572 
          else
9573 
            {
9574 
              op[7] = gen_label_rtx ();
9575 
              output_asm_insn ("l\t%4,%7-%5(%4)", op);
9576 
              output_asm_insn ("a\t%4,0(%1)", op);
9577 
              output_asm_insn ("a\t%1,0(%4)", op);
9578 
            }
9579 
 
9580 
          /* We had to clobber the base pointer register.
9581 
             Re-setup the base pointer (with a different base).  */
9582 
          op[5] = gen_label_rtx ();
9583 
          output_asm_insn ("basr\t%4,0", op);
9584 
          targetm.asm_out.internal_label (file, "L",
9585 
                                          CODE_LABEL_NUMBER (op[5]));
9586 
        }
9587 
 
9588 
      /* Jump to target.  */
9589 
      op[8] = gen_label_rtx ();
9590 
 
9591 
      if (!flag_pic)
9592 
        output_asm_insn ("l\t%4,%8-%5(%4)", op);
9593 
      else if (!nonlocal)
9594 
        output_asm_insn ("a\t%4,%8-%5(%4)", op);
9595 
      /* We cannot call through .plt, since .plt requires %r12 loaded.  */
9596 
      else if (flag_pic == 1)
9597 
        {
9598 
          output_asm_insn ("a\t%4,%8-%5(%4)", op);
9599 
          output_asm_insn ("l\t%4,%0(%4)", op);
9600 
        }
9601 
      else if (flag_pic == 2)
9602 
        {
9603 
          op[9] = gen_rtx_REG (Pmode, 0);
9604 
          output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9605 
          output_asm_insn ("a\t%4,%8-%5(%4)", op);
9606 
          output_asm_insn ("ar\t%4,%9", op);
9607 
          output_asm_insn ("l\t%4,0(%4)", op);
9608 
        }
9609 
 
9610 
      output_asm_insn ("br\t%4", op);
9611 
 
9612 
      /* Output literal pool.  */
9613 
      output_asm_insn (".align\t4", op);
9614 
 
9615 
      if (nonlocal && flag_pic == 2)
9616 
        output_asm_insn (".long\t%0", op);
9617 
      if (nonlocal)
9618 
        {
9619 
          op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9620 
          SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9621 
        }
9622 
 
9623 
      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9624 
      if (!flag_pic)
9625 
        output_asm_insn (".long\t%0", op);
9626 
      else
9627 
        output_asm_insn (".long\t%0-%5", op);
9628 
 
9629 
      if (op[6])
9630 
        {
9631 
          targetm.asm_out.internal_label (file, "L",
9632 
                                          CODE_LABEL_NUMBER (op[6]));
9633 
          output_asm_insn (".long\t%2", op);
9634 
        }
9635 
      if (op[7])
9636 
        {
9637 
          targetm.asm_out.internal_label (file, "L",
9638 
                                          CODE_LABEL_NUMBER (op[7]));
9639 
          output_asm_insn (".long\t%3", op);
9640 
        }
9641 
    }
9642 
  final_end_function ();
9643 
}
9644 
 
9645 
static bool
9646 
s390_valid_pointer_mode (enum machine_mode mode)
9647 
{
9648 
  return (mode == SImode || (TARGET_64BIT && mode == DImode));
9649 
}
9650 
 
9651 
/* Checks whether the given CALL_EXPR would use a caller
9652 
   saved register.  This is used to decide whether sibling call
9653 
   optimization could be performed on the respective function
9654 
   call.  */
9655 
 
9656 
static bool
9657 
s390_call_saved_register_used (tree call_expr)
9658 
{
9659 
  CUMULATIVE_ARGS cum_v;
9660 
  cumulative_args_t cum;
9661 
  tree parameter;
9662 
  enum machine_mode mode;
9663 
  tree type;
9664 
  rtx parm_rtx;
9665 
  int reg, i;
9666 
 
9667 
  INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
9668 
  cum = pack_cumulative_args (&cum_v);
9669 
 
9670 
  for (i = 0; i < call_expr_nargs (call_expr); i++)
9671 
    {
9672 
      parameter = CALL_EXPR_ARG (call_expr, i);
9673 
      gcc_assert (parameter);
9674 
 
9675 
      /* For an undeclared variable passed as parameter we will get
9676 
         an ERROR_MARK node here.  */
9677 
      if (TREE_CODE (parameter) == ERROR_MARK)
9678 
        return true;
9679 
 
9680 
      type = TREE_TYPE (parameter);
9681 
      gcc_assert (type);
9682 
 
9683 
      mode = TYPE_MODE (type);
9684 
      gcc_assert (mode);
9685 
 
9686 
      if (pass_by_reference (&cum_v, mode, type, true))
9687 
        {
9688 
          mode = Pmode;
9689 
          type = build_pointer_type (type);
9690 
        }
9691 
 
9692 
       parm_rtx = s390_function_arg (cum, mode, type, 0);
9693 
 
9694 
       s390_function_arg_advance (cum, mode, type, 0);
9695 
 
9696 
       if (!parm_rtx)
9697 
         continue;
9698 
 
9699 
       if (REG_P (parm_rtx))
9700 
         {
9701 
           for (reg = 0;
9702 
                reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9703 
                reg++)
9704 
             if (!call_used_regs[reg + REGNO (parm_rtx)])
9705 
               return true;
9706 
         }
9707 
 
9708 
       if (GET_CODE (parm_rtx) == PARALLEL)
9709 
         {
9710 
           int i;
9711 
 
9712 
           for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
9713 
             {
9714 
               rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9715 
 
9716 
               gcc_assert (REG_P (r));
9717 
 
9718 
               for (reg = 0;
9719 
                    reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
9720 
                    reg++)
9721 
                 if (!call_used_regs[reg + REGNO (r)])
9722 
                   return true;
9723 
             }
9724 
         }
9725 
 
9726 
    }
9727 
  return false;
9728 
}
9729 
 
9730 
/* Return true if the given call expression can be
9731 
   turned into a sibling call.
9732 
   DECL holds the declaration of the function to be called whereas
9733 
   EXP is the call expression itself.  */
9734 
 
9735 
static bool
9736 
s390_function_ok_for_sibcall (tree decl, tree exp)
9737 
{
9738 
  /* The TPF epilogue uses register 1.  */
9739 
  if (TARGET_TPF_PROFILING)
9740 
    return false;
9741 
 
9742 
  /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9743 
     which would have to be restored before the sibcall.  */
9744 
  if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9745 
    return false;
9746 
 
9747 
  /* Register 6 on s390 is available as an argument register but unfortunately
9748 
     "caller saved". This makes functions needing this register for arguments
9749 
     not suitable for sibcalls.  */
9750 
  return !s390_call_saved_register_used (exp);
9751 
}
9752 
 
9753 
/* Return the fixed registers used for condition codes.  */
9754 
 
9755 
static bool
9756 
s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9757 
{
9758 
  *p1 = CC_REGNUM;
9759 
  *p2 = INVALID_REGNUM;
9760 
 
9761 
  return true;
9762 
}
9763 
 
9764 
/* This function is used by the call expanders of the machine description.
9765 
   It emits the call insn itself together with the necessary operations
9766 
   to adjust the target address and returns the emitted insn.
9767 
   ADDR_LOCATION is the target address rtx
9768 
   TLS_CALL the location of the thread-local symbol
9769 
   RESULT_REG the register where the result of the call should be stored
9770 
   RETADDR_REG the register where the return address should be stored
9771 
               If this parameter is NULL_RTX the call is considered
9772 
               to be a sibling call.  */
9773 
 
9774 
rtx
9775 
s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9776 
                rtx retaddr_reg)
9777 
{
9778 
  bool plt_call = false;
9779 
  rtx insn;
9780 
  rtx call;
9781 
  rtx clobber;
9782 
  rtvec vec;
9783 
 
9784 
  /* Direct function calls need special treatment.  */
9785 
  if (GET_CODE (addr_location) == SYMBOL_REF)
9786 
    {
9787 
      /* When calling a global routine in PIC mode, we must
9788 
         replace the symbol itself with the PLT stub.  */
9789 
      if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9790 
        {
9791 
          if (retaddr_reg != NULL_RTX)
9792 
            {
9793 
              addr_location = gen_rtx_UNSPEC (Pmode,
9794 
                                              gen_rtvec (1, addr_location),
9795 
                                              UNSPEC_PLT);
9796 
              addr_location = gen_rtx_CONST (Pmode, addr_location);
9797 
              plt_call = true;
9798 
            }
9799 
          else
9800 
            /* For -fpic code the PLT entries might use r12 which is
9801 
               call-saved.  Therefore we cannot do a sibcall when
9802 
               calling directly using a symbol ref.  When reaching
9803 
               this point we decided (in s390_function_ok_for_sibcall)
9804 
               to do a sibcall for a function pointer but one of the
9805 
               optimizers was able to get rid of the function pointer
9806 
               by propagating the symbol ref into the call.  This
9807 
               optimization is illegal for S/390 so we turn the direct
9808 
               call into a indirect call again.  */
9809 
            addr_location = force_reg (Pmode, addr_location);
9810 
        }
9811 
 
9812 
      /* Unless we can use the bras(l) insn, force the
9813 
         routine address into a register.  */
9814 
      if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9815 
        {
9816 
          if (flag_pic)
9817 
            addr_location = legitimize_pic_address (addr_location, 0);
9818 
          else
9819 
            addr_location = force_reg (Pmode, addr_location);
9820 
        }
9821 
    }
9822 
 
9823 
  /* If it is already an indirect call or the code above moved the
9824 
     SYMBOL_REF to somewhere else make sure the address can be found in
9825 
     register 1.  */
9826 
  if (retaddr_reg == NULL_RTX
9827 
      && GET_CODE (addr_location) != SYMBOL_REF
9828 
      && !plt_call)
9829 
    {
9830 
      emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9831 
      addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9832 
    }
9833 
 
9834 
  addr_location = gen_rtx_MEM (QImode, addr_location);
9835 
  call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9836 
 
9837 
  if (result_reg != NULL_RTX)
9838 
    call = gen_rtx_SET (VOIDmode, result_reg, call);
9839 
 
9840 
  if (retaddr_reg != NULL_RTX)
9841 
    {
9842 
      clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9843 
 
9844 
      if (tls_call != NULL_RTX)
9845 
        vec = gen_rtvec (3, call, clobber,
9846 
                         gen_rtx_USE (VOIDmode, tls_call));
9847 
      else
9848 
        vec = gen_rtvec (2, call, clobber);
9849 
 
9850 
      call = gen_rtx_PARALLEL (VOIDmode, vec);
9851 
    }
9852 
 
9853 
  insn = emit_call_insn (call);
9854 
 
9855 
  /* 31-bit PLT stubs and tls calls use the GOT register implicitly.  */
9856 
  if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9857 
    {
9858 
      /* s390_function_ok_for_sibcall should
9859 
         have denied sibcalls in this case.  */
9860 
      gcc_assert (retaddr_reg != NULL_RTX);
9861 
      use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
9862 
    }
9863 
  return insn;
9864 
}
9865 
 
9866 
/* Implement TARGET_CONDITIONAL_REGISTER_USAGE.  */
9867 
 
9868 
static void
9869 
s390_conditional_register_usage (void)
9870 
{
9871 
  int i;
9872 
 
9873 
  if (flag_pic)
9874 
    {
9875 
      fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9876 
      call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9877 
    }
9878 
  if (TARGET_CPU_ZARCH)
9879 
    {
9880 
      fixed_regs[BASE_REGNUM] = 0;
9881 
      call_used_regs[BASE_REGNUM] = 0;
9882 
      fixed_regs[RETURN_REGNUM] = 0;
9883 
      call_used_regs[RETURN_REGNUM] = 0;
9884 
    }
9885 
  if (TARGET_64BIT)
9886 
    {
9887 
      for (i = 24; i < 32; i++)
9888 
        call_used_regs[i] = call_really_used_regs[i] = 0;
9889 
    }
9890 
  else
9891 
    {
9892 
      for (i = 18; i < 20; i++)
9893 
        call_used_regs[i] = call_really_used_regs[i] = 0;
9894 
    }
9895 
 
9896 
  if (TARGET_SOFT_FLOAT)
9897 
    {
9898 
      for (i = 16; i < 32; i++)
9899 
        call_used_regs[i] = fixed_regs[i] = 1;
9900 
    }
9901 
}
9902 
 
9903 
/* Corresponding function to eh_return expander.  */
9904 
 
9905 
static GTY(()) rtx s390_tpf_eh_return_symbol;
9906 
void
9907 
s390_emit_tpf_eh_return (rtx target)
9908 
{
9909 
  rtx insn, reg;
9910 
 
9911 
  if (!s390_tpf_eh_return_symbol)
9912 
    s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9913 
 
9914 
  reg = gen_rtx_REG (Pmode, 2);
9915 
 
9916 
  emit_move_insn (reg, target);
9917 
  insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9918 
                                     gen_rtx_REG (Pmode, RETURN_REGNUM));
9919 
  use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9920 
 
9921 
  emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9922 
}
9923 
 
9924 
/* Rework the prologue/epilogue to avoid saving/restoring
9925 
   registers unnecessarily.  */
9926 
 
9927 
static void
9928 
s390_optimize_prologue (void)
9929 
{
9930 
  rtx insn, new_insn, next_insn;
9931 
 
9932 
  /* Do a final recompute of the frame-related data.  */
9933 
 
9934 
  s390_update_frame_layout ();
9935 
 
9936 
  /* If all special registers are in fact used, there's nothing we
9937 
     can do, so no point in walking the insn list.  */
9938 
 
9939 
  if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9940 
      && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9941 
      && (TARGET_CPU_ZARCH
9942 
          || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9943 
              && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9944 
    return;
9945 
 
9946 
  /* Search for prologue/epilogue insns and replace them.  */
9947 
 
9948 
  for (insn = get_insns (); insn; insn = next_insn)
9949 
    {
9950 
      int first, last, off;
9951 
      rtx set, base, offset;
9952 
 
9953 
      next_insn = NEXT_INSN (insn);
9954 
 
9955 
      if (GET_CODE (insn) != INSN)
9956 
        continue;
9957 
 
9958 
      if (GET_CODE (PATTERN (insn)) == PARALLEL
9959 
          && store_multiple_operation (PATTERN (insn), VOIDmode))
9960 
        {
9961 
          set = XVECEXP (PATTERN (insn), 0, 0);
9962 
          first = REGNO (SET_SRC (set));
9963 
          last = first + XVECLEN (PATTERN (insn), 0) - 1;
9964 
          offset = const0_rtx;
9965 
          base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9966 
          off = INTVAL (offset);
9967 
 
9968 
          if (GET_CODE (base) != REG || off < 0)
9969 
            continue;
9970 
          if (cfun_frame_layout.first_save_gpr != -1
9971 
              && (cfun_frame_layout.first_save_gpr < first
9972 
                  || cfun_frame_layout.last_save_gpr > last))
9973 
            continue;
9974 
          if (REGNO (base) != STACK_POINTER_REGNUM
9975 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9976 
            continue;
9977 
          if (first > BASE_REGNUM || last < BASE_REGNUM)
9978 
            continue;
9979 
 
9980 
          if (cfun_frame_layout.first_save_gpr != -1)
9981 
            {
9982 
              new_insn  = save_gprs (base,
9983 
                                     off + (cfun_frame_layout.first_save_gpr
9984 
                                            - first) * UNITS_PER_LONG,
9985 
                                     cfun_frame_layout.first_save_gpr,
9986 
                                     cfun_frame_layout.last_save_gpr);
9987 
              new_insn = emit_insn_before (new_insn, insn);
9988 
              INSN_ADDRESSES_NEW (new_insn, -1);
9989 
            }
9990 
 
9991 
          remove_insn (insn);
9992 
          continue;
9993 
        }
9994 
 
9995 
      if (cfun_frame_layout.first_save_gpr == -1
9996 
          && GET_CODE (PATTERN (insn)) == SET
9997 
          && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9998 
          && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9999 
              || (!TARGET_CPU_ZARCH
10000 
                  && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
10001 
          && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
10002 
        {
10003 
          set = PATTERN (insn);
10004 
          first = REGNO (SET_SRC (set));
10005 
          offset = const0_rtx;
10006 
          base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10007 
          off = INTVAL (offset);
10008 
 
10009 
          if (GET_CODE (base) != REG || off < 0)
10010 
            continue;
10011 
          if (REGNO (base) != STACK_POINTER_REGNUM
10012 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10013 
            continue;
10014 
 
10015 
          remove_insn (insn);
10016 
          continue;
10017 
        }
10018 
 
10019 
      if (GET_CODE (PATTERN (insn)) == PARALLEL
10020 
          && load_multiple_operation (PATTERN (insn), VOIDmode))
10021 
        {
10022 
          set = XVECEXP (PATTERN (insn), 0, 0);
10023 
          first = REGNO (SET_DEST (set));
10024 
          last = first + XVECLEN (PATTERN (insn), 0) - 1;
10025 
          offset = const0_rtx;
10026 
          base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10027 
          off = INTVAL (offset);
10028 
 
10029 
          if (GET_CODE (base) != REG || off < 0)
10030 
            continue;
10031 
          if (cfun_frame_layout.first_restore_gpr != -1
10032 
              && (cfun_frame_layout.first_restore_gpr < first
10033 
                  || cfun_frame_layout.last_restore_gpr > last))
10034 
            continue;
10035 
          if (REGNO (base) != STACK_POINTER_REGNUM
10036 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10037 
            continue;
10038 
          if (first > BASE_REGNUM || last < BASE_REGNUM)
10039 
            continue;
10040 
 
10041 
          if (cfun_frame_layout.first_restore_gpr != -1)
10042 
            {
10043 
              new_insn = restore_gprs (base,
10044 
                                       off + (cfun_frame_layout.first_restore_gpr
10045 
                                              - first) * UNITS_PER_LONG,
10046 
                                       cfun_frame_layout.first_restore_gpr,
10047 
                                       cfun_frame_layout.last_restore_gpr);
10048 
              new_insn = emit_insn_before (new_insn, insn);
10049 
              INSN_ADDRESSES_NEW (new_insn, -1);
10050 
            }
10051 
 
10052 
          remove_insn (insn);
10053 
          continue;
10054 
        }
10055 
 
10056 
      if (cfun_frame_layout.first_restore_gpr == -1
10057 
          && GET_CODE (PATTERN (insn)) == SET
10058 
          && GET_CODE (SET_DEST (PATTERN (insn))) == REG
10059 
          && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
10060 
              || (!TARGET_CPU_ZARCH
10061 
                  && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
10062 
          && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
10063 
        {
10064 
          set = PATTERN (insn);
10065 
          first = REGNO (SET_DEST (set));
10066 
          offset = const0_rtx;
10067 
          base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10068 
          off = INTVAL (offset);
10069 
 
10070 
          if (GET_CODE (base) != REG || off < 0)
10071 
            continue;
10072 
          if (REGNO (base) != STACK_POINTER_REGNUM
10073 
              && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10074 
            continue;
10075 
 
10076 
          remove_insn (insn);
10077 
          continue;
10078 
        }
10079 
    }
10080 
}
10081 
 
10082 
/* On z10 and later the dynamic branch prediction must see the
10083 
   backward jump within a certain windows.  If not it falls back to
10084 
   the static prediction.  This function rearranges the loop backward
10085 
   branch in a way which makes the static prediction always correct.
10086 
   The function returns true if it added an instruction.  */
10087 
static bool
10088 
s390_fix_long_loop_prediction (rtx insn)
10089 
{
10090 
  rtx set = single_set (insn);
10091 
  rtx code_label, label_ref, new_label;
10092 
  rtx uncond_jump;
10093 
  rtx cur_insn;
10094 
  rtx tmp;
10095 
  int distance;
10096 
 
10097 
  /* This will exclude branch on count and branch on index patterns
10098 
     since these are correctly statically predicted.  */
10099 
  if (!set
10100 
      || SET_DEST (set) != pc_rtx
10101 
      || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
10102 
    return false;
10103 
 
10104 
  label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
10105 
               XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
10106 
 
10107 
  gcc_assert (GET_CODE (label_ref) == LABEL_REF);
10108 
 
10109 
  code_label = XEXP (label_ref, 0);
10110 
 
10111 
  if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
10112 
      || INSN_ADDRESSES (INSN_UID (insn)) == -1
10113 
      || (INSN_ADDRESSES (INSN_UID (insn))
10114 
          - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
10115 
    return false;
10116 
 
10117 
  for (distance = 0, cur_insn = PREV_INSN (insn);
10118 
       distance < PREDICT_DISTANCE - 6;
10119 
       distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
10120 
    if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
10121 
      return false;
10122 
 
10123 
  new_label = gen_label_rtx ();
10124 
  uncond_jump = emit_jump_insn_after (
10125 
                  gen_rtx_SET (VOIDmode, pc_rtx,
10126 
                               gen_rtx_LABEL_REF (VOIDmode, code_label)),
10127 
                  insn);
10128 
  emit_label_after (new_label, uncond_jump);
10129 
 
10130 
  tmp = XEXP (SET_SRC (set), 1);
10131 
  XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
10132 
  XEXP (SET_SRC (set), 2) = tmp;
10133 
  INSN_CODE (insn) = -1;
10134 
 
10135 
  XEXP (label_ref, 0) = new_label;
10136 
  JUMP_LABEL (insn) = new_label;
10137 
  JUMP_LABEL (uncond_jump) = code_label;
10138 
 
10139 
  return true;
10140 
}
10141 
 
10142 
/* Returns 1 if INSN reads the value of REG for purposes not related
10143 
   to addressing of memory, and 0 otherwise.  */
10144 
static int
10145 
s390_non_addr_reg_read_p (rtx reg, rtx insn)
10146 
{
10147 
  return reg_referenced_p (reg, PATTERN (insn))
10148 
    && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
10149 
}
10150 
 
10151 
/* Starting from INSN find_cond_jump looks downwards in the insn
10152 
   stream for a single jump insn which is the last user of the
10153 
   condition code set in INSN.  */
10154 
static rtx
10155 
find_cond_jump (rtx insn)
10156 
{
10157 
  for (; insn; insn = NEXT_INSN (insn))
10158 
    {
10159 
      rtx ite, cc;
10160 
 
10161 
      if (LABEL_P (insn))
10162 
        break;
10163 
 
10164 
      if (!JUMP_P (insn))
10165 
        {
10166 
          if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
10167 
            break;
10168 
          continue;
10169 
        }
10170 
 
10171 
      /* This will be triggered by a return.  */
10172 
      if (GET_CODE (PATTERN (insn)) != SET)
10173 
        break;
10174 
 
10175 
      gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
10176 
      ite = SET_SRC (PATTERN (insn));
10177 
 
10178 
      if (GET_CODE (ite) != IF_THEN_ELSE)
10179 
        break;
10180 
 
10181 
      cc = XEXP (XEXP (ite, 0), 0);
10182 
      if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
10183 
        break;
10184 
 
10185 
      if (find_reg_note (insn, REG_DEAD, cc))
10186 
        return insn;
10187 
      break;
10188 
    }
10189 
 
10190 
  return NULL_RTX;
10191 
}
10192 
 
10193 
/* Swap the condition in COND and the operands in OP0 and OP1 so that
10194 
   the semantics does not change.  If NULL_RTX is passed as COND the
10195 
   function tries to find the conditional jump starting with INSN.  */
10196 
static void
10197 
s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
10198 
{
10199 
  rtx tmp = *op0;
10200 
 
10201 
  if (cond == NULL_RTX)
10202 
    {
10203 
      rtx jump = find_cond_jump (NEXT_INSN (insn));
10204 
      jump = jump ? single_set (jump) : NULL_RTX;
10205 
 
10206 
      if (jump == NULL_RTX)
10207 
        return;
10208 
 
10209 
      cond = XEXP (XEXP (jump, 1), 0);
10210 
    }
10211 
 
10212 
  *op0 = *op1;
10213 
  *op1 = tmp;
10214 
  PUT_CODE (cond, swap_condition (GET_CODE (cond)));
10215 
}
10216 
 
10217 
/* On z10, instructions of the compare-and-branch family have the
10218 
   property to access the register occurring as second operand with
10219 
   its bits complemented.  If such a compare is grouped with a second
10220 
   instruction that accesses the same register non-complemented, and
10221 
   if that register's value is delivered via a bypass, then the
10222 
   pipeline recycles, thereby causing significant performance decline.
10223 
   This function locates such situations and exchanges the two
10224 
   operands of the compare.  The function return true whenever it
10225 
   added an insn.  */
10226 
static bool
10227 
s390_z10_optimize_cmp (rtx insn)
10228 
{
10229 
  rtx prev_insn, next_insn;
10230 
  bool insn_added_p = false;
10231 
  rtx cond, *op0, *op1;
10232 
 
10233 
  if (GET_CODE (PATTERN (insn)) == PARALLEL)
10234 
    {
10235 
      /* Handle compare and branch and branch on count
10236 
         instructions.  */
10237 
      rtx pattern = single_set (insn);
10238 
 
10239 
      if (!pattern
10240 
          || SET_DEST (pattern) != pc_rtx
10241 
          || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
10242 
        return false;
10243 
 
10244 
      cond = XEXP (SET_SRC (pattern), 0);
10245 
      op0 = &XEXP (cond, 0);
10246 
      op1 = &XEXP (cond, 1);
10247 
    }
10248 
  else if (GET_CODE (PATTERN (insn)) == SET)
10249 
    {
10250 
      rtx src, dest;
10251 
 
10252 
      /* Handle normal compare instructions.  */
10253 
      src = SET_SRC (PATTERN (insn));
10254 
      dest = SET_DEST (PATTERN (insn));
10255 
 
10256 
      if (!REG_P (dest)
10257 
          || !CC_REGNO_P (REGNO (dest))
10258 
          || GET_CODE (src) != COMPARE)
10259 
        return false;
10260 
 
10261 
      /* s390_swap_cmp will try to find the conditional
10262 
         jump when passing NULL_RTX as condition.  */
10263 
      cond = NULL_RTX;
10264 
      op0 = &XEXP (src, 0);
10265 
      op1 = &XEXP (src, 1);
10266 
    }
10267 
  else
10268 
    return false;
10269 
 
10270 
  if (!REG_P (*op0) || !REG_P (*op1))
10271 
    return false;
10272 
 
10273 
  if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
10274 
    return false;
10275 
 
10276 
  /* Swap the COMPARE arguments and its mask if there is a
10277 
     conflicting access in the previous insn.  */
10278 
  prev_insn = prev_active_insn (insn);
10279 
  if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10280 
      && reg_referenced_p (*op1, PATTERN (prev_insn)))
10281 
    s390_swap_cmp (cond, op0, op1, insn);
10282 
 
10283 
  /* Check if there is a conflict with the next insn. If there
10284 
     was no conflict with the previous insn, then swap the
10285 
     COMPARE arguments and its mask.  If we already swapped
10286 
     the operands, or if swapping them would cause a conflict
10287 
     with the previous insn, issue a NOP after the COMPARE in
10288 
     order to separate the two instuctions.  */
10289 
  next_insn = next_active_insn (insn);
10290 
  if (next_insn != NULL_RTX && INSN_P (next_insn)
10291 
      && s390_non_addr_reg_read_p (*op1, next_insn))
10292 
    {
10293 
      if (prev_insn != NULL_RTX && INSN_P (prev_insn)
10294 
          && s390_non_addr_reg_read_p (*op0, prev_insn))
10295 
        {
10296 
          if (REGNO (*op1) == 0)
10297 
            emit_insn_after (gen_nop1 (), insn);
10298 
          else
10299 
            emit_insn_after (gen_nop (), insn);
10300 
          insn_added_p = true;
10301 
        }
10302 
      else
10303 
        s390_swap_cmp (cond, op0, op1, insn);
10304 
    }
10305 
  return insn_added_p;
10306 
}
10307 
 
10308 
/* Perform machine-dependent processing.  */
10309 
 
10310 
static void
10311 
s390_reorg (void)
10312 
{
10313 
  bool pool_overflow = false;
10314 
 
10315 
  /* Make sure all splits have been performed; splits after
10316 
     machine_dependent_reorg might confuse insn length counts.  */
10317 
  split_all_insns_noflow ();
10318 
 
10319 
  /* Install the main literal pool and the associated base
10320 
     register load insns.
10321 
 
10322 
     In addition, there are two problematic situations we need
10323 
     to correct:
10324 
 
10325 
     - the literal pool might be > 4096 bytes in size, so that
10326 
       some of its elements cannot be directly accessed
10327 
 
10328 
     - a branch target might be > 64K away from the branch, so that
10329 
       it is not possible to use a PC-relative instruction.
10330 
 
10331 
     To fix those, we split the single literal pool into multiple
10332 
     pool chunks, reloading the pool base register at various
10333 
     points throughout the function to ensure it always points to
10334 
     the pool chunk the following code expects, and / or replace
10335 
     PC-relative branches by absolute branches.
10336 
 
10337 
     However, the two problems are interdependent: splitting the
10338 
     literal pool can move a branch further away from its target,
10339 
     causing the 64K limit to overflow, and on the other hand,
10340 
     replacing a PC-relative branch by an absolute branch means
10341 
     we need to put the branch target address into the literal
10342 
     pool, possibly causing it to overflow.
10343 
 
10344 
     So, we loop trying to fix up both problems until we manage
10345 
     to satisfy both conditions at the same time.  Note that the
10346 
     loop is guaranteed to terminate as every pass of the loop
10347 
     strictly decreases the total number of PC-relative branches
10348 
     in the function.  (This is not completely true as there
10349 
     might be branch-over-pool insns introduced by chunkify_start.
10350 
     Those never need to be split however.)  */
10351 
 
10352 
  for (;;)
10353 
    {
10354 
      struct constant_pool *pool = NULL;
10355 
 
10356 
      /* Collect the literal pool.  */
10357 
      if (!pool_overflow)
10358 
        {
10359 
          pool = s390_mainpool_start ();
10360 
          if (!pool)
10361 
            pool_overflow = true;
10362 
        }
10363 
 
10364 
      /* If literal pool overflowed, start to chunkify it.  */
10365 
      if (pool_overflow)
10366 
        pool = s390_chunkify_start ();
10367 
 
10368 
      /* Split out-of-range branches.  If this has created new
10369 
         literal pool entries, cancel current chunk list and
10370 
         recompute it.  zSeries machines have large branch
10371 
         instructions, so we never need to split a branch.  */
10372 
      if (!TARGET_CPU_ZARCH && s390_split_branches ())
10373 
        {
10374 
          if (pool_overflow)
10375 
            s390_chunkify_cancel (pool);
10376 
          else
10377 
            s390_mainpool_cancel (pool);
10378 
 
10379 
          continue;
10380 
        }
10381 
 
10382 
      /* If we made it up to here, both conditions are satisfied.
10383 
         Finish up literal pool related changes.  */
10384 
      if (pool_overflow)
10385 
        s390_chunkify_finish (pool);
10386 
      else
10387 
        s390_mainpool_finish (pool);
10388 
 
10389 
      /* We're done splitting branches.  */
10390 
      cfun->machine->split_branches_pending_p = false;
10391 
      break;
10392 
    }
10393 
 
10394 
  /* Generate out-of-pool execute target insns.  */
10395 
  if (TARGET_CPU_ZARCH)
10396 
    {
10397 
      rtx insn, label, target;
10398 
 
10399 
      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10400 
        {
10401 
          label = s390_execute_label (insn);
10402 
          if (!label)
10403 
            continue;
10404 
 
10405 
          gcc_assert (label != const0_rtx);
10406 
 
10407 
          target = emit_label (XEXP (label, 0));
10408 
          INSN_ADDRESSES_NEW (target, -1);
10409 
 
10410 
          target = emit_insn (s390_execute_target (insn));
10411 
          INSN_ADDRESSES_NEW (target, -1);
10412 
        }
10413 
    }
10414 
 
10415 
  /* Try to optimize prologue and epilogue further.  */
10416 
  s390_optimize_prologue ();
10417 
 
10418 
  /* Walk over the insns and do some >=z10 specific changes.  */
10419 
  if (s390_tune == PROCESSOR_2097_Z10
10420 
      || s390_tune == PROCESSOR_2817_Z196)
10421 
    {
10422 
      rtx insn;
10423 
      bool insn_added_p = false;
10424 
 
10425 
      /* The insn lengths and addresses have to be up to date for the
10426 
         following manipulations.  */
10427 
      shorten_branches (get_insns ());
10428 
 
10429 
      for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10430 
        {
10431 
          if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10432 
            continue;
10433 
 
10434 
          if (JUMP_P (insn))
10435 
            insn_added_p |= s390_fix_long_loop_prediction (insn);
10436 
 
10437 
          if ((GET_CODE (PATTERN (insn)) == PARALLEL
10438 
               || GET_CODE (PATTERN (insn)) == SET)
10439 
              && s390_tune == PROCESSOR_2097_Z10)
10440 
            insn_added_p |= s390_z10_optimize_cmp (insn);
10441 
        }
10442 
 
10443 
      /* Adjust branches if we added new instructions.  */
10444 
      if (insn_added_p)
10445 
        shorten_branches (get_insns ());
10446 
    }
10447 
}
10448 
 
10449 
/* Return true if INSN is a fp load insn writing register REGNO.  */
10450 
static inline bool
10451 
s390_fpload_toreg (rtx insn, unsigned int regno)
10452 
{
10453 
  rtx set;
10454 
  enum attr_type flag = s390_safe_attr_type (insn);
10455 
 
10456 
  if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
10457 
    return false;
10458 
 
10459 
  set = single_set (insn);
10460 
 
10461 
  if (set == NULL_RTX)
10462 
    return false;
10463 
 
10464 
  if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
10465 
    return false;
10466 
 
10467 
  if (REGNO (SET_DEST (set)) != regno)
10468 
    return false;
10469 
 
10470 
  return true;
10471 
}
10472 
 
10473 
/* This value describes the distance to be avoided between an
10474 
   aritmetic fp instruction and an fp load writing the same register.
10475 
   Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10476 
   fine but the exact value has to be avoided. Otherwise the FP
10477 
   pipeline will throw an exception causing a major penalty.  */
10478 
#define Z10_EARLYLOAD_DISTANCE 7
10479 
 
10480 
/* Rearrange the ready list in order to avoid the situation described
10481 
   for Z10_EARLYLOAD_DISTANCE.  A problematic load instruction is
10482 
   moved to the very end of the ready list.  */
10483 
static void
10484 
s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
10485 
{
10486 
  unsigned int regno;
10487 
  int nready = *nready_p;
10488 
  rtx tmp;
10489 
  int i;
10490 
  rtx insn;
10491 
  rtx set;
10492 
  enum attr_type flag;
10493 
  int distance;
10494 
 
10495 
  /* Skip DISTANCE - 1 active insns.  */
10496 
  for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
10497 
       distance > 0 && insn != NULL_RTX;
10498 
       distance--, insn = prev_active_insn (insn))
10499 
    if (CALL_P (insn) || JUMP_P (insn))
10500 
      return;
10501 
 
10502 
  if (insn == NULL_RTX)
10503 
    return;
10504 
 
10505 
  set = single_set (insn);
10506 
 
10507 
  if (set == NULL_RTX || !REG_P (SET_DEST (set))
10508 
      || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
10509 
    return;
10510 
 
10511 
  flag = s390_safe_attr_type (insn);
10512 
 
10513 
  if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
10514 
    return;
10515 
 
10516 
  regno = REGNO (SET_DEST (set));
10517 
  i = nready - 1;
10518 
 
10519 
  while (!s390_fpload_toreg (ready[i], regno) && i > 0)
10520 
    i--;
10521 
 
10522 
  if (!i)
10523 
    return;
10524 
 
10525 
  tmp = ready[i];
10526 
  memmove (&ready[1], &ready[0], sizeof (rtx) * i);
10527 
  ready[0] = tmp;
10528 
}
10529 
 
10530 
/* This function is called via hook TARGET_SCHED_REORDER before
10531 
   issueing one insn from list READY which contains *NREADYP entries.
10532 
   For target z10 it reorders load instructions to avoid early load
10533 
   conflicts in the floating point pipeline  */
10534 
static int
10535 
s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10536 
                    rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
10537 
{
10538 
  if (s390_tune == PROCESSOR_2097_Z10)
10539 
    if (reload_completed && *nreadyp > 1)
10540 
      s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
10541 
 
10542 
  return s390_issue_rate ();
10543 
}
10544 
 
10545 
/* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10546 
   the scheduler has issued INSN.  It stores the last issued insn into
10547 
   last_scheduled_insn in order to make it available for
10548 
   s390_sched_reorder.  */
10549 
static int
10550 
s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED,
10551 
                           int verbose ATTRIBUTE_UNUSED,
10552 
                         rtx insn, int more)
10553 
{
10554 
  last_scheduled_insn = insn;
10555 
 
10556 
  if (GET_CODE (PATTERN (insn)) != USE
10557 
      && GET_CODE (PATTERN (insn)) != CLOBBER)
10558 
    return more - 1;
10559 
  else
10560 
    return more;
10561 
}
10562 
 
10563 
static void
10564 
s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
10565 
                 int verbose ATTRIBUTE_UNUSED,
10566 
                 int max_ready ATTRIBUTE_UNUSED)
10567 
{
10568 
  last_scheduled_insn = NULL_RTX;
10569 
}
10570 
 
10571 
/* This function checks the whole of insn X for memory references. The
10572 
   function always returns zero because the framework it is called
10573 
   from would stop recursively analyzing the insn upon a return value
10574 
   other than zero. The real result of this function is updating
10575 
   counter variable MEM_COUNT.  */
10576 
static int
10577 
check_dpu (rtx *x, unsigned *mem_count)
10578 
{
10579 
  if (*x != NULL_RTX && MEM_P (*x))
10580 
    (*mem_count)++;
10581 
  return 0;
10582 
}
10583 
 
10584 
/* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10585 
   a new number struct loop *loop should be unrolled if tuned for cpus with
10586 
   a built-in stride prefetcher.
10587 
   The loop is analyzed for memory accesses by calling check_dpu for
10588 
   each rtx of the loop. Depending on the loop_depth and the amount of
10589 
   memory accesses a new number <=nunroll is returned to improve the
10590 
   behaviour of the hardware prefetch unit.  */
10591 
static unsigned
10592 
s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
10593 
{
10594 
  basic_block *bbs;
10595 
  rtx insn;
10596 
  unsigned i;
10597 
  unsigned mem_count = 0;
10598 
 
10599 
  if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196)
10600 
    return nunroll;
10601 
 
10602 
  /* Count the number of memory references within the loop body.  */
10603 
  bbs = get_loop_body (loop);
10604 
  for (i = 0; i < loop->num_nodes; i++)
10605 
    {
10606 
      for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
10607 
        if (INSN_P (insn) && INSN_CODE (insn) != -1)
10608 
            for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
10609 
    }
10610 
  free (bbs);
10611 
 
10612 
  /* Prevent division by zero, and we do not need to adjust nunroll in this case.  */
10613 
  if (mem_count == 0)
10614 
    return nunroll;
10615 
 
10616 
  switch (loop_depth(loop))
10617 
    {
10618 
    case 1:
10619 
      return MIN (nunroll, 28 / mem_count);
10620 
    case 2:
10621 
      return MIN (nunroll, 22 / mem_count);
10622 
    default:
10623 
      return MIN (nunroll, 16 / mem_count);
10624 
    }
10625 
}
10626 
 
10627 
/* Initialize GCC target structure.  */
10628 
 
10629 
#undef  TARGET_ASM_ALIGNED_HI_OP
10630 
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10631 
#undef  TARGET_ASM_ALIGNED_DI_OP
10632 
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10633 
#undef  TARGET_ASM_INTEGER
10634 
#define TARGET_ASM_INTEGER s390_assemble_integer
10635 
 
10636 
#undef  TARGET_ASM_OPEN_PAREN
10637 
#define TARGET_ASM_OPEN_PAREN ""
10638 
 
10639 
#undef  TARGET_ASM_CLOSE_PAREN
10640 
#define TARGET_ASM_CLOSE_PAREN ""
10641 
 
10642 
#undef TARGET_OPTION_OVERRIDE
10643 
#define TARGET_OPTION_OVERRIDE s390_option_override
10644 
 
10645 
#undef  TARGET_ENCODE_SECTION_INFO
10646 
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10647 
 
10648 
#undef TARGET_SCALAR_MODE_SUPPORTED_P
10649 
#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10650 
 
10651 
#ifdef HAVE_AS_TLS
10652 
#undef TARGET_HAVE_TLS
10653 
#define TARGET_HAVE_TLS true
10654 
#endif
10655 
#undef TARGET_CANNOT_FORCE_CONST_MEM
10656 
#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10657 
 
10658 
#undef TARGET_DELEGITIMIZE_ADDRESS
10659 
#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10660 
 
10661 
#undef TARGET_LEGITIMIZE_ADDRESS
10662 
#define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10663 
 
10664 
#undef TARGET_RETURN_IN_MEMORY
10665 
#define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10666 
 
10667 
#undef  TARGET_INIT_BUILTINS
10668 
#define TARGET_INIT_BUILTINS s390_init_builtins
10669 
#undef  TARGET_EXPAND_BUILTIN
10670 
#define TARGET_EXPAND_BUILTIN s390_expand_builtin
10671 
 
10672 
#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10673 
#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10674 
 
10675 
#undef TARGET_ASM_OUTPUT_MI_THUNK
10676 
#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10677 
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10678 
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10679 
 
10680 
#undef  TARGET_SCHED_ADJUST_PRIORITY
10681 
#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10682 
#undef TARGET_SCHED_ISSUE_RATE
10683 
#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10684 
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10685 
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10686 
 
10687 
#undef TARGET_SCHED_VARIABLE_ISSUE
10688 
#define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10689 
#undef TARGET_SCHED_REORDER
10690 
#define TARGET_SCHED_REORDER s390_sched_reorder
10691 
#undef TARGET_SCHED_INIT
10692 
#define TARGET_SCHED_INIT s390_sched_init
10693 
 
10694 
#undef TARGET_CANNOT_COPY_INSN_P
10695 
#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10696 
#undef TARGET_RTX_COSTS
10697 
#define TARGET_RTX_COSTS s390_rtx_costs
10698 
#undef TARGET_ADDRESS_COST
10699 
#define TARGET_ADDRESS_COST s390_address_cost
10700 
#undef TARGET_REGISTER_MOVE_COST
10701 
#define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10702 
#undef TARGET_MEMORY_MOVE_COST
10703 
#define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10704 
 
10705 
#undef TARGET_MACHINE_DEPENDENT_REORG
10706 
#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10707 
 
10708 
#undef TARGET_VALID_POINTER_MODE
10709 
#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10710 
 
10711 
#undef TARGET_BUILD_BUILTIN_VA_LIST
10712 
#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10713 
#undef TARGET_EXPAND_BUILTIN_VA_START
10714 
#define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10715 
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
10716 
#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10717 
 
10718 
#undef TARGET_PROMOTE_FUNCTION_MODE
10719 
#define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10720 
#undef TARGET_PASS_BY_REFERENCE
10721 
#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10722 
 
10723 
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
10724 
#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10725 
#undef TARGET_FUNCTION_ARG
10726 
#define TARGET_FUNCTION_ARG s390_function_arg
10727 
#undef TARGET_FUNCTION_ARG_ADVANCE
10728 
#define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10729 
#undef TARGET_FUNCTION_VALUE
10730 
#define TARGET_FUNCTION_VALUE s390_function_value
10731 
#undef TARGET_LIBCALL_VALUE
10732 
#define TARGET_LIBCALL_VALUE s390_libcall_value
10733 
 
10734 
#undef TARGET_FIXED_CONDITION_CODE_REGS
10735 
#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10736 
 
10737 
#undef TARGET_CC_MODES_COMPATIBLE
10738 
#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10739 
 
10740 
#undef TARGET_INVALID_WITHIN_DOLOOP
10741 
#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10742 
 
10743 
#ifdef HAVE_AS_TLS
10744 
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10745 
#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10746 
#endif
10747 
 
10748 
#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10749 
#undef TARGET_MANGLE_TYPE
10750 
#define TARGET_MANGLE_TYPE s390_mangle_type
10751 
#endif
10752 
 
10753 
#undef TARGET_SCALAR_MODE_SUPPORTED_P
10754 
#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10755 
 
10756 
#undef  TARGET_PREFERRED_RELOAD_CLASS
10757 
#define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10758 
 
10759 
#undef TARGET_SECONDARY_RELOAD
10760 
#define TARGET_SECONDARY_RELOAD s390_secondary_reload
10761 
 
10762 
#undef TARGET_LIBGCC_CMP_RETURN_MODE
10763 
#define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10764 
 
10765 
#undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10766 
#define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10767 
 
10768 
#undef TARGET_LEGITIMATE_ADDRESS_P
10769 
#define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10770 
 
10771 
#undef TARGET_LEGITIMATE_CONSTANT_P
10772 
#define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10773 
 
10774 
#undef TARGET_CAN_ELIMINATE
10775 
#define TARGET_CAN_ELIMINATE s390_can_eliminate
10776 
 
10777 
#undef TARGET_CONDITIONAL_REGISTER_USAGE
10778 
#define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10779 
 
10780 
#undef TARGET_LOOP_UNROLL_ADJUST
10781 
#define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10782 
 
10783 
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10784 
#define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10785 
#undef TARGET_TRAMPOLINE_INIT
10786 
#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10787 
 
10788 
#undef TARGET_UNWIND_WORD_MODE
10789 
#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10790 
 
10791 
struct gcc_target targetm = TARGET_INITIALIZER;
10792 
 
10793 
#include "gt-s390.h"

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