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1 709 jeremybenn
/* Definitions of target machine for GNU compiler, for IBM S/390
2
   Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3
   2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4
   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5
                  Ulrich Weigand (uweigand@de.ibm.com).
6
                  Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7
 
8
This file is part of GCC.
9
 
10
GCC is free software; you can redistribute it and/or modify it under
11
the terms of the GNU General Public License as published by the Free
12
Software Foundation; either version 3, or (at your option) any later
13
version.
14
 
15
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16
WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18
for more details.
19
 
20
You should have received a copy of the GNU General Public License
21
along with GCC; see the file COPYING3.  If not see
22
<http://www.gnu.org/licenses/>.  */
23
 
24
#ifndef _S390_H
25
#define _S390_H
26
 
27
/* Optional architectural facilities supported by the processor.  */
28
 
29
enum processor_flags
30
{
31
  PF_IEEE_FLOAT = 1,
32
  PF_ZARCH = 2,
33
  PF_LONG_DISPLACEMENT = 4,
34
  PF_EXTIMM = 8,
35
  PF_DFP = 16,
36
  PF_Z10 = 32,
37
  PF_Z196 = 64
38
};
39
 
40
/* This is necessary to avoid a warning about comparing different enum
41
   types.  */
42
#define s390_tune_attr ((enum attr_cpu)s390_tune)
43
 
44
/* These flags indicate that the generated code should run on a cpu
45
   providing the respective hardware facility regardless of the
46
   current cpu mode (ESA or z/Architecture).  */
47
 
48
#define TARGET_CPU_IEEE_FLOAT \
49
        (s390_arch_flags & PF_IEEE_FLOAT)
50
#define TARGET_CPU_ZARCH \
51
        (s390_arch_flags & PF_ZARCH)
52
#define TARGET_CPU_LONG_DISPLACEMENT \
53
        (s390_arch_flags & PF_LONG_DISPLACEMENT)
54
#define TARGET_CPU_EXTIMM \
55
        (s390_arch_flags & PF_EXTIMM)
56
#define TARGET_CPU_DFP \
57
        (s390_arch_flags & PF_DFP)
58
#define TARGET_CPU_Z10 \
59
        (s390_arch_flags & PF_Z10)
60
#define TARGET_CPU_Z196 \
61
        (s390_arch_flags & PF_Z196)
62
 
63
/* These flags indicate that the generated code should run on a cpu
64
   providing the respective hardware facility when run in
65
   z/Architecture mode.  */
66
 
67
#define TARGET_LONG_DISPLACEMENT \
68
       (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
69
#define TARGET_EXTIMM \
70
       (TARGET_ZARCH && TARGET_CPU_EXTIMM)
71
#define TARGET_DFP \
72
       (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT)
73
#define TARGET_Z10 \
74
       (TARGET_ZARCH && TARGET_CPU_Z10)
75
#define TARGET_Z196 \
76
       (TARGET_ZARCH && TARGET_CPU_Z196)
77
 
78
 
79
#define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196)
80
 
81
/* Run-time target specification.  */
82
 
83
/* Defaults for option flags defined only on some subtargets.  */
84
#ifndef TARGET_TPF_PROFILING
85
#define TARGET_TPF_PROFILING 0
86
#endif
87
 
88
/* This will be overridden by OS headers.  */
89
#define TARGET_TPF 0
90
 
91
/* Target CPU builtins.  */
92
#define TARGET_CPU_CPP_BUILTINS()                       \
93
  do                                                    \
94
    {                                                   \
95
      builtin_assert ("cpu=s390");                      \
96
      builtin_assert ("machine=s390");                  \
97
      builtin_define ("__s390__");                      \
98
      if (TARGET_ZARCH)                                 \
99
        builtin_define ("__zarch__");                   \
100
      if (TARGET_64BIT)                                 \
101
        builtin_define ("__s390x__");                   \
102
      if (TARGET_LONG_DOUBLE_128)                       \
103
        builtin_define ("__LONG_DOUBLE_128__");         \
104
    }                                                   \
105
  while (0)
106
 
107
#ifdef DEFAULT_TARGET_64BIT
108
#define TARGET_DEFAULT             (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP)
109
#else
110
#define TARGET_DEFAULT             0
111
#endif
112
 
113
/* Support for configure-time defaults.  */
114
#define OPTION_DEFAULT_SPECS                                    \
115
  { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" },                 \
116
  { "arch", "%{!march=*:-march=%(VALUE)}" },                    \
117
  { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
118
 
119
/* Defaulting rules.  */
120
#ifdef DEFAULT_TARGET_64BIT
121
#define DRIVER_SELF_SPECS                                       \
122
  "%{!m31:%{!m64:-m64}}",                                       \
123
  "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
124
  "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
125
#else
126
#define DRIVER_SELF_SPECS                                       \
127
  "%{!m31:%{!m64:-m31}}",                                       \
128
  "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",             \
129
  "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
130
#endif
131
 
132
/* Constants needed to control the TEST DATA CLASS (TDC) instruction.  */
133
#define S390_TDC_POSITIVE_ZERO                     (1 << 11)
134
#define S390_TDC_NEGATIVE_ZERO                     (1 << 10)
135
#define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER    (1 << 9)
136
#define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER    (1 << 8)
137
#define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER  (1 << 7)
138
#define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER  (1 << 6)
139
#define S390_TDC_POSITIVE_INFINITY                 (1 << 5)
140
#define S390_TDC_NEGATIVE_INFINITY                 (1 << 4)
141
#define S390_TDC_POSITIVE_QUIET_NAN                (1 << 3)
142
#define S390_TDC_NEGATIVE_QUIET_NAN                (1 << 2)
143
#define S390_TDC_POSITIVE_SIGNALING_NAN            (1 << 1)
144
#define S390_TDC_NEGATIVE_SIGNALING_NAN            (1 << 0)
145
 
146
/* The following values are different for DFP.  */
147
#define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
148
#define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
149
#define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER   (1 << 7)
150
#define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER   (1 << 6)
151
 
152
/* For signbit, the BFP-DFP-difference makes no difference. */
153
#define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
154
                          | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
155
                          | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
156
                          | S390_TDC_NEGATIVE_INFINITY \
157
                          | S390_TDC_NEGATIVE_QUIET_NAN \
158
                          | S390_TDC_NEGATIVE_SIGNALING_NAN )
159
 
160
#define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
161
                          | S390_TDC_NEGATIVE_INFINITY )
162
 
163
/* Target machine storage layout.  */
164
 
165
/* Everything is big-endian.  */
166
#define BITS_BIG_ENDIAN 1
167
#define BYTES_BIG_ENDIAN 1
168
#define WORDS_BIG_ENDIAN 1
169
 
170
#define STACK_SIZE_MODE (Pmode)
171
 
172
#ifndef IN_LIBGCC2
173
 
174
/* Width of a word, in units (bytes).  */
175
  #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4)
176
 
177
/* Width of a pointer.  To be used instead of UNITS_PER_WORD in
178
   ABI-relevant contexts.  This always matches
179
   GET_MODE_SIZE (Pmode).  */
180
  #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4)
181
  #define MIN_UNITS_PER_WORD 4
182
  #define MAX_BITS_PER_WORD 64
183
#else
184
 
185
  /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether
186
     the library should export TImode functions or not.  Thus, we have
187
     to redefine UNITS_PER_WORD depending on __s390x__ for libgcc.  */
188
  #ifdef __s390x__
189
    #define UNITS_PER_WORD 8
190
  #else
191
    #define UNITS_PER_WORD 4
192
  #endif
193
#endif
194
 
195
/* Width of a pointer, in bits.  */
196
#define POINTER_SIZE (TARGET_64BIT ? 64 : 32)
197
 
198
/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
199
#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
200
 
201
/* Boundary (in *bits*) on which stack pointer should be aligned.  */
202
#define STACK_BOUNDARY 64
203
 
204
/* Allocation boundary (in *bits*) for the code of a function.  */
205
#define FUNCTION_BOUNDARY 32
206
 
207
/* There is no point aligning anything to a rounder boundary than this.  */
208
#define BIGGEST_ALIGNMENT 64
209
 
210
/* Alignment of field after `int : 0' in a structure.  */
211
#define EMPTY_FIELD_BOUNDARY 32
212
 
213
/* Alignment on even addresses for LARL instruction.  */
214
#define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
215
#define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
216
 
217
/* Alignment is not required by the hardware.  */
218
#define STRICT_ALIGNMENT 0
219
 
220
/* Mode of stack savearea.
221
   FUNCTION is VOIDmode because calling convention maintains SP.
222
   BLOCK needs Pmode for SP.
223
   NONLOCAL needs twice Pmode to maintain both backchain and SP.  */
224
#define STACK_SAVEAREA_MODE(LEVEL)      \
225
  (LEVEL == SAVE_FUNCTION ? VOIDmode    \
226
  : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
227
 
228
 
229
/* Type layout.  */
230
 
231
/* Sizes in bits of the source language data types.  */
232
#define SHORT_TYPE_SIZE 16
233
#define INT_TYPE_SIZE 32
234
#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
235
#define LONG_LONG_TYPE_SIZE 64
236
#define FLOAT_TYPE_SIZE 32
237
#define DOUBLE_TYPE_SIZE 64
238
#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64)
239
 
240
/* Define this to set long double type size to use in libgcc2.c, which can
241
   not depend on target_flags.  */
242
#ifdef __LONG_DOUBLE_128__
243
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
244
#else
245
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
246
#endif
247
 
248
/* Work around target_flags dependency in ada/targtyps.c.  */
249
#define WIDEST_HARDWARE_FP_SIZE 64
250
 
251
/* We use "unsigned char" as default.  */
252
#define DEFAULT_SIGNED_CHAR 0
253
 
254
 
255
/* Register usage.  */
256
 
257
/* We have 16 general purpose registers (registers 0-15),
258
   and 16 floating point registers (registers 16-31).
259
   (On non-IEEE machines, we have only 4 fp registers.)
260
 
261
   Amongst the general purpose registers, some are used
262
   for specific purposes:
263
   GPR 11: Hard frame pointer (if needed)
264
   GPR 12: Global offset table pointer (if needed)
265
   GPR 13: Literal pool base register
266
   GPR 14: Return address register
267
   GPR 15: Stack pointer
268
 
269
   Registers 32-35 are 'fake' hard registers that do not
270
   correspond to actual hardware:
271
   Reg 32: Argument pointer
272
   Reg 33: Condition code
273
   Reg 34: Frame pointer
274
   Reg 35: Return address pointer
275
 
276
   Registers 36 and 37 are mapped to access registers
277
 
278
 
279
#define FIRST_PSEUDO_REGISTER 38
280
 
281
/* Standard register usage.  */
282
#define GENERAL_REGNO_P(N)      ((int)(N) >= 0 && (N) < 16)
283
#define ADDR_REGNO_P(N)         ((N) >= 1 && (N) < 16)
284
#define FP_REGNO_P(N)           ((N) >= 16 && (N) < 32)
285
#define CC_REGNO_P(N)           ((N) == 33)
286
#define FRAME_REGNO_P(N)        ((N) == 32 || (N) == 34 || (N) == 35)
287
#define ACCESS_REGNO_P(N)       ((N) == 36 || (N) == 37)
288
 
289
#define GENERAL_REG_P(X)        (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
290
#define ADDR_REG_P(X)           (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
291
#define FP_REG_P(X)             (REG_P (X) && FP_REGNO_P (REGNO (X)))
292
#define CC_REG_P(X)             (REG_P (X) && CC_REGNO_P (REGNO (X)))
293
#define FRAME_REG_P(X)          (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
294
#define ACCESS_REG_P(X)         (REG_P (X) && ACCESS_REGNO_P (REGNO (X)))
295
 
296
/* Set up fixed registers and calling convention:
297
 
298
   GPRs 0-5 are always call-clobbered,
299
   GPRs 6-15 are always call-saved.
300
   GPR 12 is fixed if used as GOT pointer.
301
   GPR 13 is always fixed (as literal pool pointer).
302
   GPR 14 is always fixed on S/390 machines (as return address).
303
   GPR 15 is always fixed (as stack pointer).
304
   The 'fake' hard registers are call-clobbered and fixed.
305
   The access registers are call-saved and fixed.
306
 
307
   On 31-bit, FPRs 18-19 are call-clobbered;
308
   on 64-bit, FPRs 24-31 are call-clobbered.
309
   The remaining FPRs are call-saved.  */
310
 
311
#define FIXED_REGISTERS                         \
312
{ 0, 0, 0, 0,                                       \
313
  0, 0, 0, 0,                                       \
314
  0, 0, 0, 0,                                       \
315
  0, 1, 1, 1,                                    \
316
  0, 0, 0, 0,                                       \
317
  0, 0, 0, 0,                                       \
318
  0, 0, 0, 0,                                       \
319
  0, 0, 0, 0,                                       \
320
  1, 1, 1, 1,                                   \
321
  1, 1 }
322
 
323
#define CALL_USED_REGISTERS                     \
324
{ 1, 1, 1, 1,                                   \
325
  1, 1, 0, 0,                                     \
326
  0, 0, 0, 0,                                       \
327
  0, 1, 1, 1,                                    \
328
  1, 1, 1, 1,                                   \
329
  1, 1, 1, 1,                                   \
330
  1, 1, 1, 1,                                   \
331
  1, 1, 1, 1,                                   \
332
  1, 1, 1, 1,                                   \
333
  1, 1 }
334
 
335
#define CALL_REALLY_USED_REGISTERS              \
336
{ 1, 1, 1, 1,                                   \
337
  1, 1, 0, 0,                                     \
338
  0, 0, 0, 0,                                       \
339
  0, 0, 0, 0,                                       \
340
  1, 1, 1, 1,                                   \
341
  1, 1, 1, 1,                                   \
342
  1, 1, 1, 1,                                   \
343
  1, 1, 1, 1,                                   \
344
  1, 1, 1, 1,                                   \
345
  0, 0 }
346
 
347
/* Preferred register allocation order.  */
348
#define REG_ALLOC_ORDER                                         \
349
{  1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13,            \
350
   16, 17, 18, 19, 20, 21, 22, 23,                              \
351
   24, 25, 26, 27, 28, 29, 30, 31,                              \
352
   15, 32, 33, 34, 35, 36, 37 }
353
 
354
 
355
/* Fitting values into registers.  */
356
 
357
/* Integer modes <= word size fit into any GPR.
358
   Integer modes > word size fit into successive GPRs, starting with
359
   an even-numbered register.
360
   SImode and DImode fit into FPRs as well.
361
 
362
   Floating point modes <= word size fit into any FPR or GPR.
363
   Floating point modes > word size (i.e. DFmode on 32-bit) fit
364
   into any FPR, or an even-odd GPR pair.
365
   TFmode fits only into an even-odd FPR pair.
366
 
367
   Complex floating point modes fit either into two FPRs, or into
368
   successive GPRs (again starting with an even number).
369
   TCmode fits only into two successive even-odd FPR pairs.
370
 
371
   Condition code modes fit only into the CC register.  */
372
 
373
/* Because all registers in a class have the same size HARD_REGNO_NREGS
374
   is equivalent to CLASS_MAX_NREGS.  */
375
#define HARD_REGNO_NREGS(REGNO, MODE)                           \
376
  s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE))
377
 
378
#define HARD_REGNO_MODE_OK(REGNO, MODE)         \
379
  s390_hard_regno_mode_ok ((REGNO), (MODE))
380
 
381
#define HARD_REGNO_RENAME_OK(FROM, TO)          \
382
  s390_hard_regno_rename_ok (FROM, TO)
383
 
384
#define MODES_TIEABLE_P(MODE1, MODE2)           \
385
   (((MODE1) == SFmode || (MODE1) == DFmode)    \
386
   == ((MODE2) == SFmode || (MODE2) == DFmode))
387
 
388
/* When generating code that runs in z/Architecture mode,
389
   but conforms to the 31-bit ABI, GPRs can hold 8 bytes;
390
   the ABI guarantees only that the lower 4 bytes are
391
   saved across calls, however.  */
392
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)             \
393
  (!TARGET_64BIT && TARGET_ZARCH                                \
394
   && GET_MODE_SIZE (MODE) > 4                                  \
395
   && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32))
396
 
397
/* Maximum number of registers to represent a value of mode MODE
398
   in a register of class CLASS.  */
399
#define CLASS_MAX_NREGS(CLASS, MODE)                                    \
400
  s390_class_max_nregs ((CLASS), (MODE))
401
 
402
/* If a 4-byte value is loaded into a FPR, it is placed into the
403
   *upper* half of the register, not the lower.  Therefore, we
404
   cannot use SUBREGs to switch between modes in FP registers.
405
   Likewise for access registers, since they have only half the
406
   word size on 64-bit.  */
407
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)                       \
408
  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)                           \
409
   ? ((reg_classes_intersect_p (FP_REGS, CLASS)                         \
410
       && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8))         \
411
      || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0)
412
 
413
/* Register classes.  */
414
 
415
/* We use the following register classes:
416
   GENERAL_REGS     All general purpose registers
417
   ADDR_REGS        All general purpose registers except %r0
418
                    (These registers can be used in address generation)
419
   FP_REGS          All floating point registers
420
   CC_REGS          The condition code register
421
   ACCESS_REGS      The access registers
422
 
423
   GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
424
   ADDR_FP_REGS     Union of ADDR_REGS and FP_REGS
425
   GENERAL_CC_REGS  Union of GENERAL_REGS and CC_REGS
426
   ADDR_CC_REGS     Union of ADDR_REGS and CC_REGS
427
 
428
   NO_REGS          No registers
429
   ALL_REGS         All registers
430
 
431
   Note that the 'fake' frame pointer and argument pointer registers
432
   are included amongst the address registers here.  */
433
 
434
enum reg_class
435
{
436
  NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS,
437
  ADDR_CC_REGS, GENERAL_CC_REGS,
438
  FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
439
  ALL_REGS, LIM_REG_CLASSES
440
};
441
#define N_REG_CLASSES (int) LIM_REG_CLASSES
442
 
443
#define REG_CLASS_NAMES                                                 \
444
{ "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS",     \
445
  "ADDR_CC_REGS", "GENERAL_CC_REGS",                                    \
446
  "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
447
 
448
/* Class -> register mapping.  */
449
#define REG_CLASS_CONTENTS \
450
{                                                       \
451
  { 0x00000000, 0x00000000 },   /* NO_REGS */           \
452
  { 0x00000000, 0x00000002 },   /* CC_REGS */           \
453
  { 0x0000fffe, 0x0000000d },   /* ADDR_REGS */         \
454
  { 0x0000ffff, 0x0000000d },   /* GENERAL_REGS */      \
455
  { 0x00000000, 0x00000030 },   /* ACCESS_REGS */       \
456
  { 0x0000fffe, 0x0000000f },   /* ADDR_CC_REGS */      \
457
  { 0x0000ffff, 0x0000000f },   /* GENERAL_CC_REGS */   \
458
  { 0xffff0000, 0x00000000 },   /* FP_REGS */           \
459
  { 0xfffffffe, 0x0000000d },   /* ADDR_FP_REGS */      \
460
  { 0xffffffff, 0x0000000d },   /* GENERAL_FP_REGS */   \
461
  { 0xffffffff, 0x0000003f },   /* ALL_REGS */          \
462
}
463
 
464
/* In some case register allocation order is not enough for IRA to
465
   generate a good code.  The following macro (if defined) increases
466
   cost of REGNO for a pseudo approximately by pseudo usage frequency
467
   multiplied by the macro value.
468
 
469
   We avoid usage of BASE_REGNUM by nonzero macro value because the
470
   reload can decide not to use the hard register because some
471
   constant was forced to be in memory.  */
472
#define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno)       \
473
  (regno == BASE_REGNUM ? 0.0 : 0.5)
474
 
475
/* Register -> class mapping.  */
476
extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
477
#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
478
 
479
/* ADDR_REGS can be used as base or index register.  */
480
#define INDEX_REG_CLASS ADDR_REGS
481
#define BASE_REG_CLASS ADDR_REGS
482
 
483
/* Check whether REGNO is a hard register of the suitable class
484
   or a pseudo register currently allocated to one such.  */
485
#define REGNO_OK_FOR_INDEX_P(REGNO)                                     \
486
    (((REGNO) < FIRST_PSEUDO_REGISTER                                   \
487
      && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS)                        \
488
     || ADDR_REGNO_P (reg_renumber[REGNO]))
489
#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
490
 
491
 
492
/* We need secondary memory to move data between GPRs and FPRs.  With
493
   DFP the ldgr lgdr instructions are available.  But these
494
   instructions do not handle GPR pairs so it is not possible for 31
495
   bit.  */
496
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
497
 ((CLASS1) != (CLASS2)                                \
498
  && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)     \
499
  && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8))
500
 
501
/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
502
   because the movsi and movsf patterns don't handle r/f moves.  */
503
#define SECONDARY_MEMORY_NEEDED_MODE(MODE)              \
504
 (GET_MODE_BITSIZE (MODE) < 32                          \
505
  ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
506
  : MODE)
507
 
508
 
509
/* Stack layout and calling conventions.  */
510
 
511
/* Our stack grows from higher to lower addresses.  However, local variables
512
   are accessed by positive offsets, and function arguments are stored at
513
   increasing addresses.  */
514
#define STACK_GROWS_DOWNWARD
515
#define FRAME_GROWS_DOWNWARD 1
516
/* #undef ARGS_GROW_DOWNWARD */
517
 
518
/* The basic stack layout looks like this: the stack pointer points
519
   to the register save area for called functions.  Above that area
520
   is the location to place outgoing arguments.  Above those follow
521
   dynamic allocations (alloca), and finally the local variables.  */
522
 
523
/* Offset from stack-pointer to first location of outgoing args.  */
524
#define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
525
 
526
/* Offset within stack frame to start allocating local variables at.  */
527
#define STARTING_FRAME_OFFSET 0
528
 
529
/* Offset from the stack pointer register to an item dynamically
530
   allocated on the stack, e.g., by `alloca'.  */
531
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
532
  (STACK_POINTER_OFFSET + crtl->outgoing_args_size)
533
 
534
/* Offset of first parameter from the argument pointer register value.
535
   We have a fake argument pointer register that points directly to
536
   the argument area.  */
537
#define FIRST_PARM_OFFSET(FNDECL) 0
538
 
539
/* Defining this macro makes __builtin_frame_address(0) and
540
   __builtin_return_address(0) work with -fomit-frame-pointer.  */
541
#define INITIAL_FRAME_ADDRESS_RTX                                             \
542
  (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
543
 
544
/* The return address of the current frame is retrieved
545
   from the initial value of register RETURN_REGNUM.
546
   For frames farther back, we use the stack slot where
547
   the corresponding RETURN_REGNUM register was saved.  */
548
#define DYNAMIC_CHAIN_ADDRESS(FRAME)                                          \
549
  (TARGET_PACKED_STACK ?                                                      \
550
   plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME))
551
 
552
/* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of
553
   builtin_frame_address.  Otherwise arg pointer -
554
   STACK_POINTER_OFFSET would be returned for
555
   __builtin_frame_address(0) what might result in an address pointing
556
   somewhere into the middle of the local variables since the packed
557
   stack layout generally does not need all the bytes in the register
558
   save area.  */
559
#define FRAME_ADDR_RTX(FRAME)                   \
560
  DYNAMIC_CHAIN_ADDRESS ((FRAME))
561
 
562
#define RETURN_ADDR_RTX(COUNT, FRAME)                                         \
563
  s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
564
 
565
/* In 31-bit mode, we need to mask off the high bit of return addresses.  */
566
#define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
567
 
568
 
569
/* Exception handling.  */
570
 
571
/* Describe calling conventions for DWARF-2 exception handling.  */
572
#define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, RETURN_REGNUM)
573
#define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
574
#define DWARF_FRAME_RETURN_COLUMN  14
575
 
576
/* Describe how we implement __builtin_eh_return.  */
577
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
578
#define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx)
579
 
580
/* Select a format to encode pointers in exception handling data.  */
581
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)                          \
582
  (flag_pic                                                                 \
583
    ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
584
   : DW_EH_PE_absptr)
585
 
586
/* Register save slot alignment.  */
587
#define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG)
588
 
589
 
590
/* Frame registers.  */
591
 
592
#define STACK_POINTER_REGNUM 15
593
#define FRAME_POINTER_REGNUM 34
594
#define HARD_FRAME_POINTER_REGNUM 11
595
#define ARG_POINTER_REGNUM 32
596
#define RETURN_ADDRESS_POINTER_REGNUM 35
597
 
598
/* The static chain must be call-clobbered, but not used for
599
   function argument passing.  As register 1 is clobbered by
600
   the trampoline code, we only have one option.  */
601
#define STATIC_CHAIN_REGNUM 0
602
 
603
/* Number of hardware registers that go into the DWARF-2 unwind info.
604
   To avoid ABI incompatibility, this number must not change even as
605
   'fake' hard registers are added or removed.  */
606
#define DWARF_FRAME_REGISTERS 34
607
 
608
 
609
/* Frame pointer and argument pointer elimination.  */
610
 
611
#define ELIMINABLE_REGS                                         \
612
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },                \
613
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },           \
614
 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },                  \
615
 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },             \
616
 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM },       \
617
 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },  \
618
 { BASE_REGNUM, BASE_REGNUM }}
619
 
620
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
621
  (OFFSET) = s390_initial_elimination_offset ((FROM), (TO))
622
 
623
 
624
/* Stack arguments.  */
625
 
626
/* We need current_function_outgoing_args to be valid.  */
627
#define ACCUMULATE_OUTGOING_ARGS 1
628
 
629
 
630
/* Register arguments.  */
631
 
632
typedef struct s390_arg_structure
633
{
634
  int gprs;                     /* gpr so far */
635
  int fprs;                     /* fpr so far */
636
}
637
CUMULATIVE_ARGS;
638
 
639
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
640
  ((CUM).gprs=0, (CUM).fprs=0)
641
 
642
/* Arguments can be placed in general registers 2 to 6, or in floating
643
   point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64
644
   bit.  */
645
#define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
646
  (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19)))
647
 
648
 
649
/* Only gpr 2 and fpr 0 are ever used as return registers.  */
650
#define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
651
 
652
 
653
/* Function entry and exit.  */
654
 
655
/* When returning from a function, the stack pointer does not matter.  */
656
#define EXIT_IGNORE_STACK       1
657
 
658
 
659
/* Profiling.  */
660
 
661
#define FUNCTION_PROFILER(FILE, LABELNO)                        \
662
  s390_function_profiler ((FILE), ((LABELNO)))
663
 
664
#define PROFILE_BEFORE_PROLOGUE 1
665
 
666
 
667
/* Trampolines for nested functions.  */
668
 
669
#define TRAMPOLINE_SIZE         (TARGET_64BIT ? 32 : 16)
670
#define TRAMPOLINE_ALIGNMENT    BITS_PER_WORD
671
 
672
/* Addressing modes, and classification of registers for them.  */
673
 
674
/* Recognize any constant value that is a valid address.  */
675
#define CONSTANT_ADDRESS_P(X) 0
676
 
677
/* Maximum number of registers that can appear in a valid memory address.  */
678
#define MAX_REGS_PER_ADDRESS 2
679
 
680
/* This definition replaces the formerly used 'm' constraint with a
681
   different constraint letter in order to avoid changing semantics of
682
   the 'm' constraint when accepting new address formats in
683
   TARGET_LEGITIMATE_ADDRESS_P.  The constraint letter defined here
684
   must not be used in insn definitions or inline assemblies.  */
685
#define TARGET_MEM_CONSTRAINT 'e'
686
 
687
/* Try a machine-dependent way of reloading an illegitimate address
688
   operand.  If we find one, push the reload and jump to WIN.  This
689
   macro is used in only one place: `find_reloads_address' in reload.c.  */
690
#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN)      \
691
do {                                                                    \
692
  rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE));       \
693
  if (new_rtx)                                                          \
694
    {                                                                   \
695
      (AD) = new_rtx;                                                   \
696
      goto WIN;                                                         \
697
    }                                                                   \
698
} while (0)
699
 
700
/* Helper macro for s390.c and s390.md to check for symbolic constants.  */
701
#define SYMBOLIC_CONST(X)       \
702
(GET_CODE (X) == SYMBOL_REF                                             \
703
 || GET_CODE (X) == LABEL_REF                                           \
704
 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
705
 
706
#define TLS_SYMBOLIC_CONST(X)   \
707
((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X))       \
708
 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
709
 
710
 
711
/* Condition codes.  */
712
 
713
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
714
   return the mode to be used for the comparison.  */
715
#define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
716
 
717
/* Canonicalize a comparison from one we don't have to one we do have.  */
718
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
719
  s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1))
720
 
721
/* Relative costs of operations.  */
722
 
723
/* A C expression for the cost of a branch instruction.  A value of 1
724
   is the default; other values are interpreted relative to that.  */
725
#define BRANCH_COST(speed_p, predictable_p) s390_branch_cost
726
 
727
/* Nonzero if access to memory by bytes is slow and undesirable.  */
728
#define SLOW_BYTE_ACCESS 1
729
 
730
/* An integer expression for the size in bits of the largest integer machine
731
   mode that should actually be used.  We allow pairs of registers.  */
732
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
733
 
734
/* The maximum number of bytes that a single instruction can move quickly
735
   between memory and registers or between two memory locations.  */
736
#define MOVE_MAX (TARGET_ZARCH ? 16 : 8)
737
#define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4)
738
#define MAX_MOVE_MAX 16
739
 
740
/* Determine whether to use move_by_pieces or block move insn.  */
741
#define MOVE_BY_PIECES_P(SIZE, ALIGN)           \
742
  ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
743
    || (TARGET_ZARCH && (SIZE) == 8) )
744
 
745
/* Determine whether to use clear_by_pieces or block clear insn.  */
746
#define CLEAR_BY_PIECES_P(SIZE, ALIGN)          \
747
  ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4   \
748
    || (TARGET_ZARCH && (SIZE) == 8) )
749
 
750
/* This macro is used to determine whether store_by_pieces should be
751
   called to "memcpy" storage when the source is a constant string.  */
752
#define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN)
753
 
754
/* Likewise to decide whether to "memset" storage with byte values
755
   other than zero.  */
756
#define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN)
757
 
758
/* Don't perform CSE on function addresses.  */
759
#define NO_FUNCTION_CSE
760
 
761
/* This value is used in tree-sra to decide whether it might benefical
762
   to split a struct move into several word-size moves.  For S/390
763
   only small values make sense here since struct moves are relatively
764
   cheap thanks to mvc so the small default value choosen for archs
765
   with memmove patterns should be ok.  But this value is multiplied
766
   in tree-sra with UNITS_PER_WORD to make a decision so we adjust it
767
   here to compensate for that factor since mvc costs exactly the same
768
   on 31 and 64 bit.  */
769
#define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4)
770
 
771
 
772
/* Sections.  */
773
 
774
/* Output before read-only data.  */
775
#define TEXT_SECTION_ASM_OP ".text"
776
 
777
/* Output before writable (initialized) data.  */
778
#define DATA_SECTION_ASM_OP ".data"
779
 
780
/* Output before writable (uninitialized) data.  */
781
#define BSS_SECTION_ASM_OP ".bss"
782
 
783
/* S/390 constant pool breaks the devices in crtstuff.c to control section
784
   in where code resides.  We have to write it as asm code.  */
785
#ifndef __s390x__
786
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
787
    asm (SECTION_OP "\n\
788
        bras\t%r2,1f\n\
789
0:      .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
790
1:      l\t%r3,0(%r2)\n\
791
        bas\t%r14,0(%r3,%r2)\n\
792
        .previous");
793
#endif
794
 
795
 
796
/* Position independent code.  */
797
 
798
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
799
 
800
#define LEGITIMATE_PIC_OPERAND_P(X)  legitimate_pic_operand_p (X)
801
 
802
 
803
/* Assembler file format.  */
804
 
805
/* Character to start a comment.  */
806
#define ASM_COMMENT_START "#"
807
 
808
/* Declare an uninitialized external linkage data object.  */
809
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
810
  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
811
 
812
/* Globalizing directive for a label.  */
813
#define GLOBAL_ASM_OP ".globl "
814
 
815
/* Advance the location counter to a multiple of 2**LOG bytes.  */
816
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
817
  if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
818
 
819
/* Advance the location counter by SIZE bytes.  */
820
#define ASM_OUTPUT_SKIP(FILE, SIZE) \
821
  fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
822
 
823
/* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h.  */
824
#define LOCAL_LABEL_PREFIX "."
825
 
826
#define LABEL_ALIGN(LABEL) \
827
  s390_label_align (LABEL)
828
 
829
/* How to refer to registers in assembler output.  This sequence is
830
   indexed by compiler's hard-register-number (see above).  */
831
#define REGISTER_NAMES                                                  \
832
{ "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",        \
833
  "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",       \
834
  "%f0",  "%f2",  "%f4",  "%f6",  "%f1",  "%f3",  "%f5",  "%f7",        \
835
  "%f8",  "%f10", "%f12", "%f14", "%f9",  "%f11", "%f13", "%f15",       \
836
  "%ap",  "%cc",  "%fp",  "%rp",  "%a0",  "%a1"                         \
837
}
838
 
839
/* Print operand X (an rtx) in assembler syntax to file FILE.  */
840
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
841
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
842
 
843
/* Output an element of a case-vector that is absolute.  */
844
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)                            \
845
do {                                                                    \
846
  char buf[32];                                                         \
847
  fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
848
  ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
849
  assemble_name ((FILE), buf);                                          \
850
  fputc ('\n', (FILE));                                                 \
851
} while (0)
852
 
853
/* Output an element of a case-vector that is relative.  */
854
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)                \
855
do {                                                                    \
856
  char buf[32];                                                         \
857
  fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE));                \
858
  ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE));                      \
859
  assemble_name ((FILE), buf);                                          \
860
  fputc ('-', (FILE));                                                  \
861
  ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL));                        \
862
  assemble_name ((FILE), buf);                                          \
863
  fputc ('\n', (FILE));                                                 \
864
} while (0)
865
 
866
 
867
/* Miscellaneous parameters.  */
868
 
869
/* Specify the machine mode that this machine uses for the index in the
870
   tablejump instruction.  */
871
#define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
872
 
873
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
874
   is done just by pretending it is already truncated.  */
875
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
876
 
877
/* Specify the machine mode that pointers have.
878
   After generation of rtl, the compiler makes no further distinction
879
   between pointers and any other objects of this machine mode.  */
880
#define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
881
 
882
/* This is -1 for "pointer mode" extend.  See ptr_extend in s390.md.  */
883
#define POINTERS_EXTEND_UNSIGNED -1
884
 
885
/* A function address in a call instruction is a byte address (for
886
   indexing purposes) so give the MEM rtx a byte's mode.  */
887
#define FUNCTION_MODE QImode
888
 
889
/* Specify the value which is used when clz operand is zero.  */
890
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1)
891
 
892
/* Machine-specific symbol_ref flags.  */
893
#define SYMBOL_FLAG_ALIGN1                (SYMBOL_FLAG_MACH_DEP << 0)
894
#define SYMBOL_REF_ALIGN1_P(X)          \
895
  ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1))
896
#define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1)
897
#define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \
898
  ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED))
899
 
900
/* Check whether integer displacement is in range.  */
901
#define DISP_IN_RANGE(d) \
902
  (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
903
                           : ((d) >= 0 && (d) <= 4095))
904
 
905
/* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c.  */
906
#define READ_CAN_USE_WRITE_PREFETCH 1
907
 
908
extern const int processor_flags_table[];
909
#endif

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