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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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jeremybenn |
; Options for the Sunnorth port of the compiler.
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; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; .
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meb
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Target RejectNegative Report InverseMask(LITTLE_ENDIAN)
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Generate big-endian code
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mel
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Target RejectNegative Report Mask(LITTLE_ENDIAN)
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Generate little-endian code
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mnhwloop
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Target RejectNegative Report Mask(NHWLOOP)
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Disable bcnz instruction
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muls
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Target RejectNegative Report Mask(ULS)
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Enable unaligned load/store instruction
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mscore7
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Target RejectNegative Report Mask(SCORE7)
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Support SCORE 7 ISA
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mscore7d
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Target RejectNegative Report Mask(SCORE7D)
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Support SCORE 7D ISA
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march=
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Target RejectNegative Joined Enum(score_arch)
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Specify the name of the target architecture
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Enum
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Name(score_arch) Type(int)
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Known SCORE architectures (for use with the -march= option):
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EnumValue
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Enum(score_arch) String(score7) Value(MASK_SCORE7)
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EnumValue
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Enum(score_arch) String(score7d) Value(MASK_SCORE7 | MASK_SCORE7D)
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