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/* Output routines for GCC for Renesas / SuperH SH.

   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,

   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011

   Free Software Foundation, Inc.

   Contributed by Steve Chamberlain (sac@cygnus.com).

   Improved by Jim Wilson (wilson@cygnus.com).

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "insn-config.h"

#include "rtl.h"

#include "tree.h"

#include "flags.h"

#include "expr.h"

#include "optabs.h"

#include "reload.h"

#include "function.h"

#include "regs.h"

#include "hard-reg-set.h"

#include "output.h"

#include "insn-attr.h"

#include "diagnostic-core.h"

#include "recog.h"

#include "integrate.h"

#include "dwarf2.h"

#include "tm_p.h"

#include "target.h"

#include "target-def.h"

#include "langhooks.h"

#include "basic-block.h"

#include "df.h"

#include "cfglayout.h"

#include "intl.h"

#include "sched-int.h"

#include "params.h"

#include "ggc.h"

#include "gimple.h"

#include "cfgloop.h"

#include "alloc-pool.h"

#include "tm-constrs.h"

#include "opts.h"

int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;

#define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)

#define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)

/* These are some macros to abstract register modes.  */

#define CONST_OK_FOR_ADD(size) \

  (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))

#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))

#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))

#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))

/* Used to simplify the logic below.  Find the attributes wherever

   they may be.  */

#define SH_ATTRIBUTES(decl) \

  (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \

                  : DECL_ATTRIBUTES (decl) \

                  ? (DECL_ATTRIBUTES (decl)) \

                  : TYPE_ATTRIBUTES (TREE_TYPE (decl))

/* Set to 1 by expand_prologue() when the function is an interrupt handler.  */

int current_function_interrupt;

tree sh_deferred_function_attributes;

tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;

/* Global variables for machine-dependent things.  */

/* Which cpu are we scheduling for.  */

enum processor_type sh_cpu;

/* Definitions used in ready queue reordering for first scheduling pass.  */

/* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID.  */

static short *regmode_weight[2];

/* Total SFmode and SImode weights of scheduled insns.  */

static int curr_regmode_pressure[2];

/* Number of r0 life regions.  */

static int r0_life_regions;

/* If true, skip cycles for Q -> R movement.  */

static int skip_cycles = 0;

/* Cached value of can_issue_more. This is cached in sh_variable_issue hook

   and returned from sh_reorder2.  */

static short cached_can_issue_more;

/* Unique number for UNSPEC_BBR pattern.  */

static unsigned int unspec_bbr_uid = 1;

/* Provides the class number of the smallest class containing

   reg number.  */

enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =

{

  R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,

  FP0_REGS,FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  FP_REGS, FP_REGS, FP_REGS, FP_REGS,

  TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,

  TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,

  DF_REGS, DF_REGS, DF_REGS, DF_REGS,

  DF_REGS, DF_REGS, DF_REGS, DF_REGS,

  NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,

  MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,

  GENERAL_REGS, GENERAL_REGS,

};

char sh_register_names[FIRST_PSEUDO_REGISTER] \

  [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;

char sh_additional_register_names[ADDREGNAMES_SIZE] \

  [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]

  = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;

int assembler_dialect;

static bool shmedia_space_reserved_for_target_registers;

static void split_branches (rtx);

static int branch_dest (rtx);

static void force_into (rtx, rtx);

static void print_slot (rtx);

static rtx add_constant (rtx, enum machine_mode, rtx);

static void dump_table (rtx, rtx);

static int hi_const (rtx);

static int broken_move (rtx);

static int mova_p (rtx);

static rtx find_barrier (int, rtx, rtx);

static int noncall_uses_reg (rtx, rtx, rtx *);

static rtx gen_block_redirect (rtx, int, int);

static void sh_reorg (void);

static void sh_option_override (void);

static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);

static rtx frame_insn (rtx);

static rtx push (int);

static void pop (int);

static void push_regs (HARD_REG_SET *, int);

static int calc_live_regs (HARD_REG_SET *);

static HOST_WIDE_INT rounded_frame_size (int);

static bool sh_frame_pointer_required (void);

static rtx mark_constant_pool_use (rtx);

static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree, int, bool *);

static tree sh_handle_resbank_handler_attribute (tree *, tree,

                                                 tree, int, bool *);

static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,

                                                           tree, int, bool *);

static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);

static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);

static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);

static void sh_print_operand (FILE *, rtx, int);

static void sh_print_operand_address (FILE *, rtx);

static bool sh_print_operand_punct_valid_p (unsigned char code);

static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);

static void sh_output_function_epilogue (FILE *, HOST_WIDE_INT);

static void sh_insert_attributes (tree, tree *);

static const char *sh_check_pch_target_flags (int);

static int sh_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);

static int sh_adjust_cost (rtx, rtx, rtx, int);

static int sh_issue_rate (void);

static int sh_dfa_new_cycle (FILE *, int, rtx, int, int, int *sort_p);

static short find_set_regmode_weight (rtx, enum machine_mode);

static short find_insn_regmode_weight (rtx, enum machine_mode);

static void find_regmode_weight (basic_block, enum machine_mode);

static int find_r0_life_regions (basic_block);

static void  sh_md_init_global (FILE *, int, int);

static void  sh_md_finish_global (FILE *, int);

static int rank_for_reorder (const void *, const void *);

static void swap_reorder (rtx *, int);

static void ready_reorder (rtx *, int);

static short high_pressure (enum machine_mode);

static int sh_reorder (FILE *, int, rtx *, int *, int);

static int sh_reorder2 (FILE *, int, rtx *, int *, int);

static void sh_md_init (FILE *, int, int);

static int sh_variable_issue (FILE *, int, rtx, int);

static bool sh_function_ok_for_sibcall (tree, tree);

static bool sh_cannot_modify_jumps_p (void);

static reg_class_t sh_target_reg_class (void);

static bool sh_optimize_target_register_callee_saved (bool);

static bool sh_ms_bitfield_layout_p (const_tree);

static void sh_init_builtins (void);

static tree sh_builtin_decl (unsigned, bool);

static void sh_media_init_builtins (void);

static tree sh_media_builtin_decl (unsigned, bool);

static rtx sh_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);

static void sh_file_start (void);

static int flow_dependent_p (rtx, rtx);

static void flow_dependent_p_1 (rtx, const_rtx, void *);

static int shiftcosts (rtx);

static int and_xor_ior_costs (rtx, int);

static int addsubcosts (rtx);

static int multcosts (rtx);

static bool unspec_caller_rtx_p (rtx);

static bool sh_cannot_copy_insn_p (rtx);

static bool sh_rtx_costs (rtx, int, int, int, int *, bool);

static int sh_address_cost (rtx, bool);

static int sh_pr_n_sets (void);

static rtx sh_allocate_initial_value (rtx);

static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);

static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,

                                        enum machine_mode,

                                        struct secondary_reload_info *);

static bool sh_legitimate_address_p (enum machine_mode, rtx, bool);

static rtx sh_legitimize_address (rtx, rtx, enum machine_mode);

static rtx sh_delegitimize_address (rtx);

static int shmedia_target_regs_stack_space (HARD_REG_SET *);

static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);

static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);

static int scavenge_reg (HARD_REG_SET *s);

struct save_schedule_s;

static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,

                                                struct save_schedule_s *, int);

static rtx sh_struct_value_rtx (tree, int);

static rtx sh_function_value (const_tree, const_tree, bool);

static bool sh_function_value_regno_p (const unsigned int);

static rtx sh_libcall_value (enum machine_mode, const_rtx);

static bool sh_return_in_memory (const_tree, const_tree);

static rtx sh_builtin_saveregs (void);

static void sh_setup_incoming_varargs (cumulative_args_t, enum machine_mode, tree, int *, int);

static bool sh_strict_argument_naming (cumulative_args_t);

static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);

static tree sh_build_builtin_va_list (void);

static void sh_va_start (tree, rtx);

static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);

static bool sh_promote_prototypes (const_tree);

static enum machine_mode sh_promote_function_mode (const_tree type,

                                                   enum machine_mode,

                                                   int *punsignedp,

                                                   const_tree funtype,

                                                   int for_return);

static bool sh_pass_by_reference (cumulative_args_t, enum machine_mode,

                                  const_tree, bool);

static bool sh_callee_copies (cumulative_args_t, enum machine_mode,

                              const_tree, bool);

static int sh_arg_partial_bytes (cumulative_args_t, enum machine_mode,

                                 tree, bool);

static void sh_function_arg_advance (cumulative_args_t, enum machine_mode,

                                     const_tree, bool);

static rtx sh_function_arg (cumulative_args_t, enum machine_mode,

                            const_tree, bool);

static bool sh_scalar_mode_supported_p (enum machine_mode);

static int sh_dwarf_calling_convention (const_tree);

static void sh_encode_section_info (tree, rtx, int);

static int sh2a_function_vector_p (tree);

static void sh_trampoline_init (rtx, tree, rtx);

static rtx sh_trampoline_adjust_address (rtx);

static void sh_conditional_register_usage (void);

static bool sh_legitimate_constant_p (enum machine_mode, rtx);

static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;

static const struct attribute_spec sh_attribute_table[] =

{

  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,

       affects_type_identity } */

  { "interrupt_handler", 0, 0, true,  false, false,

    sh_handle_interrupt_handler_attribute, false },

  { "sp_switch",         1, 1, true,  false, false,

     sh_handle_sp_switch_attribute, false },

  { "trap_exit",         1, 1, true,  false, false,

    sh_handle_trap_exit_attribute, false },

  { "renesas",           0, 0, false, true, false,

    sh_handle_renesas_attribute, false },

  { "trapa_handler",     0, 0, true,  false, false,

    sh_handle_interrupt_handler_attribute, false },

  { "nosave_low_regs",   0, 0, true,  false, false,

    sh_handle_interrupt_handler_attribute, false },

  { "resbank",           0, 0, true,  false, false,

    sh_handle_resbank_handler_attribute, false },

  { "function_vector",   1, 1, true,  false, false,

    sh2a_handle_function_vector_handler_attribute, false },

  { NULL,                0, 0, false, false, false, NULL, false }

};

/* Initialize the GCC target structure.  */

#undef TARGET_ATTRIBUTE_TABLE

#define TARGET_ATTRIBUTE_TABLE sh_attribute_table

/* The next two are used for debug info when compiling with -gdwarf.  */

#undef TARGET_ASM_UNALIGNED_HI_OP

#define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"

#undef TARGET_ASM_UNALIGNED_SI_OP

#define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"

/* These are NULLed out on non-SH5 in TARGET_OPTION_OVERRIDE.  */

#undef TARGET_ASM_UNALIGNED_DI_OP

#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"

#undef TARGET_ASM_ALIGNED_DI_OP

#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"

#undef TARGET_OPTION_OVERRIDE

#define TARGET_OPTION_OVERRIDE sh_option_override

#undef TARGET_PRINT_OPERAND

#define TARGET_PRINT_OPERAND sh_print_operand

#undef TARGET_PRINT_OPERAND_ADDRESS

#define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address

#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P

#define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p

#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA

#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra

#undef TARGET_ASM_FUNCTION_EPILOGUE

#define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue

#undef TARGET_ASM_OUTPUT_MI_THUNK

#define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk

#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK

#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true

#undef TARGET_ASM_FILE_START

#define TARGET_ASM_FILE_START sh_file_start

#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE

#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true

#undef TARGET_REGISTER_MOVE_COST

#define TARGET_REGISTER_MOVE_COST sh_register_move_cost

#undef TARGET_INSERT_ATTRIBUTES

#define TARGET_INSERT_ATTRIBUTES sh_insert_attributes

#undef TARGET_SCHED_ADJUST_COST

#define TARGET_SCHED_ADJUST_COST sh_adjust_cost

#undef TARGET_SCHED_ISSUE_RATE

#define TARGET_SCHED_ISSUE_RATE sh_issue_rate

/* The next 5 hooks have been implemented for reenabling sched1.  With the

   help of these macros we are limiting the movement of insns in sched1 to

   reduce the register pressure.  The overall idea is to keep count of SImode

   and SFmode regs required by already scheduled insns. When these counts

   cross some threshold values; give priority to insns that free registers.

   The insn that frees registers is most likely to be the insn with lowest

   LUID (original insn order); but such an insn might be there in the stalled

   queue (Q) instead of the ready queue (R).  To solve this, we skip cycles

   upto a max of 8 cycles so that such insns may move from Q -> R.

   The description of the hooks are as below:

   TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic

   scheduler; it is called inside the sched_init function just after

   find_insn_reg_weights function call. It is used to calculate the SImode

   and SFmode weights of insns of basic blocks; much similar to what

   find_insn_reg_weights does.

   TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.

   TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is

   indicated by TARGET_SCHED_REORDER2; doing this may move insns from

   (Q)->(R).

   TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is

   high; reorder the ready queue so that the insn with lowest LUID will be

   issued next.

   TARGET_SCHED_REORDER2: If the register pressure is high, indicate to

   TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.

   TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it

   can be returned from TARGET_SCHED_REORDER2.

   TARGET_SCHED_INIT: Reset the register pressure counting variables.  */

#undef TARGET_SCHED_DFA_NEW_CYCLE

#define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle

#undef TARGET_SCHED_INIT_GLOBAL

#define TARGET_SCHED_INIT_GLOBAL sh_md_init_global

#undef TARGET_SCHED_FINISH_GLOBAL

#define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global

#undef TARGET_SCHED_VARIABLE_ISSUE

#define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue

#undef TARGET_SCHED_REORDER

#define TARGET_SCHED_REORDER sh_reorder

#undef TARGET_SCHED_REORDER2

#define TARGET_SCHED_REORDER2 sh_reorder2

#undef TARGET_SCHED_INIT

#define TARGET_SCHED_INIT sh_md_init

#undef TARGET_DELEGITIMIZE_ADDRESS

#define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address

#undef TARGET_LEGITIMIZE_ADDRESS

#define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address

#undef TARGET_CANNOT_MODIFY_JUMPS_P

#define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p

#undef TARGET_BRANCH_TARGET_REGISTER_CLASS

#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class

#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED

#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \

 sh_optimize_target_register_callee_saved

#undef TARGET_MS_BITFIELD_LAYOUT_P

#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p

#undef TARGET_INIT_BUILTINS

#define TARGET_INIT_BUILTINS sh_init_builtins

#undef TARGET_BUILTIN_DECL

#define TARGET_BUILTIN_DECL sh_builtin_decl

#undef TARGET_EXPAND_BUILTIN

#define TARGET_EXPAND_BUILTIN sh_expand_builtin

#undef TARGET_FUNCTION_OK_FOR_SIBCALL

#define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall

#undef TARGET_CANNOT_COPY_INSN_P

#define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p

#undef TARGET_RTX_COSTS

#define TARGET_RTX_COSTS sh_rtx_costs

#undef TARGET_ADDRESS_COST

#define TARGET_ADDRESS_COST sh_address_cost

#undef TARGET_ALLOCATE_INITIAL_VALUE

#define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value

#undef TARGET_MACHINE_DEPENDENT_REORG

#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg

#undef TARGET_DWARF_REGISTER_SPAN

#define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span

#ifdef HAVE_AS_TLS

#undef TARGET_HAVE_TLS

#define TARGET_HAVE_TLS true

#endif

#undef TARGET_PROMOTE_PROTOTYPES

#define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes

#undef TARGET_PROMOTE_FUNCTION_MODE

#define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode

#undef TARGET_FUNCTION_VALUE

#define TARGET_FUNCTION_VALUE sh_function_value

#undef TARGET_FUNCTION_VALUE_REGNO_P

#define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p

#undef TARGET_LIBCALL_VALUE

#define TARGET_LIBCALL_VALUE sh_libcall_value

#undef TARGET_STRUCT_VALUE_RTX

#define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx

#undef TARGET_RETURN_IN_MEMORY

#define TARGET_RETURN_IN_MEMORY sh_return_in_memory

#undef TARGET_EXPAND_BUILTIN_SAVEREGS

#define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs

#undef TARGET_SETUP_INCOMING_VARARGS

#define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs

#undef TARGET_STRICT_ARGUMENT_NAMING

#define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming

#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED

#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named

#undef TARGET_MUST_PASS_IN_STACK

#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size

#undef TARGET_PASS_BY_REFERENCE

#define TARGET_PASS_BY_REFERENCE sh_pass_by_reference

#undef TARGET_CALLEE_COPIES

#define TARGET_CALLEE_COPIES sh_callee_copies

#undef TARGET_ARG_PARTIAL_BYTES

#define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes

#undef TARGET_FUNCTION_ARG

#define TARGET_FUNCTION_ARG sh_function_arg

#undef TARGET_FUNCTION_ARG_ADVANCE

#define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance

#undef TARGET_BUILD_BUILTIN_VA_LIST

#define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list

#undef TARGET_EXPAND_BUILTIN_VA_START

#define TARGET_EXPAND_BUILTIN_VA_START sh_va_start

#undef TARGET_GIMPLIFY_VA_ARG_EXPR

#define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr

#undef TARGET_SCALAR_MODE_SUPPORTED_P

#define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p

#undef TARGET_VECTOR_MODE_SUPPORTED_P

#define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p

#undef TARGET_CHECK_PCH_TARGET_FLAGS

#define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags

#undef TARGET_DWARF_CALLING_CONVENTION

#define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention

#undef TARGET_FRAME_POINTER_REQUIRED

#define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required

/* Return regmode weight for insn.  */

#define INSN_REGMODE_WEIGHT(INSN, MODE)  regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]

/* Return current register pressure for regmode.  */

#define CURR_REGMODE_PRESSURE(MODE)     curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]

#undef  TARGET_ENCODE_SECTION_INFO

#define TARGET_ENCODE_SECTION_INFO      sh_encode_section_info

#undef TARGET_SECONDARY_RELOAD

#define TARGET_SECONDARY_RELOAD sh_secondary_reload

#undef  TARGET_PREFERRED_RELOAD_CLASS

#define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class

#undef TARGET_CONDITIONAL_REGISTER_USAGE

#define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage

#undef TARGET_LEGITIMATE_ADDRESS_P

#define TARGET_LEGITIMATE_ADDRESS_P     sh_legitimate_address_p

#undef TARGET_TRAMPOLINE_INIT

#define TARGET_TRAMPOLINE_INIT          sh_trampoline_init

#undef TARGET_TRAMPOLINE_ADJUST_ADDRESS

#define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address

#undef TARGET_LEGITIMATE_CONSTANT_P

#define TARGET_LEGITIMATE_CONSTANT_P    sh_legitimate_constant_p

/* Machine-specific symbol_ref flags.  */

#define SYMBOL_FLAG_FUNCVEC_FUNCTION    (SYMBOL_FLAG_MACH_DEP << 0)

struct gcc_target targetm = TARGET_INITIALIZER;

/* Implement TARGET_OPTION_OVERRIDE macro.  Validate and override

   various options, and do some machine dependent initialization.  */

static void

sh_option_override (void)

{

  int regno;

  SUBTARGET_OVERRIDE_OPTIONS;

  if (optimize > 1 && !optimize_size)

    target_flags |= MASK_SAVE_ALL_TARGET_REGS;

  if (flag_finite_math_only == 2)

    flag_finite_math_only

      = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;

  if (TARGET_SH2E && !flag_finite_math_only)

    target_flags |= MASK_IEEE;

  sh_cpu = PROCESSOR_SH1;

  assembler_dialect = 0;

  if (TARGET_SH2)

    sh_cpu = PROCESSOR_SH2;

  if (TARGET_SH2E)

    sh_cpu = PROCESSOR_SH2E;

  if (TARGET_SH2A)

    sh_cpu = PROCESSOR_SH2A;

  if (TARGET_SH3)

    sh_cpu = PROCESSOR_SH3;

  if (TARGET_SH3E)

    sh_cpu = PROCESSOR_SH3E;

  if (TARGET_SH4)

    {

      assembler_dialect = 1;

      sh_cpu = PROCESSOR_SH4;

    }

  if (TARGET_SH4A_ARCH)

    {

      assembler_dialect = 1;

      sh_cpu = PROCESSOR_SH4A;

    }

  if (TARGET_SH5)

    {

      sh_cpu = PROCESSOR_SH5;

      target_flags |= MASK_ALIGN_DOUBLE;

      if (TARGET_SHMEDIA_FPU)

        target_flags |= MASK_FMOVD;

      if (TARGET_SHMEDIA)

        {

          /* There are no delay slots on SHmedia.  */

          flag_delayed_branch = 0;

          /* Relaxation isn't yet supported for SHmedia */

          target_flags &= ~MASK_RELAX;

          /* After reload, if conversion does little good but can cause

             ICEs:

             - find_if_block doesn't do anything for SH because we don't

               have conditional execution patterns.  (We use conditional

               move patterns, which are handled differently, and only

               before reload).

             - find_cond_trap doesn't do anything for the SH because we

               don't have conditional traps.

             - find_if_case_1 uses redirect_edge_and_branch_force in

               the only path that does an optimization, and this causes

               an ICE when branch targets are in registers.

             - find_if_case_2 doesn't do anything for the SHmedia after

               reload except when it can redirect a tablejump - and

               that's rather rare.  */

          flag_if_conversion2 = 0;

          if (! strcmp (sh_div_str, "call"))

            sh_div_strategy = SH_DIV_CALL;

          else if (! strcmp (sh_div_str, "call2"))

            sh_div_strategy = SH_DIV_CALL2;

          if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)

            sh_div_strategy = SH_DIV_FP;

          else if (! strcmp (sh_div_str, "inv"))

            sh_div_strategy = SH_DIV_INV;

          else if (! strcmp (sh_div_str, "inv:minlat"))

            sh_div_strategy = SH_DIV_INV_MINLAT;

          else if (! strcmp (sh_div_str, "inv20u"))

            sh_div_strategy = SH_DIV_INV20U;

          else if (! strcmp (sh_div_str, "inv20l"))

            sh_div_strategy = SH_DIV_INV20L;

          else if (! strcmp (sh_div_str, "inv:call2"))

            sh_div_strategy = SH_DIV_INV_CALL2;

          else if (! strcmp (sh_div_str, "inv:call"))

            sh_div_strategy = SH_DIV_INV_CALL;

          else if (! strcmp (sh_div_str, "inv:fp"))

            {

              if (TARGET_FPU_ANY)

                sh_div_strategy = SH_DIV_INV_FP;

              else

                sh_div_strategy = SH_DIV_INV;

            }

          TARGET_CBRANCHDI4 = 0;

          /* Assembler CFI isn't yet fully supported for SHmedia.  */

          flag_dwarf2_cfi_asm = 0;

        }

    }

  else

    {

       /* Only the sh64-elf assembler fully supports .quad properly.  */

       targetm.asm_out.aligned_op.di = NULL;

       targetm.asm_out.unaligned_op.di = NULL;

    }

  if (TARGET_SH1)

    {

      if (! strcmp (sh_div_str, "call-div1"))

        sh_div_strategy = SH_DIV_CALL_DIV1;

      else if (! strcmp (sh_div_str, "call-fp")

               && (TARGET_FPU_DOUBLE

                   || (TARGET_HARD_SH4 && TARGET_SH2E)

                   || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))

        sh_div_strategy = SH_DIV_CALL_FP;

      else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)

        sh_div_strategy = SH_DIV_CALL_TABLE;