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jeremybenn |
;; Scheduling description for Niagara.
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;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Niagara is a single-issue processor.
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(define_automaton "niagara_0")
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(define_cpu_unit "niag_pipe" "niagara_0")
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(define_insn_reservation "niag_5cycle" 5
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "multi,flushw,iflush,trap"))
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"niag_pipe*5")
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(define_insn_reservation "niag_4cycle" 4
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "savew"))
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"niag_pipe*4")
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/* Most basic operations are single-cycle. */
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(define_insn_reservation "niag_ialu" 1
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "ialu,shift,compare,cmove"))
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"niag_pipe")
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(define_insn_reservation "niag_imul" 11
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "imul"))
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"niag_pipe*11")
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(define_insn_reservation "niag_idiv" 72
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "idiv"))
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"niag_pipe*72")
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(define_insn_reservation "niag_branch" 3
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
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"niag_pipe*3")
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(define_insn_reservation "niag_3cycle_load" 3
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "load"))
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"niag_pipe*3")
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(define_insn_reservation "niag_9cycle_load" 9
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpload"))
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"niag_pipe*9")
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(define_insn_reservation "niag_1cycle_store" 1
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "store"))
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"niag_pipe")
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(define_insn_reservation "niag_8cycle_store" 8
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpstore"))
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"niag_pipe*8")
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/* Things incorrectly modelled here:
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* FPADD{s,d}: 26 cycles
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* FPSUB{s,d}: 26 cycles
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* FABSD: 26 cycles
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* F{s,d}TO{s,d}: 26 cycles
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* F{s,d}TO{i,x}: 26 cycles
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* FSMULD: 29 cycles
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*/
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(define_insn_reservation "niag_fmov" 8
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpmove,fpcmove,fpcrmove"))
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"niag_pipe*8")
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(define_insn_reservation "niag_fpcmp" 26
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpcmp"))
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"niag_pipe*26")
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(define_insn_reservation "niag_fmult" 29
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpmul"))
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"niag_pipe*29")
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(define_insn_reservation "niag_fdivs" 54
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpdivs"))
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"niag_pipe*54")
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(define_insn_reservation "niag_fdivd" 83
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fpdivd"))
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"niag_pipe*83")
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/* Things incorrectly modelled here:
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* FPADD{16,32}: 10 cycles
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* FPSUB{16,32}: 10 cycles
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* FALIGNDATA: 10 cycles
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*/
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(define_insn_reservation "niag_vis" 8
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(and (eq_attr "cpu" "niagara")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,gsr,array"))
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"niag_pipe*8")
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