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jeremybenn |
;; Scheduling description for Niagara-2 and Niagara-3.
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;; Copyright (C) 2007, 2011 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; .
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;; Niagara-2 and Niagara-3 are single-issue processors.
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(define_automaton "niagara2_0")
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(define_cpu_unit "niag2_pipe" "niagara2_0")
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(define_insn_reservation "niag2_25cycle" 25
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "flushw"))
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"niag2_pipe*25")
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(define_insn_reservation "niag2_5cycle" 5
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "multi,flushw,iflush,trap"))
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"niag2_pipe*5")
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(define_insn_reservation "niag2_6cycle" 4
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "savew"))
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"niag2_pipe*4")
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/* Most basic operations are single-cycle. */
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(define_insn_reservation "niag2_ialu" 1
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "ialu,shift,compare,cmove"))
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"niag2_pipe")
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(define_insn_reservation "niag2_imul" 5
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "imul"))
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"niag2_pipe*5")
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(define_insn_reservation "niag3_imul" 9
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "imul"))
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"niag2_pipe*9")
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(define_insn_reservation "niag2_idiv" 26
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "idiv"))
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"niag2_pipe*26")
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(define_insn_reservation "niag3_idiv" 31
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "idiv"))
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"niag2_pipe*31")
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(define_insn_reservation "niag2_branch" 5
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
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"niag2_pipe*5")
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(define_insn_reservation "niag2_3cycle_load" 3
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "load,fpload"))
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"niag2_pipe*3")
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(define_insn_reservation "niag2_1cycle_store" 1
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(and (eq_attr "cpu" "niagara2,niagara3")
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(eq_attr "type" "store,fpstore"))
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"niag2_pipe")
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(define_insn_reservation "niag2_fp" 6
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
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"niag2_pipe*6")
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(define_insn_reservation "niag3_fp" 9
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
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"niag2_pipe*9")
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(define_insn_reservation "niag2_fdivs" 19
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "fpdivs"))
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"niag2_pipe*19")
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(define_insn_reservation "niag3_fdivs" 23
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "fpdivs"))
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"niag2_pipe*23")
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(define_insn_reservation "niag2_fdivd" 33
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "fpdivd"))
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"niag2_pipe*33")
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(define_insn_reservation "niag3_fdivd" 37
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "fpdivd"))
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"niag2_pipe*37")
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(define_insn_reservation "niag2_vis" 6
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(and (eq_attr "cpu" "niagara2")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,array,gsr"))
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"niag2_pipe*6")
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(define_insn_reservation "niag3_vis" 9
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(and (eq_attr "cpu" "niagara3")
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(eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist,edge,edgen,array,gsr"))
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"niag2_pipe*9")
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