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jeremybenn |
/* Definitions of target machine for GCC, for Sun SPARC.
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Copyright (C) 2002, 2004, 2007 Free Software Foundation, Inc.
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Contributed by Michael Tiemann (tiemann@cygnus.com).
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64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
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at Cygnus Support.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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. */
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/* 128-bit floating point */
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FLOAT_MODE (TF, 16, ieee_quad_format);
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/* Add any extra modes needed to represent the condition code.
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On the SPARC, we have a "no-overflow" mode which is used when an add or
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subtract insn is used to set the condition code. Different branches are
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used in this case for some operations.
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We also have two modes to indicate that the relevant condition code is
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in the floating-point condition code register. One for comparisons which
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will generate an exception if the result is unordered (CCFPEmode) and
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one for comparisons which will never trap (CCFPmode).
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CCXmode and CCX_NOOVmode are only used by v9. */
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CC_MODE (CCX);
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CC_MODE (CC_NOOV);
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CC_MODE (CCX_NOOV);
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CC_MODE (CCFP);
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CC_MODE (CCFPE);
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/* Vector modes. */
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VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
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VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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VECTOR_MODES (INT, 4); /* V4QI V2HI */
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VECTOR_MODE (INT, DI, 1); /* V1DI */
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VECTOR_MODE (INT, SI, 1); /* V1SI */
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