OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [sparc/] [sparc.opt] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn
; Options for the SPARC port of the compiler
2
;
3
; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
4
;
5
; This file is part of GCC.
6
;
7
; GCC is free software; you can redistribute it and/or modify it under
8
; the terms of the GNU General Public License as published by the Free
9
; Software Foundation; either version 3, or (at your option) any later
10
; version.
11
;
12
; GCC is distributed in the hope that it will be useful, but WITHOUT
13
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15
; License for more details.
16
;
17
; You should have received a copy of the GNU General Public License
18
; along with GCC; see the file COPYING3.  If not see
19
; .
20
 
21
HeaderInclude
22
config/sparc/sparc-opts.h
23
 
24
;; Debug flags
25
TargetVariable
26
unsigned int sparc_debug
27
 
28
mfpu
29
Target Report Mask(FPU)
30
Use hardware FP
31
 
32
mhard-float
33
Target RejectNegative Mask(FPU) MaskExists
34
Use hardware FP
35
 
36
msoft-float
37
Target RejectNegative InverseMask(FPU)
38
Do not use hardware FP
39
 
40
mflat
41
Target Report Mask(FLAT)
42
Use flat register window model
43
 
44
munaligned-doubles
45
Target Report Mask(UNALIGNED_DOUBLES)
46
Assume possible double misalignment
47
 
48
mapp-regs
49
Target Report Mask(APP_REGS)
50
Use ABI reserved registers
51
 
52
mhard-quad-float
53
Target Report RejectNegative Mask(HARD_QUAD)
54
Use hardware quad FP instructions
55
 
56
msoft-quad-float
57
Target Report RejectNegative InverseMask(HARD_QUAD)
58
Do not use hardware quad fp instructions
59
 
60
mv8plus
61
Target Report Mask(V8PLUS)
62
Compile for V8+ ABI
63
 
64
mvis
65
Target Report Mask(VIS)
66
Use UltraSPARC Visual Instruction Set version 1.0 extensions
67
 
68
mvis2
69
Target Report Mask(VIS2)
70
Use UltraSPARC Visual Instruction Set version 2.0 extensions
71
 
72
mvis3
73
Target Report Mask(VIS3)
74
Use UltraSPARC Visual Instruction Set version 3.0 extensions
75
 
76
mfmaf
77
Target Report Mask(FMAF)
78
Use UltraSPARC Fused Multiply-Add extensions
79
 
80
mpopc
81
Target Report Mask(POPC)
82
Use UltraSPARC Population-Count instruction
83
 
84
mptr64
85
Target Report RejectNegative Mask(PTR64)
86
Pointers are 64-bit
87
 
88
mptr32
89
Target Report RejectNegative InverseMask(PTR64)
90
Pointers are 32-bit
91
 
92
m64
93
Target Report RejectNegative Mask(64BIT)
94
Use 64-bit ABI
95
 
96
m32
97
Target Report RejectNegative InverseMask(64BIT)
98
Use 32-bit ABI
99
 
100
mstack-bias
101
Target Report Mask(STACK_BIAS)
102
Use stack bias
103
 
104
mfaster-structs
105
Target Report Mask(FASTER_STRUCTS)
106
Use structs on stronger alignment for double-word copies
107
 
108
mrelax
109
Target
110
Optimize tail call instructions in assembler and linker
111
 
112
mcpu=
113
Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
114
Use features of and schedule code for given CPU
115
 
116
mtune=
117
Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
118
Schedule code for given CPU
119
 
120
Enum
121
Name(sparc_processor_type) Type(enum processor_type)
122
 
123
EnumValue
124
Enum(sparc_processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
125
 
126
EnumValue
127
Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7)
128
 
129
EnumValue
130
Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS)
131
 
132
EnumValue
133
Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8)
134
 
135
EnumValue
136
Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC)
137
 
138
EnumValue
139
Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
140
 
141
EnumValue
142
Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
143
 
144
EnumValue
145
Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
146
 
147
EnumValue
148
Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930)
149
 
150
EnumValue
151
Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934)
152
 
153
EnumValue
154
Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
155
 
156
EnumValue
157
Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET)
158
 
159
EnumValue
160
Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701)
161
 
162
EnumValue
163
Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9)
164
 
165
EnumValue
166
Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
167
 
168
EnumValue
169
Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
170
 
171
EnumValue
172
Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA)
173
 
174
EnumValue
175
Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2)
176
 
177
EnumValue
178
Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3)
179
 
180
EnumValue
181
Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4)
182
 
183
mcmodel=
184
Target RejectNegative Joined Var(sparc_cmodel_string)
185
Use given SPARC-V9 code model
186
 
187
mdebug=
188
Target RejectNegative Joined Var(sparc_debug_string)
189
Enable debug output
190
 
191
mstd-struct-return
192
Target Report RejectNegative Var(sparc_std_struct_return)
193
Enable strict 32-bit psABI struct return checking.
194
 
195
mfix-at697f
196
Target Report RejectNegative Var(sparc_fix_at697f)
197
Enable workaround for single erratum of AT697F processor
198
(corresponding to erratum #13 of AT697E processor)
199
 
200
Mask(LONG_DOUBLE_128)
201
;; Use 128-bit long double
202
 
203
Mask(SPARCLITE)
204
;; Generate code for SPARClite
205
 
206
Mask(SPARCLET)
207
;; Generate code for SPARClet
208
 
209
Mask(V8)
210
;; Generate code for SPARC-V8
211
 
212
Mask(V9)
213
;; Generate code for SPARC-V9
214
 
215
Mask(DEPRECATED_V8_INSNS)
216
;; Generate code that uses the V8 instructions deprecated
217
;; in the V9 architecture.
218
 
219
mmemory-model=
220
Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
221
Specify the memory model in effect for the program.
222
 
223
Enum
224
Name(sparc_memory_model) Type(enum sparc_memory_model_type)
225
 
226
EnumValue
227
Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
228
 
229
EnumValue
230
Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
231
 
232
EnumValue
233
Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
234
 
235
EnumValue
236
Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
237
 
238
EnumValue
239
Enum(sparc_memory_model) String(sc) Value(SMM_SC)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.