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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [tilegx/] [tilegx-generic.md] - Blame information for rev 719

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Line No. Rev Author Line
1 709 jeremybenn 
;; Scheduling description for Tilera TILE-Gx chip.
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;; Copyright (C) 2011, 2012
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;; Free Software Foundation, Inc.
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;; Contributed by Walter Lee (walt@tilera.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
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;; .
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(define_automaton "tile")
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; Make the scheduling automaton an ndfa.
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(automata_option "ndfa")
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; Name the three pipes.
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(define_cpu_unit "X0" "tile")
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(define_cpu_unit "X1" "tile")
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(define_cpu_unit "Y0" "tile")
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(define_cpu_unit "Y1" "tile")
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(define_cpu_unit "Y2" "tile")
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(define_insn_reservation "X0" 1
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  (eq_attr "type" "X0")
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  "X0")
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(define_insn_reservation "X0_2cycle" 2
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  (eq_attr "type" "X0_2cycle")
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  "X0,nothing")
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(define_insn_reservation "X1" 1
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  (eq_attr "type" "X1,X1_branch")
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  "X1")
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(define_insn_reservation "X1_2cycle" 2
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  (eq_attr "type" "X1_2cycle")
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  "X1,nothing")
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(define_insn_reservation "X1_L2" 11
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  (eq_attr "type" "X1_L2")
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  "X1")
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(define_insn_reservation "X1_miss" 80
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  (eq_attr "type" "X1_miss")
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  "X1")
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(define_insn_reservation "X01" 1
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  (eq_attr "type" "X01")
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  "X0|X1")
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(define_insn_reservation "Y0" 1
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  (eq_attr "type" "Y0")
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  "Y0|X0")
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(define_insn_reservation "Y0_2cycle" 2
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  (eq_attr "type" "Y0_2cycle")
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  "Y0|X0,nothing")
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(define_insn_reservation "Y1" 1
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  (eq_attr "type" "Y1")
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  "Y1|X1")
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(define_insn_reservation "Y2" 1
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  (eq_attr "type" "Y2")
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  "Y2|X1")
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(define_insn_reservation "Y2_2cycle" 2
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  (eq_attr "type" "Y2_2cycle")
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  "Y2|X1,nothing")
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(define_insn_reservation "Y2_L2" 11
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  (eq_attr "type" "Y2_L2")
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  "Y2|X1")
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(define_insn_reservation "Y2_miss" 80
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  (eq_attr "type" "Y2_miss")
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  "Y2|X1")
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(define_insn_reservation "Y01" 1
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  (eq_attr "type" "Y01")
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  "Y0|Y1|X0|X1")
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(define_insn_reservation "nothing" 0
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  (eq_attr "type" "nothing")
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  "nothing")
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(define_insn_reservation "cannot_bundle" 1
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  (eq_attr "type" "cannot_bundle")
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  "X0+X1")
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(define_insn_reservation "cannot_bundle_3cycle" 3
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  (eq_attr "type" "cannot_bundle_3cycle")
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  "X0+X1")
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(define_insn_reservation "cannot_bundle_4cycle" 4
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  (eq_attr "type" "cannot_bundle_4cycle")
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  "X0+X1")
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; A bundle must be in either X format or Y format.
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(exclusion_set "X0,X1" "Y0,Y1,Y2")

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