OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [tilegx/] [tilegx-generic.md] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; Scheduling description for Tilera TILE-Gx chip.
2 
;; Copyright (C) 2011, 2012
3 
;; Free Software Foundation, Inc.
4 
;; Contributed by Walter Lee (walt@tilera.com)
5 
;;
6 
;; This file is part of GCC.
7 
;;
8 
;; GCC is free software; you can redistribute it and/or modify it
9 
;; under the terms of the GNU General Public License as published
10 
;; by the Free Software Foundation; either version 3, or (at your
11 
;; option) any later version.
12 
;;
13 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
;; License for more details.
17 
;;
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
(define_automaton "tile")
23 
 
24 
; Make the scheduling automaton an ndfa.
25 
(automata_option "ndfa")
26 
 
27 
; Name the three pipes.
28 
(define_cpu_unit "X0" "tile")
29 
(define_cpu_unit "X1" "tile")
30 
(define_cpu_unit "Y0" "tile")
31 
(define_cpu_unit "Y1" "tile")
32 
(define_cpu_unit "Y2" "tile")
33 
 
34 
(define_insn_reservation "X0" 1
35 
  (eq_attr "type" "X0")
36 
  "X0")
37 
 
38 
(define_insn_reservation "X0_2cycle" 2
39 
  (eq_attr "type" "X0_2cycle")
40 
  "X0,nothing")
41 
 
42 
(define_insn_reservation "X1" 1
43 
  (eq_attr "type" "X1,X1_branch")
44 
  "X1")
45 
 
46 
(define_insn_reservation "X1_2cycle" 2
47 
  (eq_attr "type" "X1_2cycle")
48 
  "X1,nothing")
49 
 
50 
(define_insn_reservation "X1_L2" 11
51 
  (eq_attr "type" "X1_L2")
52 
  "X1")
53 
 
54 
(define_insn_reservation "X1_miss" 80
55 
  (eq_attr "type" "X1_miss")
56 
  "X1")
57 
 
58 
(define_insn_reservation "X01" 1
59 
  (eq_attr "type" "X01")
60 
  "X0|X1")
61 
 
62 
(define_insn_reservation "Y0" 1
63 
  (eq_attr "type" "Y0")
64 
  "Y0|X0")
65 
 
66 
(define_insn_reservation "Y0_2cycle" 2
67 
  (eq_attr "type" "Y0_2cycle")
68 
  "Y0|X0,nothing")
69 
 
70 
(define_insn_reservation "Y1" 1
71 
  (eq_attr "type" "Y1")
72 
  "Y1|X1")
73 
 
74 
(define_insn_reservation "Y2" 1
75 
  (eq_attr "type" "Y2")
76 
  "Y2|X1")
77 
 
78 
(define_insn_reservation "Y2_2cycle" 2
79 
  (eq_attr "type" "Y2_2cycle")
80 
  "Y2|X1,nothing")
81 
 
82 
(define_insn_reservation "Y2_L2" 11
83 
  (eq_attr "type" "Y2_L2")
84 
  "Y2|X1")
85 
 
86 
(define_insn_reservation "Y2_miss" 80
87 
  (eq_attr "type" "Y2_miss")
88 
  "Y2|X1")
89 
 
90 
(define_insn_reservation "Y01" 1
91 
  (eq_attr "type" "Y01")
92 
  "Y0|Y1|X0|X1")
93 
 
94 
(define_insn_reservation "nothing" 0
95 
  (eq_attr "type" "nothing")
96 
  "nothing")
97 
 
98 
(define_insn_reservation "cannot_bundle" 1
99 
  (eq_attr "type" "cannot_bundle")
100 
  "X0+X1")
101 
 
102 
(define_insn_reservation "cannot_bundle_3cycle" 3
103 
  (eq_attr "type" "cannot_bundle_3cycle")
104 
  "X0+X1")
105 
 
106 
(define_insn_reservation "cannot_bundle_4cycle" 4
107 
  (eq_attr "type" "cannot_bundle_4cycle")
108 
  "X0+X1")
109 
 
110 
 
111 
; A bundle must be in either X format or Y format.
112 
(exclusion_set "X0,X1" "Y0,Y1,Y2")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.