OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [tilegx/] [tilegx.md] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 709 jeremybenn 
;; Machine description for Tilera TILE-Gx chip for GCC.
2 
;; Copyright (C) 2011, 2012
3 
;; Free Software Foundation, Inc.
4 
;; Contributed by Walter Lee (walt@tilera.com)
5 
;;
6 
;; This file is part of GCC.
7 
;;
8 
;; GCC is free software; you can redistribute it and/or modify it
9 
;; under the terms of the GNU General Public License as published
10 
;; by the Free Software Foundation; either version 3, or (at your
11 
;; option) any later version.
12 
;;
13 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16 
;; License for more details.
17 
;;
18 
;; You should have received a copy of the GNU General Public License
19 
;; along with GCC; see the file COPYING3.  If not see
20 
;; .
21 
 
22 
(define_constants [
23 
  ;;
24 
  ;; The following represent intrinsic insns, organized by latency.
25 
  ;;
26 
 
27 
  ;; single cycle
28 
  (UNSPEC_INSN_ADDR_SHL16INSLI         1)
29 
  (UNSPEC_INSN_BFEXTS                  2)
30 
  (UNSPEC_INSN_BFEXTU                  3)
31 
  (UNSPEC_INSN_BFINS                   4)
32 
  (UNSPEC_INSN_CRC32_32                5)
33 
  (UNSPEC_INSN_CRC32_8                 6)
34 
  (UNSPEC_INSN_DBLALIGN                7)
35 
  (UNSPEC_INSN_DBLALIGN2               8)
36 
  (UNSPEC_INSN_DBLALIGN4               9)
37 
  (UNSPEC_INSN_DBLALIGN6               10)
38 
  (UNSPEC_INSN_DRAIN                   11)
39 
  (UNSPEC_INSN_DTLBPR                  12)
40 
  (UNSPEC_INSN_FINV                    13)
41 
  (UNSPEC_INSN_FLUSH                   14)
42 
  (UNSPEC_INSN_FLUSHWB                 15)
43 
  (UNSPEC_INSN_FNOP                    16)
44 
  (UNSPEC_INSN_ICOH                    17)
45 
  (UNSPEC_INSN_ILL                     18)
46 
  (UNSPEC_INSN_INFO                    19)
47 
  (UNSPEC_INSN_INFOL                   20)
48 
  (UNSPEC_INSN_INV                     21)
49 
  (UNSPEC_INSN_LNK                     22)
50 
  (UNSPEC_INSN_MFSPR                   23)
51 
  (UNSPEC_INSN_MM                      24)
52 
  (UNSPEC_INSN_MTSPR                   25)
53 
  (UNSPEC_INSN_NAP                     26)
54 
  (UNSPEC_INSN_PREFETCH_L1_FAULT       27)
55 
  (UNSPEC_INSN_PREFETCH_L2_FAULT       28)
56 
  (UNSPEC_INSN_PREFETCH_L3_FAULT       29)
57 
  (UNSPEC_INSN_REVBITS                 30)
58 
  (UNSPEC_INSN_SHUFFLEBYTES            31)
59 
  (UNSPEC_INSN_TBLIDXB0                32)
60 
  (UNSPEC_INSN_TBLIDXB1                33)
61 
  (UNSPEC_INSN_TBLIDXB2                34)
62 
  (UNSPEC_INSN_TBLIDXB3                35)
63 
  (UNSPEC_INSN_V1AVGU                  36)
64 
  (UNSPEC_INSN_V2AVGS                  37)
65 
  (UNSPEC_INSN_WH64                    38)
66 
 
67 
  ;; 2 cycles
68 
  (UNSPEC_INSN_CMUL                    100)
69 
  (UNSPEC_INSN_CMULA                   101)
70 
  (UNSPEC_INSN_CMULAF                  102)
71 
  (UNSPEC_INSN_CMULFR                  103)
72 
  (UNSPEC_INSN_CMULHR                  104)
73 
  (UNSPEC_INSN_CMULF                   105)
74 
  (UNSPEC_INSN_CMULH                   106)
75 
  (UNSPEC_INSN_EXCH                    107)
76 
  (UNSPEC_INSN_FDOUBLE_ADDSUB          108)
77 
  (UNSPEC_INSN_FDOUBLE_ADD_FLAGS       109)
78 
  (UNSPEC_INSN_FDOUBLE_MUL_FLAGS       110)
79 
  (UNSPEC_INSN_FDOUBLE_PACK1           111)
80 
  (UNSPEC_INSN_FDOUBLE_PACK2           112)
81 
  (UNSPEC_INSN_FDOUBLE_SUB_FLAGS       113)
82 
  (UNSPEC_INSN_FDOUBLE_UNPACK_MAX      114)
83 
  (UNSPEC_INSN_FDOUBLE_UNPACK_MIN      115)
84 
  (UNSPEC_INSN_FETCHADDGEZ             116)
85 
  (UNSPEC_INSN_FSINGLE_ADD1            117)
86 
  (UNSPEC_INSN_FSINGLE_ADDSUB2         118)
87 
  (UNSPEC_INSN_FSINGLE_MUL1            119)
88 
  (UNSPEC_INSN_FSINGLE_MUL2            120)
89 
  (UNSPEC_INSN_FSINGLE_PACK1           121)
90 
  (UNSPEC_INSN_FSINGLE_PACK2           122)
91 
  (UNSPEC_INSN_FSINGLE_SUB1            123)
92 
  (UNSPEC_INSN_MULAX                   124)
93 
  (UNSPEC_INSN_MULA_HS_HS              125)
94 
  (UNSPEC_INSN_MULA_HS_HU              126)
95 
  (UNSPEC_INSN_MULA_HS_LS              127)
96 
  (UNSPEC_INSN_MULA_HS_LU              128)
97 
  (UNSPEC_INSN_MULA_HU_HU              129)
98 
  (UNSPEC_INSN_MULA_HU_LS              130)
99 
  (UNSPEC_INSN_MULA_HU_LU              131)
100 
  (UNSPEC_INSN_MULA_LS_LS              132)
101 
  (UNSPEC_INSN_MULA_LS_LU              133)
102 
  (UNSPEC_INSN_MULA_LU_LU              134)
103 
  (UNSPEC_INSN_MUL_HS_HS               135)
104 
  (UNSPEC_INSN_MUL_HS_HU               136)
105 
  (UNSPEC_INSN_MUL_HS_LS               137)
106 
  (UNSPEC_INSN_MUL_HS_LU               138)
107 
  (UNSPEC_INSN_MUL_HU_HU               139)
108 
  (UNSPEC_INSN_MUL_HU_LS               140)
109 
  (UNSPEC_INSN_MUL_HU_LU               141)
110 
  (UNSPEC_INSN_MUL_LS_LS               142)
111 
  (UNSPEC_INSN_MUL_LS_LU               143)
112 
  (UNSPEC_INSN_MUL_LU_LU               144)
113 
  (UNSPEC_INSN_V1ADIFFU                145)
114 
  (UNSPEC_INSN_V1DDOTPU                146)
115 
  (UNSPEC_INSN_V1DDOTPUA               147)
116 
  (UNSPEC_INSN_V1DDOTPUS               148)
117 
  (UNSPEC_INSN_V1DDOTPUSA              149)
118 
  (UNSPEC_INSN_V1DOTP                  150)
119 
  (UNSPEC_INSN_V1DOTPA                 151)
120 
  (UNSPEC_INSN_V1DOTPU                 152)
121 
  (UNSPEC_INSN_V1DOTPUA                153)
122 
  (UNSPEC_INSN_V1DOTPUS                154)
123 
  (UNSPEC_INSN_V1DOTPUSA               155)
124 
  (UNSPEC_INSN_V1SADAU                 156)
125 
  (UNSPEC_INSN_V1SADU                  157)
126 
  (UNSPEC_INSN_V2ADIFFS                158)
127 
  (UNSPEC_INSN_V2DOTP                  159)
128 
  (UNSPEC_INSN_V2DOTPA                 160)
129 
  (UNSPEC_INSN_V2MULFSC                161)
130 
  (UNSPEC_INSN_V2SADAS                 162)
131 
  (UNSPEC_INSN_V2SADAU                 163)
132 
  (UNSPEC_INSN_V2SADS                  164)
133 
  (UNSPEC_INSN_V2SADU                  165)
134 
 
135 
  ;; 11 cycles
136 
  (UNSPEC_INSN_CMPEXCH                 200)
137 
 
138 
  ;;
139 
  ;; The following are special insns.
140 
  ;;
141 
 
142 
  ;; Blockage
143 
  (UNSPEC_BLOCKAGE                     201)
144 
 
145 
  ;; Lnk and its label
146 
  (UNSPEC_LNK_AND_LABEL                202)
147 
 
148 
  ;; Memory fence
149 
  (UNSPEC_MF                           203)
150 
 
151 
  ;; Insns generating difference of two labels
152 
  (UNSPEC_MOV_PCREL_STEP3              204)
153 
 
154 
  ;; Latency specifying loads.
155 
  (UNSPEC_LATENCY_L2                   205)
156 
  (UNSPEC_LATENCY_MISS                 206)
157 
 
158 
  ;; A pseudo-op that prevents network operations from being ordered.
159 
  (UNSPEC_NETWORK_BARRIER              207)
160 
 
161 
  ;; Operations that access network registers.
162 
  (UNSPEC_NETWORK_RECEIVE              208)
163 
  (UNSPEC_NETWORK_SEND                 209)
164 
 
165 
  ;; Stack protector operations
166 
  (UNSPEC_SP_SET                       210)
167 
  (UNSPEC_SP_TEST                      211)
168 
 
169 
  ;; This is used to move a value to a SPR.
170 
  (UNSPEC_SPR_MOVE                     212)
171 
 
172 
  ;; A call to __tls_get_addr
173 
  (UNSPEC_TLS_GD_CALL                  213)
174 
 
175 
  ;; An opaque TLS "add" operation for TLS general dynamic model
176 
  ;; access.
177 
  (UNSPEC_TLS_GD_ADD                   214)
178 
 
179 
  ;; An opaque TLS "load" operation for TLS initial exec model access.
180 
  (UNSPEC_TLS_IE_LOAD                  215)
181 
 
182 
  ;; An opaque TLS "add" operation for TLS access.
183 
  (UNSPEC_TLS_ADD                      216)
184 
 
185 
  ;; Atomics
186 
  (UNSPEC_ATOMIC                       217)
187 
  (UNSPEC_CMPXCHG                      218)
188 
  (UNSPEC_XCHG                         219)
189 
 
190 
  ;;
191 
  ;; The following are operands.
192 
  ;;
193 
  (UNSPEC_HW0                          300)
194 
  (UNSPEC_HW1                          301)
195 
  (UNSPEC_HW2                          302)
196 
  (UNSPEC_HW3                          303)
197 
  (UNSPEC_HW0_LAST                     304)
198 
  (UNSPEC_HW1_LAST                     305)
199 
  (UNSPEC_HW2_LAST                     306)
200 
 
201 
  (UNSPEC_HW0_PCREL                    307)
202 
  (UNSPEC_HW1_LAST_PCREL               308)
203 
 
204 
  (UNSPEC_HW0_GOT                      309)
205 
  (UNSPEC_HW0_LAST_GOT                 310)
206 
  (UNSPEC_HW1_LAST_GOT                 311)
207 
 
208 
  (UNSPEC_HW0_TLS_GD                   312)
209 
  (UNSPEC_HW1_LAST_TLS_GD              313)
210 
 
211 
  (UNSPEC_HW0_TLS_IE                   314)
212 
  (UNSPEC_HW1_LAST_TLS_IE              315)
213 
 
214 
  (UNSPEC_HW0_TLS_LE                   316)
215 
  (UNSPEC_HW1_LAST_TLS_LE              317)
216 
 
217 
  ;; This is used to wrap around the addresses of non-temporal load/store
218 
  ;; intrinsics.
219 
  (UNSPEC_NON_TEMPORAL                 318)
220 
])
221 
 
222 
;; Mark the last instruction of various latencies, used to
223 
;; determine the rtx costs of unspec insns.
224 
(define_constants [
225 
  (TILEGX_LAST_LATENCY_1_INSN           99)
226 
  (TILEGX_LAST_LATENCY_2_INSN          199)
227 
  (TILEGX_LAST_LATENCY_INSN            299)
228 
])
229 
 
230 
(define_constants [
231 
  (TILEGX_NETREG_IDN0 0)
232 
  (TILEGX_NETREG_IDN1 1)
233 
  (TILEGX_NETREG_UDN0 2)
234 
  (TILEGX_NETREG_UDN1 3)
235 
  (TILEGX_NETREG_UDN2 4)
236 
  (TILEGX_NETREG_UDN3 5)
237 
])
238 
 
239 
(define_constants [
240 
  (TILEGX_CMPEXCH_REG  66)
241 
  (TILEGX_NETORDER_REG 67)
242 
])
243 
 
244 
 
245 
;; Operand and operator predicates and constraints
246 
 
247 
(include "predicates.md")
248 
(include "constraints.md")
249 
(include "tilegx-generic.md")
250 
 
251 
;; Define an insn type attribute.  This defines what pipes things can go in.
252 
(define_attr "type"
253 
  "X0,X0_2cycle,X1,X1_branch,X1_2cycle,X1_L2,X1_miss,X01,Y0,Y0_2cycle,Y1,Y2,Y2_2cycle,Y2_L2,Y2_miss,Y01,cannot_bundle,cannot_bundle_3cycle,cannot_bundle_4cycle,nothing"
254 
  (const_string "Y01"))
255 
 
256 
(define_attr "length" ""
257 
   (cond [(eq_attr "type" "X1_branch")
258 
          (if_then_else
259 
           (and (le (minus (match_dup 0) (pc)) (const_int 524280))
260 
                (le (minus (pc) (match_dup 0)) (const_int 524288)))
261 
           (const_int 8)
262 
           (const_int 16))
263 
          ]
264 
         (const_int 8)))
265 
 
266 
 
267 
;; Define some iterators.
268 
(define_mode_iterator IVMODE [SI DI V8QI V4HI V2SI])
269 
(define_mode_iterator IVNMODE [SI V8QI V4HI V2SI])
270 
(define_mode_iterator I48MODE [SI DI])
271 
(define_mode_iterator I48MODE2 [SI DI])
272 
(define_mode_iterator I124MODE [QI HI SI])
273 
(define_mode_iterator FI48MODE [SF DF SI DI])
274 
(define_mode_iterator VEC48MODE [V8QI V4HI])
275 
(define_mode_iterator VEC248MODE [V8QI V4HI V2SI])
276 
 
277 
(define_mode_attr n [(QI "1") (HI "2") (SI "4") (DI "")
278 
                     (V8QI "1") (V4HI "2") (V2SI "4")])
279 
(define_mode_attr x [(SI "x") (DI "")])
280 
(define_mode_attr bitsuffix [(SI "_32bit") (DI "")])
281 
(define_mode_attr four_if_si [(SI "4") (DI "")])
282 
(define_mode_attr four_s_if_si [(SI "4s") (DI "")])
283 
(define_mode_attr nbits [(SI "5") (DI "6")])
284 
(define_mode_attr shift_pipe [(SI "X01") (DI "*")])
285 
 
286 
;; Code iterator for either extend.
287 
(define_code_iterator any_extend [sign_extend zero_extend])
288 
 
289 
;; Code iterator for all three shifts.
290 
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
291 
 
292 
;; Code iterator for all byte ops without immediate variants.
293 
(define_code_iterator v1op [us_minus us_plus minus ne le leu mult])
294 
 
295 
;; Code iterator for all 2-byte vector ops without immediate variants.
296 
(define_code_iterator v2op [ss_minus ss_plus minus ne le leu])
297 
 
298 
;; Code iterator for all 4-byte vector ops without immediate variants.
299 
(define_code_iterator v4op [ss_minus ss_plus minus plus])
300 
 
301 
;; Code iterator for all byte vector ops with immediate variants.
302 
(define_code_iterator v1op_immed [plus umax umin eq lt ltu])
303 
 
304 
;; Code iterator for all 2-byte vector ops with immediate variants.
305 
(define_code_iterator v2op_immed [plus smax smin eq lt ltu])
306 
 
307 
;; Code iterator for all 2-byte vector shifts without immediate variants.
308 
(define_code_iterator v2shift [ss_ashift])
309 
 
310 
;; Code iterator for all 4-byte vector shifts without immediate variants.
311 
(define_code_iterator v4shift [ashift ashiftrt lshiftrt ss_ashift])
312 
 
313 
;;  expands to the name of the optab for a particular code.
314 
(define_code_attr optab [(ashift "ashl")
315 
                         (ashiftrt "ashr")
316 
                         (lshiftrt "lshr")
317 
                         (ss_ashift "ssashl")
318 
                         (eq "seq")
319 
                         (ne "sne")
320 
                         (lt "slt")
321 
                         (ltu "sltu")
322 
                         (le "sle")
323 
                         (leu "sleu")
324 
                         (minus "sub")
325 
                         (plus "add")
326 
                         (mult "mul")
327 
                         (smax "smax")
328 
                         (smin "smin")
329 
                         (ss_minus "sssub")
330 
                         (ss_plus "ssadd")
331 
                         (umax "umax")
332 
                         (umin "umin")
333 
                         (us_minus "ussub")
334 
                         (us_plus "usadd")
335 
                         ])
336 
 
337 
;;  expands to the name of the insn that implements a particular
338 
;; code.
339 
(define_code_attr insn [(ashift "shl")
340 
                        (ashiftrt "shrs")
341 
                        (lshiftrt "shru")
342 
                        (ss_ashift "shlsc")
343 
                        (eq "cmpeq")
344 
                        (ne "cmpne")
345 
                        (lt "cmplts")
346 
                        (ltu "cmpltu")
347 
                        (le "cmples")
348 
                        (leu "cmpleu")
349 
                        (minus "sub")
350 
                        (plus "add")
351 
                        (mult "multu")
352 
                        (smax "maxs")
353 
                        (smin "mins")
354 
                        (umax "maxu")
355 
                        (umin "minu")
356 
                        (ss_minus "subsc")
357 
                        (ss_plus  "addsc")
358 
                        (us_minus "subuc")
359 
                        (us_plus  "adduc")
360 
                        ])
361 
 
362 
;;  expands to the pipeline resource that contains the
363 
;; particular code.
364 
(define_code_attr pipe [(ashift "X01")
365 
                        (ashiftrt "X01")
366 
                        (lshiftrt "X01")
367 
                        (ss_ashift "X01")
368 
                        (eq "X01")
369 
                        (ne "X01")
370 
                        (lt "X01")
371 
                        (ltu "X01")
372 
                        (le "X01")
373 
                        (leu "X01")
374 
                        (minus "X01")
375 
                        (plus "X01")
376 
                        (mult "X0_2cycle")
377 
                        (smax "X01")
378 
                        (smin "X01")
379 
                        (umax "X01")
380 
                        (umin "X01")
381 
                        (ss_minus "X01")
382 
                        (ss_plus  "X01")
383 
                        (us_minus "X01")
384 
                        (us_plus  "X01")
385 
                        ])
386 
 
387 
;;  indicates whether a particular code is commutative, using
388 
;; the "%" commutative opterator constraint.
389 
(define_code_attr comm [(ashift "")
390 
                        (ashiftrt "")
391 
                        (lshiftrt "")
392 
                        (ss_ashift "")
393 
                        (eq "%")
394 
                        (ne "%")
395 
                        (lt "")
396 
                        (ltu "")
397 
                        (le "")
398 
                        (leu "")
399 
                        (minus "")
400 
                        (plus "%")
401 
                        (mult "%")
402 
                        (smin "%")
403 
                        (umin "%")
404 
                        (smax "%")
405 
                        (umax "%")
406 
                        (ss_plus "%")
407 
                        (us_plus "%")
408 
                        (ss_minus "")
409 
                        (us_minus "")
410 
                        ])
411 
 
412 
;;  is the load/store extension suffix.
413 
(define_code_attr s [(zero_extend "u")
414 
                     (sign_extend "s")])
415 
 
416 
;; Code for packing two 2-byte vectors.
417 
(define_code_iterator v2pack [truncate us_truncate])
418 
 
419 
;;  expands to the part of the optab name describing how
420 
;; two vectors are packed.
421 
(define_code_attr pack_optab [(truncate "trunc")
422 
                              (us_truncate "usat")
423 
                              (ss_truncate "ssat")])
424 
 
425 
;;  expands to the insn that implements a particular vector
426 
;; packing code.
427 
(define_code_attr pack_insn [(truncate "packl")
428 
                             (us_truncate "packuc")
429 
                             (ss_truncate "packsc")])
430 
 
431 
;;
432 
;; The basic data move insns.
433 
;;
434 
 
435 
(define_expand "movqi"
436 
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
437 
        (match_operand:QI 1 "nonautoinc_operand" ""))]
438 
  ""
439 
{
440 
  if (tilegx_expand_mov (QImode, operands))
441 
    DONE;
442 
})
443 
 
444 
(define_insn "*movqi_insn"
445 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,U,m")
446 
        (match_operand:QI 1 "move_operand"         "r,I,U,m,rO,rO"))]
447 
  "(register_operand (operands[0], QImode)
448 
    || reg_or_0_operand (operands[1], QImode))"
449 
  "@
450 
   move\t%0, %r1
451 
   movei\t%0, %1
452 
   ld1u\t%0, %1
453 
   ld1u_add\t%0, %I1, %i1
454 
   st1\t%0, %r1
455 
   st1_add\t%I0, %r1, %i0"
456 
  [(set_attr "type" "*,*,Y2_2cycle,X1_2cycle,Y2,X1")])
457 
 
458 
(define_expand "movhi"
459 
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
460 
        (match_operand:HI 1 "nonautoinc_operand" ""))]
461 
  ""
462 
{
463 
  if (tilegx_expand_mov (HImode, operands))
464 
    DONE;
465 
})
466 
 
467 
(define_insn "*movhi_insn"
468 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,U,m")
469 
        (match_operand:HI 1 "move_operand"         "r,I,JT,U,m,rO,rO"))]
470 
  "(register_operand (operands[0], HImode)
471 
    || reg_or_0_operand (operands[1], HImode))"
472 
  "@
473 
   move\t%0, %r1
474 
   movei\t%0, %1
475 
   moveli\t%0, %H1
476 
   ld2u\t%0, %1
477 
   ld2u_add\t%0, %I1, %i1
478 
   st2\t%0, %r1
479 
   st2_add\t%I0, %r1, %i0"
480 
  [(set_attr "type" "*,*,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
481 
 
482 
(define_expand "movsi"
483 
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
484 
        (match_operand:SI 1 "nonautoinc_operand" ""))]
485 
  ""
486 
{
487 
  if (tilegx_expand_mov (SImode, operands))
488 
    DONE;
489 
})
490 
 
491 
(define_insn "*movsi_insn"
492 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,U,m")
493 
        (match_operand:SI 1 "move_operand"         "r,I,JT,K,U,m,rO,rO"))]
494 
  "(register_operand (operands[0], SImode)
495 
    || reg_or_0_operand (operands[1], SImode))"
496 
  "@
497 
   move\t%0, %r1
498 
   movei\t%0, %1
499 
   moveli\t%0, %H1
500 
   shl16insli\t%0, zero, %h1
501 
   ld4s\t%0, %1
502 
   ld4s_add\t%0, %I1, %i1
503 
   st4\t%0, %r1
504 
   st4_add\t%I0, %r1, %i0"
505 
  [(set_attr "type" "*,*,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
506 
 
507 
(define_expand "movdi"
508 
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
509 
        (match_operand:DI 1 "nonautoinc_operand" ""))]
510 
  ""
511 
{
512 
  if (tilegx_expand_mov (DImode, operands))
513 
    DONE;
514 
})
515 
 
516 
(define_insn "*movdi_insn"
517 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,r,U,m")
518 
        (match_operand:DI 1 "move_operand"         "r,I,JT,K,N,P,U,m,rO,rO"))]
519 
  "(register_operand (operands[0], DImode)
520 
    || reg_or_0_operand (operands[1], DImode))"
521 
  "@
522 
   move\t%0, %r1
523 
   movei\t%0, %1
524 
   moveli\t%0, %H1
525 
   shl16insli\t%0, zero, %h1
526 
   v1addi\t%0, zero, %j1
527 
   v2addi\t%0, zero, %h1
528 
   ld\t%0, %1
529 
   ld_add\t%0, %I1, %i1
530 
   st\t%0, %r1
531 
   st_add\t%I0, %r1, %i0"
532 
  [(set_attr "type" "*,*,X01,X01,X01,X01,Y2_2cycle,X1_2cycle,Y2,X1")])
533 
 
534 
(define_expand "movmisalign"
535 
  [(set (match_operand:VEC248MODE 0 "nonautoincmem_nonimmediate_operand" "")
536 
        (match_operand:VEC248MODE 1 "nonautoincmem_general_operand" ""))]
537 
  ""
538 
{
539 
  tilegx_expand_movmisalign (mode, operands);
540 
  DONE;
541 
})
542 
 
543 
(define_expand "movsf"
544 
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
545 
        (match_operand:SF 1 "general_operand" ""))]
546 
  ""
547 
{
548 
  /* Materialize immediates using clever SImode code, but don't
549 
     do this after reload starts, since gen_lowpart will choke
550 
     during reload if given an illegitimate address. */
551 
  if (immediate_operand (operands[1], SFmode)
552 
      && operands[1] != const0_rtx
553 
      && (register_operand (operands[0], SFmode)
554 
          || (!reload_in_progress && !reload_completed)))
555 
    {
556 
      emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]),
557 
                            gen_lowpart (SImode, operands[1])));
558 
      DONE;
559 
    }
560 
})
561 
 
562 
(define_insn "*movsf"
563 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,U,m")
564 
        (match_operand:SF 1 "general_operand" "rO,U,m,rO,rO"))]
565 
  ""
566 
  "@
567 
   move\t%0, %r1
568 
   ld4s\t%0, %1
569 
   ld4s_add\t%0, %I1, %i1
570 
   st4\t%0, %r1
571 
   st4_add\t%I0, %r1, %i0"
572 
  [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
573 
 
574 
(define_expand "movdf"
575 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
576 
        (match_operand:DF 1 "general_operand" ""))]
577 
  ""
578 
{
579 
  /* Materialize immediates using clever DImode code, but don't
580 
     do this after reload starts, since gen_lowpart will choke
581 
     during reload if given an illegitimate address. */
582 
  if (immediate_operand (operands[1], DFmode)
583 
      && operands[1] != const0_rtx
584 
      && (register_operand (operands[0], DFmode)
585 
          || (!reload_in_progress && !reload_completed)))
586 
    {
587 
      emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
588 
                            gen_lowpart (DImode, operands[1])));
589 
      DONE;
590 
    }
591 
})
592 
 
593 
(define_insn "*movdf"
594 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,U,m")
595 
        (match_operand:DF 1 "general_operand" "rO,U,m,rO,rO"))]
596 
  ""
597 
  "@
598 
   move\t%0, %r1
599 
   ld\t%0, %1
600 
   ld_add\t%0, %I1, %i1
601 
   st\t%0, %r1
602 
   st_add\t%I0, %r1, %i0"
603 
  [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
604 
 
605 
(define_expand "mov"
606 
  [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "")
607 
        (match_operand:VEC248MODE 1 "general_operand" ""))]
608 
  ""
609 
{
610 
  /* Materialize immediates using clever DImode code, but don't
611 
     do this after reload starts, since gen_lowpart will choke
612 
     during reload if given an illegitimate address. */
613 
  if (immediate_operand (operands[1], mode)
614 
      && operands[1] != const0_rtx
615 
      && (register_operand (operands[0], mode)
616 
          || (!reload_in_progress && !reload_completed)))
617 
    {
618 
      emit_insn (gen_movdi (gen_lowpart (DImode, operands[0]),
619 
                            gen_lowpart (DImode, operands[1])));
620 
      DONE;
621 
    }
622 
})
623 
 
624 
(define_insn "*mov"
625 
  [(set (match_operand:VEC248MODE 0 "nonimmediate_operand" "=r,r,r,U,m")
626 
        (match_operand:VEC248MODE 1 "general_operand" "rO,U,m,rO,rO"))]
627 
  ""
628 
  "@
629 
   move\t%0, %r1
630 
   ld\t%0, %1
631 
   ld_add\t%0, %I1, %i1
632 
   st\t%0, %r1
633 
   st_add\t%I0, %r1, %i0"
634 
  [(set_attr "type" "*,Y2_2cycle,X1_2cycle,Y2,X1")])
635 
 
636 
(define_insn "movstrictqi"
637 
  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
638 
        (match_operand:QI 1 "reg_or_0_operand" "rO"))]
639 
  ""
640 
  "bfins\t%0, %r1, 0, 7"
641 
  [(set_attr "type" "X0")])
642 
 
643 
(define_insn "movstricthi"
644 
  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
645 
        (match_operand:HI 1 "reg_or_0_operand" "rO"))]
646 
  ""
647 
  "bfins\t%0, %r1, 0, 15"
648 
  [(set_attr "type" "X0")])
649 
 
650 
(define_insn "movstrictsi"
651 
  [(set (strict_low_part (match_operand:SI 0 "register_operand" "+r"))
652 
        (match_operand:SI 1 "reg_or_0_operand" "rO"))]
653 
  ""
654 
  "bfins\t%0, %r1, 0, 31"
655 
  [(set_attr "type" "X0")])
656 
 
657 
 
658 
;;
659 
;; Bit-field extracts/inserts
660 
;;
661 
 
662 
(define_expand "insv"
663 
  [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
664 
                         (match_operand:DI 1 "u6bit_cint_operand" "")
665 
                         (match_operand:DI 2 "u6bit_cint_operand" ""))
666 
        (match_operand:DI 3 "reg_or_cint_operand" ""))]
667 
  ""
668 
{
669 
  rtx first_rtx = operands[2];
670 
  HOST_WIDE_INT first = INTVAL (first_rtx);
671 
  HOST_WIDE_INT width = INTVAL (operands[1]);
672 
  rtx v = operands[3];
673 
 
674 
  if (CONST_INT_P (v))
675 
    {
676 
      /* Which bits are we affecting? */
677 
      HOST_WIDE_INT mask = ((((HOST_WIDE_INT) 1) << width) - 1) << first;
678 
 
679 
      /* Extract just the bits we need, sign extending them to make the
680 
         constant easier to materialize in a register. */
681 
      int shift = sizeof(HOST_WIDE_INT) * 8 - width;
682 
      HOST_WIDE_INT n = (INTVAL (v) << shift) >> shift;
683 
 
684 
      if (n == 0)
685 
        {
686 
          /* We are setting every bit in the bitfield to zero. Try to use
687 
             andi instead, since that is more efficient. */
688 
          rtx mask_rtx = GEN_INT (~mask);
689 
          if (satisfies_constraint_I (mask_rtx))
690 
            {
691 
              emit_insn (gen_anddi3 (operands[0], operands[0], mask_rtx));
692 
              DONE;
693 
            }
694 
 
695 
          operands[3] = const0_rtx;
696 
        }
697 
      else
698 
        {
699 
          if (n == -1)
700 
            {
701 
              /* We are setting every bit in the bitfield to one. Try to use
702 
                 ori instead, since that is more efficient. */
703 
              rtx mask_rtx = GEN_INT (mask);
704 
              if (satisfies_constraint_I (mask_rtx))
705 
                {
706 
                  emit_insn (gen_iordi3 (operands[0], operands[0], mask_rtx));
707 
                  DONE;
708 
                }
709 
            }
710 
 
711 
          if (!can_create_pseudo_p ())
712 
            FAIL;
713 
 
714 
          operands[3] = force_reg (DImode, GEN_INT (n));
715 
        }
716 
    }
717 
})
718 
 
719 
(define_insn "*insv_tblidxb0"
720 
  [(set (zero_extract:DI
721 
         (match_operand:DI 0 "register_operand" "+r")
722 
         (const_int 8)
723 
         (const_int 2))
724 
        (match_operand:DI 1 "register_operand" "rO"))]
725 
  ""
726 
  "tblidxb0\t%0, %r1"
727 
  [(set_attr "type" "Y0")])
728 
 
729 
(define_insn "*insv_tblidxb1"
730 
  [(set (zero_extract:DI
731 
         (match_operand:DI 0 "register_operand" "+r")
732 
         (const_int 8)
733 
         (const_int 2))
734 
        (zero_extract:DI
735 
         (const_int 8)
736 
         (const_int 8)
737 
        (match_operand:DI 1 "register_operand" "rO")))]
738 
  ""
739 
  "tblidxb1\t%0, %r1"
740 
  [(set_attr "type" "Y0")])
741 
 
742 
(define_insn "*insv_tblidxb2"
743 
  [(set (zero_extract:DI
744 
         (match_operand:DI 0 "register_operand" "+r")
745 
         (const_int 8)
746 
         (const_int 2))
747 
        (zero_extract:DI
748 
         (const_int 8)
749 
         (const_int 16)
750 
        (match_operand:DI 1 "register_operand" "rO")))]
751 
  ""
752 
  "tblidxb2\t%0, %r1"
753 
  [(set_attr "type" "Y0")])
754 
 
755 
(define_insn "*insv_tblidxb3"
756 
  [(set (zero_extract:DI
757 
         (match_operand:DI 0 "register_operand" "+r")
758 
         (const_int 8)
759 
         (const_int 2))
760 
        (zero_extract:DI
761 
         (const_int 8)
762 
         (const_int 24)
763 
        (match_operand:DI 1 "register_operand" "rO")))]
764 
  ""
765 
  "tblidxb3\t%0, %r1"
766 
  [(set_attr "type" "Y0")])
767 
 
768 
(define_insn "*insv_bfins"
769 
  [(set (zero_extract:DI
770 
         (match_operand:DI 0 "register_operand" "+r")
771 
         (match_operand:DI 1 "u6bit_cint_operand" "n")
772 
         (match_operand:DI 2 "u6bit_cint_operand" "n"))
773 
        (match_operand:DI 3 "reg_or_cint_operand" "rO"))]
774 
  ""
775 
  "bfins\t%0, %r3, %2, %2+%1-1"
776 
  [(set_attr "type" "X0")])
777 
 
778 
(define_insn "*insv_mm"
779 
  [(set (zero_extract:DI
780 
         (match_operand:DI 0 "register_operand" "+r")
781 
         (match_operand:DI 1 "u6bit_cint_operand" "n")
782 
         (match_operand:DI 2 "u6bit_cint_operand" "n"))
783 
        (zero_extract:DI
784 
         (match_operand:DI 3 "register_operand" "rO")
785 
         (match_dup 1)
786 
         (match_dup 2)))]
787 
  ""
788 
{
789 
  int n;
790 
 
791 
  operands[1] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[2]));
792 
 
793 
  n = INTVAL (operands[2]);
794 
  n = (n == 0) ? 63 : n - 1;
795 
  operands[2] = GEN_INT (n);
796 
 
797 
  return "mm\t%0, %r3, %1, %2";
798 
}
799 
  [(set_attr "type" "X0")])
800 
 
801 
(define_expand "extv"
802 
  [(set (match_operand:DI 0 "register_operand" "")
803 
        (sign_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
804 
                         (match_operand:DI 2 "immediate_operand" "")
805 
                         (match_operand:DI 3 "immediate_operand" "")))]
806 
  ""
807 
{
808 
  if (MEM_P (operands[1]))
809 
    {
810 
      HOST_WIDE_INT bit_offset, bit_width;
811 
      HOST_WIDE_INT first_byte_offset, last_byte_offset;
812 
 
813 
      if (GET_MODE (operands[1]) != QImode)
814 
        FAIL;
815 
 
816 
      bit_width = INTVAL (operands[2]);
817 
      bit_offset = INTVAL (operands[3]);
818 
 
819 
      /* Reject bitfields that can be done with a normal load */
820 
      if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
821 
        FAIL;
822 
 
823 
      /* The value in memory cannot span more than 8 bytes. */
824 
      first_byte_offset = bit_offset / BITS_PER_UNIT;
825 
      last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
826 
      if (last_byte_offset - first_byte_offset > 7)
827 
        FAIL;
828 
 
829 
      tilegx_expand_unaligned_load (operands[0], operands[1],
830 
                                    bit_width, bit_offset, 1);
831 
 
832 
      DONE;
833 
    }
834 
 
835 
  operands[1] = force_reg (DImode, operands[1]);
836 
})
837 
 
838 
(define_expand "extzv"
839 
  [(set (match_operand:DI 0 "register_operand" "")
840 
        (zero_extract:DI (match_operand 1 "nonautoincmem_general_operand" "")
841 
                         (match_operand:DI 2 "immediate_operand" "")
842 
                         (match_operand:DI 3 "immediate_operand" "")))]
843 
  ""
844 
{
845 
  HOST_WIDE_INT bit_width = INTVAL (operands[2]);
846 
  HOST_WIDE_INT bit_offset = INTVAL (operands[3]);
847 
 
848 
 
849 
  if (MEM_P (operands[1]))
850 
    {
851 
      HOST_WIDE_INT first_byte_offset, last_byte_offset;
852 
 
853 
      if (GET_MODE (operands[1]) != QImode)
854 
        FAIL;
855 
 
856 
      /* Reject bitfields that can be done with a normal load */
857 
      if (MEM_ALIGN (operands[1]) >= bit_offset + bit_width)
858 
        FAIL;
859 
 
860 
      /* The value in memory cannot span more than 8 bytes. */
861 
      first_byte_offset = bit_offset / BITS_PER_UNIT;
862 
      last_byte_offset = (bit_offset + bit_width - 1) / BITS_PER_UNIT;
863 
      if (last_byte_offset - first_byte_offset > 7)
864 
        FAIL;
865 
 
866 
      tilegx_expand_unaligned_load (operands[0], operands[1],
867 
                                    bit_width, bit_offset, 0);
868 
 
869 
      DONE;
870 
    }
871 
 
872 
    operands[1] = force_reg (DImode, operands[1]);
873 
 
874 
    if (bit_offset == 0)
875 
      {
876 
         /* Extracting the low bits is just a bitwise AND. */
877 
         HOST_WIDE_INT mask = ((HOST_WIDE_INT)1 << bit_width) - 1;
878 
         emit_insn (gen_anddi3 (operands[0], operands[1], GEN_INT (mask)));
879 
         DONE;
880 
      }
881 
})
882 
 
883 
 
884 
;;
885 
;; Addresses
886 
;;
887 
 
888 
;; First step of the 3-insn sequence to materialize a symbolic
889 
;; address.
890 
(define_expand "mov_address_step1"
891 
  [(set (match_operand:DI 0 "register_operand" "")
892 
        (const:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
893 
                             UNSPEC_HW2_LAST)))])
894 
 
895 
;; Second step of the 3-insn sequence to materialize a symbolic
896 
;; address.
897 
(define_expand "mov_address_step2"
898 
  [(set (match_operand:DI 0 "register_operand" "")
899 
        (unspec:DI
900 
         [(match_operand:DI 1 "reg_or_0_operand" "")
901 
          (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
902 
                               UNSPEC_HW1))]
903 
         UNSPEC_INSN_ADDR_SHL16INSLI))])
904 
 
905 
;; Third step of the 3-insn sequence to materialize a symbolic
906 
;; address.
907 
(define_expand "mov_address_step3"
908 
  [(set (match_operand:DI 0 "register_operand" "")
909 
        (unspec:DI
910 
         [(match_operand:DI 1 "reg_or_0_operand" "")
911 
          (const:DI (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
912 
                               UNSPEC_HW0))]
913 
         UNSPEC_INSN_ADDR_SHL16INSLI))])
914 
 
915 
;; First step of the 2-insn sequence to materialize a 32-bit symbolic
916 
;; address.
917 
(define_expand "mov_address_32bit_step1"
918 
  [(set (match_operand:SI 0 "register_operand" "")
919 
        (const:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "")]
920 
                             UNSPEC_HW1_LAST)))])
921 
 
922 
;; Second step of the 2-insn sequence to materialize a 32-bit symbolic
923 
;; address.
924 
(define_expand "mov_address_32bit_step2"
925 
  [(set (match_operand:SI 0 "register_operand" "")
926 
        (unspec:SI
927 
         [(match_operand:SI 1 "reg_or_0_operand" "")
928 
          (const:SI (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")]
929 
                               UNSPEC_HW0))]
930 
         UNSPEC_INSN_ADDR_SHL16INSLI))])
931 
 
932 
 
933 
;;
934 
;; pic related instructions
935 
;;
936 
 
937 
;; NOTE: We compute the label in this unusual way because if we place
938 
;; the label after the lnk, whether it is at the same address as the
939 
;; lnk will vary depending on whether the optimization level chooses
940 
;; to insert bundling braces.
941 
(define_insn "insn_lnk_and_label"
942 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
943 
        (unspec_volatile:I48MODE
944 
         [(match_operand:I48MODE 1 "symbolic_operand" "")]
945 
         UNSPEC_LNK_AND_LABEL))]
946 
  ""
947 
  "%1 = . + 8\n\tlnk\t%0"
948 
  [(set_attr "type" "Y1")])
949 
 
950 
;; First step of the 3-insn sequence to materialize a position
951 
;; independent address by adding the difference of two labels to a
952 
;; base label in the text segment, assuming that the difference fits
953 
;; in 32 signed bits.
954 
(define_expand "mov_pcrel_step1"
955 
  [(set (match_operand:I48MODE 0 "register_operand" "")
956 
        (const:I48MODE (unspec:I48MODE
957 
                        [(match_operand:I48MODE 1 "symbolic_operand" "")
958 
                         (match_operand:I48MODE 2 "symbolic_operand" "")]
959 
                        UNSPEC_HW1_LAST_PCREL)))]
960 
  "flag_pic")
961 
 
962 
;; Second step of the 3-insn sequence to materialize a position
963 
;; independent address by adding the difference of two labels to a
964 
;; base label in the text segment, assuming that the difference fits
965 
;; in 32 signed bits.
966 
(define_expand "mov_pcrel_step2"
967 
  [(set (match_operand:I48MODE 0 "register_operand" "")
968 
        (unspec:I48MODE
969 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "")
970 
          (const:I48MODE
971 
           (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")
972 
                            (match_operand:I48MODE 3 "symbolic_operand" "")]
973 
                           UNSPEC_HW0_PCREL))]
974 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
975 
  "flag_pic")
976 
 
977 
;; Third step of the 3-insn sequence to materialize a position
978 
;; independent address by adding the difference of two labels to a base
979 
;; label in the text segment, assuming that the difference fits in 32
980 
;; signed bits.
981 
(define_insn "mov_pcrel_step3"
982 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
983 
        (unspec:I48MODE [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
984 
                         (match_operand:I48MODE 2 "reg_or_0_operand" "rO")
985 
                         (match_operand:I48MODE 3 "symbolic_operand" "in")
986 
                         (match_operand:I48MODE 4 "symbolic_operand" "in")]
987 
                        UNSPEC_MOV_PCREL_STEP3))]
988 
  "flag_pic"
989 
  "add\t%0, %r1, %r2")
990 
 
991 
(define_expand "add_got16"
992 
  [(set (match_operand:I48MODE 0 "register_operand" "")
993 
        (plus:I48MODE
994 
         (match_operand:I48MODE 1 "reg_or_0_operand" "")
995 
         (const:I48MODE
996 
          (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
997 
                          UNSPEC_HW0_LAST_GOT))))]
998 
  "flag_pic == 1")
999 
 
1000 
(define_expand "mov_got32_step1"
1001 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1002 
        (const:I48MODE
1003 
         (unspec:I48MODE [(match_operand:I48MODE 1 "symbolic_operand" "")]
1004 
                         UNSPEC_HW1_LAST_GOT)))]
1005 
  "flag_pic == 2")
1006 
 
1007 
(define_expand "mov_got32_step2"
1008 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1009 
        (unspec:I48MODE
1010 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1011 
          (const:I48MODE
1012 
           (unspec:I48MODE [(match_operand:I48MODE 2 "symbolic_operand" "")]
1013 
                           UNSPEC_HW0_GOT))]
1014 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
1015 
  "flag_pic == 2")
1016 
 
1017 
 
1018 
;;
1019 
;; TLS
1020 
;;
1021 
 
1022 
(define_expand "mov_tls_gd_step1"
1023 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1024 
        (const:I48MODE
1025 
         (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1026 
                         UNSPEC_HW1_LAST_TLS_GD)))]
1027 
  "HAVE_AS_TLS")
1028 
 
1029 
(define_expand "mov_tls_gd_step2"
1030 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1031 
        (unspec:I48MODE
1032 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1033 
          (const:I48MODE
1034 
           (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1035 
                           UNSPEC_HW0_TLS_GD))]
1036 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
1037 
  "HAVE_AS_TLS")
1038 
 
1039 
(define_expand "mov_tls_ie_step1"
1040 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1041 
        (const:I48MODE
1042 
         (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1043 
                         UNSPEC_HW1_LAST_TLS_IE)))]
1044 
  "HAVE_AS_TLS")
1045 
 
1046 
(define_expand "mov_tls_ie_step2"
1047 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1048 
        (unspec:I48MODE
1049 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1050 
          (const:I48MODE
1051 
           (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1052 
                           UNSPEC_HW0_TLS_IE))]
1053 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
1054 
  "HAVE_AS_TLS")
1055 
 
1056 
(define_expand "mov_tls_le_step1"
1057 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1058 
        (const:I48MODE
1059 
         (unspec:I48MODE [(match_operand:I48MODE 1 "tls_symbolic_operand" "")]
1060 
                         UNSPEC_HW1_LAST_TLS_LE)))]
1061 
  "HAVE_AS_TLS")
1062 
 
1063 
(define_expand "mov_tls_le_step2"
1064 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1065 
        (unspec:I48MODE
1066 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "")
1067 
          (const:I48MODE
1068 
           (unspec:I48MODE [(match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1069 
                           UNSPEC_HW0_TLS_LE))]
1070 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
1071 
  "HAVE_AS_TLS")
1072 
 
1073 
(define_expand "tls_gd_call"
1074 
  [(parallel
1075 
    [(set (reg:I48MODE 0)
1076 
          (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1077 
                           (reg:I48MODE 0)]
1078 
                           UNSPEC_TLS_GD_CALL))
1079 
     (clobber (reg:I48MODE 25))
1080 
     (clobber (reg:I48MODE 26))
1081 
     (clobber (reg:I48MODE 27))
1082 
     (clobber (reg:I48MODE 28))
1083 
     (clobber (reg:I48MODE 29))
1084 
     (clobber (reg:I48MODE 55))])]
1085 
   ""
1086 
{
1087 
  cfun->machine->calls_tls_get_addr = true;
1088 
})
1089 
 
1090 
(define_insn "*tls_gd_call"
1091 
  [(set (reg:I48MODE 0)
1092 
        (unspec:I48MODE [(match_operand:I48MODE 0 "tls_symbolic_operand" "")
1093 
                         (reg:I48MODE 0)]
1094 
                        UNSPEC_TLS_GD_CALL))
1095 
   (clobber (reg:I48MODE 25))
1096 
   (clobber (reg:I48MODE 26))
1097 
   (clobber (reg:I48MODE 27))
1098 
   (clobber (reg:I48MODE 28))
1099 
   (clobber (reg:I48MODE 29))
1100 
   (clobber (reg:I48MODE 55))]
1101 
  ""
1102 
  "jal\ttls_gd_call(%0)"
1103 
  [(set_attr "type" "X1")])
1104 
 
1105 
(define_insn "tls_gd_add"
1106 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1107 
        (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1108 
                         (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1109 
                        UNSPEC_TLS_GD_ADD))]
1110 
  "HAVE_AS_TLS"
1111 
  "addi\t%0, %1, tls_gd_add(%2)")
1112 
 
1113 
(define_insn "tls_add"
1114 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1115 
        (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1116 
                         (match_operand:I48MODE 2 "register_operand" "0")
1117 
                         (match_operand:I48MODE 3 "tls_symbolic_operand" "")]
1118 
                        UNSPEC_TLS_ADD))]
1119 
  "HAVE_AS_TLS"
1120 
  "addi\t%0, %1, tls_add(%3)")
1121 
 
1122 
(define_insn "tls_ie_load"
1123 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1124 
        (unspec:I48MODE [(match_operand:I48MODE 1 "register_operand" "r")
1125 
                         (match_operand:I48MODE 2 "tls_symbolic_operand" "")]
1126 
                        UNSPEC_TLS_IE_LOAD))]
1127 
  "HAVE_AS_TLS"
1128 
  "ld_tls\t%0, %1, tls_ie_load(%2)"
1129 
  [(set_attr "type" "X1_2cycle")])
1130 
 
1131 
(define_insn "*zero_extract"
1132 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1133 
        (zero_extract:I48MODE
1134 
         (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1135 
         (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1136 
         (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1137 
  ""
1138 
  "bfextu\t%0, %r1, %3, %3+%2-1"
1139 
  [(set_attr "type" "X0")])
1140 
 
1141 
(define_insn "*sign_extract_low32"
1142 
  [(set (match_operand:DI 0 "register_operand" "=r")
1143 
        (sign_extract:DI
1144 
         (match_operand:DI 1 "reg_or_0_operand" "r")
1145 
         (match_operand:DI 2 "u6bit_cint_operand" "n")
1146 
         (match_operand:DI 3 "u6bit_cint_operand" "n")))]
1147 
  "INTVAL (operands[3]) == 0 && INTVAL (operands[2]) == 32"
1148 
  "addxi\t%0, %r1, 0")
1149 
 
1150 
(define_insn "*sign_extract"
1151 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1152 
        (sign_extract:I48MODE
1153 
         (match_operand:I48MODE 1 "reg_or_0_operand" "r")
1154 
         (match_operand:I48MODE 2 "u6bit_cint_operand" "n")
1155 
         (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))]
1156 
  ""
1157 
  "bfexts\t%0, %r1, %3, %3+%2-1"
1158 
  [(set_attr "type" "X0")])
1159 
 
1160 
 
1161 
;;
1162 
;; Arithmetic ops
1163 
;;
1164 
 
1165 
(define_insn "add3"
1166 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1167 
        (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO,rO")
1168 
                      (match_operand:I48MODE 2 "add_operand" "r,I,JT")))]
1169 
  ""
1170 
  "@
1171 
   add\t%0, %r1, %r2
1172 
   addi\t%0, %r1, %2
1173 
   addli\t%0, %r1, %H2"
1174 
  [(set_attr "type" "*,*,X01")])
1175 
 
1176 
(define_insn "*addsi3_sext"
1177 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1178 
        (sign_extend:DI
1179 
         (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,rO")
1180 
                  (match_operand:SI 2 "add_operand" "r,I,JT"))))]
1181 
  ""
1182 
  "@
1183 
   addx\t%0, %r1, %r2
1184 
   addxi\t%0, %r1, %2
1185 
   addxli\t%0, %r1, %H2"
1186 
  [(set_attr "type" "*,*,X01")])
1187 
 
1188 
(define_insn "sub3"
1189 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1190 
        (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1191 
                       (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
1192 
  ""
1193 
  "sub\t%0, %r1, %r2")
1194 
 
1195 
(define_insn "*subsi3_sext"
1196 
  [(set (match_operand:DI 0 "register_operand" "=r")
1197 
        (sign_extend:DI
1198 
         (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1199 
                   (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1200 
  ""
1201 
  "subx\t%0, %r1, %r2")
1202 
 
1203 
(define_insn "neg2"
1204 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1205 
        (neg:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO")))]
1206 
  ""
1207 
  "sub\t%0, zero, %r1")
1208 
 
1209 
(define_insn "*negsi2_sext"
1210 
  [(set (match_operand:DI 0 "register_operand" "=r")
1211 
        (sign_extend:DI
1212 
         (neg:SI (match_operand:SI 1 "reg_or_0_operand" "rO"))))]
1213 
  ""
1214 
  "subx\t%0, zero, %r1")
1215 
 
1216 
(define_insn "ssaddsi3"
1217 
  [(set (match_operand:SI 0 "register_operand" "=r")
1218 
        (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1219 
                    (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1220 
  ""
1221 
  "addxsc\t%0, %r1, %r2"
1222 
  [(set_attr "type" "X01")])
1223 
 
1224 
(define_insn "*ssaddsi3_sext"
1225 
  [(set (match_operand:DI 0 "register_operand" "=r")
1226 
        (sign_extend:DI
1227 
         (ss_plus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1228 
                     (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1229 
  ""
1230 
  "addxsc\t%0, %r1, %r2"
1231 
  [(set_attr "type" "X01")])
1232 
 
1233 
(define_insn "sssubsi3"
1234 
  [(set (match_operand:SI 0 "register_operand" "=r")
1235 
        (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1236 
                     (match_operand:SI 2 "reg_or_0_operand" "rO")))]
1237 
  ""
1238 
  "subxsc\t%0, %r1, %r2"
1239 
  [(set_attr "type" "X01")])
1240 
 
1241 
(define_insn "*sssubsi3_sext"
1242 
  [(set (match_operand:DI 0 "register_operand" "=r")
1243 
        (sign_extend:DI
1244 
         (ss_minus:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
1245 
                      (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
1246 
  ""
1247 
  "subxsc\t%0, %r1, %r2"
1248 
  [(set_attr "type" "X01")])
1249 
 
1250 
(define_expand "addsf3"
1251 
  [(set (match_operand:SF 0 "register_operand" "")
1252 
        (plus:SF (match_operand:SF 1 "register_operand" "")
1253 
                 (match_operand:SF 2 "register_operand" "")))]
1254 
  ""
1255 
{
1256 
  rtx result = gen_lowpart (DImode, operands[0]);
1257 
  rtx a = gen_lowpart (DImode, operands[1]);
1258 
  rtx b = gen_lowpart (DImode, operands[2]);
1259 
 
1260 
  rtx tmp = gen_reg_rtx (DImode);
1261 
  rtx flags = gen_reg_rtx (DImode);
1262 
 
1263 
  emit_insn (gen_insn_fsingle_add1 (tmp, a, b));
1264 
  emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1265 
  emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1266 
  emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1267 
 
1268 
  DONE;
1269 
})
1270 
 
1271 
(define_expand "subsf3"
1272 
  [(set (match_operand:SF 0 "register_operand" "")
1273 
        (minus:SF (match_operand:SF 1 "register_operand" "")
1274 
                  (match_operand:SF 2 "register_operand" "")))]
1275 
  ""
1276 
{
1277 
  rtx result = gen_lowpart (DImode, operands[0]);
1278 
  rtx a = gen_lowpart (DImode, operands[1]);
1279 
  rtx b = gen_lowpart (DImode, operands[2]);
1280 
 
1281 
  rtx tmp = gen_reg_rtx (DImode);
1282 
  rtx flags = gen_reg_rtx (DImode);
1283 
 
1284 
  emit_insn (gen_insn_fsingle_sub1 (tmp, a, b));
1285 
  emit_insn (gen_insn_fsingle_addsub2 (tmp, tmp, a, b));
1286 
  emit_insn (gen_insn_fsingle_pack1 (flags, tmp));
1287 
  emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags));
1288 
 
1289 
  DONE;
1290 
})
1291 
 
1292 
(define_expand "mulsf3"
1293 
  [(set (match_operand:SF 0 "register_operand" "")
1294 
        (mult:SF (match_operand:SF 1 "register_operand" "")
1295 
                 (match_operand:SF 2 "register_operand" "")))]
1296 
  ""
1297 
{
1298 
  rtx result = gen_lowpart (DImode, operands[0]);
1299 
  rtx a = gen_lowpart (DImode, operands[1]);
1300 
  rtx b = gen_lowpart (DImode, operands[2]);
1301 
 
1302 
  rtx tmp1 = gen_reg_rtx (DImode);
1303 
  rtx tmp2 = gen_reg_rtx (DImode);
1304 
  rtx flags = gen_reg_rtx (DImode);
1305 
 
1306 
  emit_insn (gen_insn_fsingle_mul1 (tmp1, a, b));
1307 
  emit_insn (gen_insn_fsingle_mul2 (tmp2, tmp1, b));
1308 
  emit_insn (gen_insn_fsingle_pack1 (flags, tmp2));
1309 
  emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags));
1310 
 
1311 
  DONE;
1312 
})
1313 
 
1314 
(define_expand "adddf3"
1315 
  [(set (match_operand:DF 0 "register_operand" "")
1316 
        (plus:DF (match_operand:DF 1 "register_operand" "")
1317 
                 (match_operand:DF 2 "register_operand" "")))]
1318 
  ""
1319 
{
1320 
  rtx result = gen_lowpart (DImode, operands[0]);
1321 
  rtx a = gen_lowpart (DImode, operands[1]);
1322 
  rtx b = gen_lowpart (DImode, operands[2]);
1323 
 
1324 
  rtx min = gen_reg_rtx (DImode);
1325 
  rtx max = gen_reg_rtx (DImode);
1326 
  rtx flags = gen_reg_rtx (DImode);
1327 
 
1328 
  emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1329 
  emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1330 
  emit_insn (gen_insn_fdouble_add_flags (flags, a, b));
1331 
  emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1332 
  emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1333 
  emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1334 
 
1335 
  DONE;
1336 
})
1337 
 
1338 
 
1339 
(define_expand "subdf3"
1340 
  [(set (match_operand:DF 0 "register_operand" "")
1341 
        (minus:DF (match_operand:DF 1 "register_operand" "")
1342 
                  (match_operand:DF 2 "register_operand" "")))]
1343 
  ""
1344 
{
1345 
  rtx result = gen_lowpart (DImode, operands[0]);
1346 
  rtx a = gen_lowpart (DImode, operands[1]);
1347 
  rtx b = gen_lowpart (DImode, operands[2]);
1348 
 
1349 
  rtx min = gen_reg_rtx (DImode);
1350 
  rtx max = gen_reg_rtx (DImode);
1351 
  rtx flags = gen_reg_rtx (DImode);
1352 
 
1353 
  emit_insn (gen_insn_fdouble_unpack_min (min, a, b));
1354 
  emit_insn (gen_insn_fdouble_unpack_max (max, a, b));
1355 
  emit_insn (gen_insn_fdouble_sub_flags (flags, a, b));
1356 
  emit_insn (gen_insn_fdouble_addsub (max, max, min, flags));
1357 
  emit_insn (gen_insn_fdouble_pack1 (result, max, flags));
1358 
  emit_insn (gen_insn_fdouble_pack2 (result, result, max, const0_rtx));
1359 
 
1360 
  DONE;
1361 
})
1362 
 
1363 
(define_expand "muldf3"
1364 
  [(set (match_operand:DF 0 "register_operand" "")
1365 
        (mult:DF (match_operand:DF 1 "register_operand" "")
1366 
                 (match_operand:DF 2 "register_operand" "")))]
1367 
  ""
1368 
  ;; TODO: Decide if we should not inline this with -Os.
1369 
  ;; "optimize_function_for_speed_p (cfun)"
1370 
{
1371 
  rtx result = gen_lowpart (DImode, operands[0]);
1372 
  rtx a = gen_lowpart (DImode, operands[1]);
1373 
  rtx b = gen_lowpart (DImode, operands[2]);
1374 
 
1375 
  rtx a_unpacked = gen_reg_rtx (DImode);
1376 
  rtx b_unpacked = gen_reg_rtx (DImode);
1377 
  rtx flags = gen_reg_rtx (DImode);
1378 
 
1379 
  rtx low1 = gen_reg_rtx (DImode);
1380 
  rtx low = gen_reg_rtx (DImode);
1381 
  rtx low_carry = gen_reg_rtx (DImode);
1382 
 
1383 
  rtx mid = gen_reg_rtx (DImode);
1384 
  rtx mid_l32 = gen_reg_rtx (DImode);
1385 
  rtx mid_r32 = gen_reg_rtx (DImode);
1386 
 
1387 
  rtx high1 = gen_reg_rtx (DImode);
1388 
  rtx high = gen_reg_rtx (DImode);
1389 
  rtx high1_plus_mid_r32 = gen_reg_rtx (DImode);
1390 
 
1391 
  /* NOTE: We compute using max(a, 0) and max(b, 0) rather than
1392 
     min(a, b) and max(a, b) because for multiply we just need to unpack,
1393 
     we don't actually care which is min and which is max. And this
1394 
     formulation gives the scheduler more freedom in case one of a or b
1395 
     would stall at the start of this code sequence. */
1396 
  emit_insn (gen_insn_fdouble_unpack_max (a_unpacked, a, const0_rtx));
1397 
  emit_insn (gen_insn_fdouble_unpack_max (b_unpacked, b, const0_rtx));
1398 
  emit_insn (gen_insn_fdouble_mul_flags (flags, a, b));
1399 
 
1400 
  /* This depends on the fact that the high few bits of the unpacked
1401 
     mantissa are zero, so we can't have a carry out from the mid sum. */
1402 
  emit_insn (gen_insn_mul_lu_lu (low1, a_unpacked, b_unpacked));
1403 
  emit_insn (gen_insn_mul_hu_lu (mid, a_unpacked, b_unpacked));
1404 
  emit_insn (gen_insn_mula_hu_lu (mid, mid, b_unpacked, a_unpacked));
1405 
  emit_insn (gen_insn_mul_hu_hu (high1, a_unpacked, b_unpacked));
1406 
 
1407 
  emit_insn (gen_ashldi3 (mid_l32, mid, GEN_INT (32)));
1408 
  emit_insn (gen_lshrdi3 (mid_r32, mid, GEN_INT (32)));
1409 
 
1410 
  emit_insn (gen_adddi3 (high1_plus_mid_r32, high1, mid_r32));
1411 
 
1412 
  emit_insn (gen_adddi3 (low, low1, mid_l32));
1413 
  emit_insn (gen_insn_cmpltu_didi (low_carry, low, mid_l32));
1414 
 
1415 
  emit_insn (gen_adddi3 (high, high1_plus_mid_r32, low_carry));
1416 
 
1417 
  emit_insn (gen_insn_fdouble_pack1 (result, high, flags));
1418 
  emit_insn (gen_insn_fdouble_pack2 (result, result, high, low));
1419 
 
1420 
  DONE;
1421 
})
1422 
 
1423 
 
1424 
;;
1425 
;; Shifts
1426 
;;
1427 
 
1428 
(define_insn "ashl3"
1429 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1430 
        (ashift:I48MODE
1431 
         (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1432 
         (match_operand:SI 2 "reg_or_ubit_operand" "I,rO")))]
1433 
  ""
1434 
  "@
1435 
  shli\t%0, %r1, %2
1436 
  shl\t%0, %r1, %r2"
1437 
  [(set_attr "type" ",")])
1438 
 
1439 
(define_insn "*ashlsi3_sext"
1440 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1441 
        (sign_extend:DI
1442 
         (ashift:SI
1443 
          (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1444 
          (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1445 
  ""
1446 
  "@
1447 
  shlxi\t%0, %r1, %2
1448 
  shlx\t%0, %r1, %r2"
1449 
  [(set_attr "type" "X01,X01")])
1450 
 
1451 
(define_insn "ashr3"
1452 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1453 
        (ashiftrt:I48MODE
1454 
         (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1455 
         (match_operand:SI 2 "reg_or_ubit_operand" "I,rO")))]
1456 
  ""
1457 
  "@
1458 
  shrsi\t%0, %r1, %2
1459 
  shrs\t%0, %r1, %r2")
1460 
 
1461 
(define_insn "*ashrsi3_sext"
1462 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1463 
        (sign_extend:DI
1464 
         (ashiftrt:SI (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1465 
                      (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1466 
  ""
1467 
  "@
1468 
  shrsi\t%0, %r1, %2
1469 
  shrs\t%0, %r1, %r2")
1470 
 
1471 
(define_insn "lshr3"
1472 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r")
1473 
        (lshiftrt:I48MODE
1474 
         (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1475 
         (match_operand:SI 2 "reg_or_ubit_operand" "I,rO")))]
1476 
  ""
1477 
  "@
1478 
  shrui\t%0, %r1, %2
1479 
  shru\t%0, %r1, %r2"
1480 
  [(set_attr "type" ",")])
1481 
 
1482 
(define_insn "*lshrsi3_sext"
1483 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1484 
        (sign_extend:DI
1485 
         (lshiftrt:SI
1486 
          (match_operand:SI 1 "reg_or_0_operand" "rO,rO")
1487 
          (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO"))))]
1488 
  ""
1489 
  "@
1490 
  shruxi\t%0, %r1, %2
1491 
  shrux\t%0, %r1, %r2"
1492 
  [(set_attr "type" "X01,X01")])
1493 
 
1494 
(define_insn "rotldi3"
1495 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1496 
        (rotate:DI (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1497 
                   (match_operand:SI 2 "reg_or_u6bit_operand" "I,rO")))]
1498 
  ""
1499 
  "@
1500 
  rotli\t%0, %r1, %2
1501 
  rotl\t%0, %r1, %r2")
1502 
 
1503 
(define_insn "insn_shl16insli"
1504 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1505 
        (ior:DI
1506 
         (ashift:DI
1507 
          (match_operand:DI 1 "reg_or_0_operand" "rO,rO")
1508 
          (const_int 16))
1509 
         (match_operand:DI 2 "u16bit_or_const_symbolic_operand" "O,KT")))]
1510 
  ""
1511 
  "@
1512 
   shli\t%0, %r1, 16
1513 
   shl16insli\t%0, %r1, %H2"
1514 
  [(set_attr "type" "*,X01")])
1515 
 
1516 
(define_insn "insn_addr_shl16insli"
1517 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1518 
        (unspec:I48MODE
1519 
         [(match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1520 
          (match_operand:I48MODE 2 "const_symbolic_operand" "T")]
1521 
         UNSPEC_INSN_ADDR_SHL16INSLI))]
1522 
  ""
1523 
  "shl16insli\t%0, %r1, %H2"
1524 
  [(set_attr "type" "X01")])
1525 
 
1526 
 
1527 
;;
1528 
;; Compares
1529 
;;
1530 
 
1531 
(define_expand "cstore4"
1532 
  [(set (match_operand:DI 0 "register_operand" "")
1533 
      (match_operator:DI 1 "ordered_comparison_operator"
1534 
         [(match_operand:FI48MODE 2 "reg_or_cint_operand" "")
1535 
          (match_operand:FI48MODE 3 "reg_or_cint_operand" "")]))]
1536 
  ""
1537 
{
1538 
  if (!tilegx_emit_setcc (operands, GET_MODE (operands[2])))
1539 
    FAIL;
1540 
  else
1541 
    DONE;
1542 
})
1543 
 
1544 
 
1545 
(define_insn "insn_cmpne_"
1546 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r")
1547 
        (ne:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
1548 
                     (match_operand:I48MODE 2 "reg_or_cint_operand" "rO")))]
1549 
  ""
1550 
  "cmpne\t%0, %r1, %r2")
1551 
 
1552 
(define_insn "insn_cmpeq_"
1553 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1554 
        (eq:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "%rO,rO")
1555 
                     (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1556 
  ""
1557 
  "@
1558 
   cmpeqi\t%0, %r1, %2
1559 
   cmpeq\t%0, %r1, %r2")
1560 
 
1561 
(define_insn "insn_cmplts_"
1562 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1563 
        (lt:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1564 
                     (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1565 
  ""
1566 
  "@
1567 
   cmpltsi\t%0, %r1, %2
1568 
   cmplts\t%0, %r1, %r2")
1569 
 
1570 
(define_insn "insn_cmpltu_"
1571 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1572 
        (ltu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1573 
                      (match_operand:I48MODE 2 "reg_or_cint_operand" "I,rO")))]
1574 
  ""
1575 
  "@
1576 
   cmpltui\t%0, %r1, %2
1577 
   cmpltu\t%0, %r1, %r2"
1578 
  [(set_attr "type" "X01,*")])
1579 
 
1580 
(define_insn "insn_cmples_"
1581 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1582 
        (le:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1583 
                     (match_operand:I48MODE 2 "reg_or_cint_operand" "L,rO")))]
1584 
  ""
1585 
  "@
1586 
   cmpltsi\t%0, %r1, %P2
1587 
   cmples\t%0, %r1, %r2")
1588 
 
1589 
(define_insn "insn_cmpleu_"
1590 
  [(set (match_operand:I48MODE2 0 "register_operand" "=r,r")
1591 
        (leu:I48MODE2 (match_operand:I48MODE 1 "reg_or_0_operand" "rO,rO")
1592 
                      (match_operand:I48MODE 2 "reg_or_cint_operand" "Q,rO")))]
1593 
  ""
1594 
  "@
1595 
   cmpltui\t%0, %r1, %P2
1596 
   cmpleu\t%0, %r1, %r2"
1597 
  [(set_attr "type" "X01,*")])
1598 
 
1599 
 
1600 
;;
1601 
;; Logical ops
1602 
;;
1603 
 
1604 
(define_insn "and3"
1605 
  [(set (match_operand:IVNMODE 0 "register_operand" "=r,r,r,r")
1606 
        (and:IVNMODE (match_operand:IVNMODE 1 "reg_or_0_operand" "%rO,rO,0,rO")
1607 
                     (match_operand:IVNMODE 2 "and_operand" "I,S,M,rO")))]
1608 
  ""
1609 
  "@
1610 
   andi\t%0, %r1, %2
1611 
   bfextu\t%0, %r1, %M2
1612 
   bfins\t%0, zero, %m2
1613 
   and\t%0, %r1, %r2"
1614 
  [(set_attr "type" "*,X0,X0,*")])
1615 
 
1616 
(define_insn "*andsi3_sext"
1617 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1618 
        (sign_extend:DI
1619 
         (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO,0,rO")
1620 
                 (match_operand:SI 2 "and_operand" "I,S,M,rO"))))]
1621 
  ""
1622 
  "@
1623 
   andi\t%0, %r1, %2
1624 
   bfextu\t%0, %r1, %M2
1625 
   bfins\t%0, zero, %m2
1626 
   and\t%0, %r1, %r2"
1627 
  [(set_attr "type" "*,X0,X0,*")])
1628 
 
1629 
(define_insn "anddi3"
1630 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
1631 
        (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO,rO,0,rO")
1632 
                    (match_operand:DI 2 "and_operand" "I,Z0,Z1,S,M,rO")))]
1633 
  ""
1634 
  "@
1635 
   andi\t%0, %r1, %2
1636 
   v4int_l\t%0, zero, %r1
1637 
   v4int_h\t%0, %r1, zero
1638 
   bfextu\t%0, %r1, %M2
1639 
   bfins\t%0, zero, %m2
1640 
   and\t%0, %r1, %r2"
1641 
  [(set_attr "type" "*,X01,X01,X0,X0,*")])
1642 
 
1643 
(define_insn "ior3"
1644 
  [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1645 
        (ior:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1646 
                    (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1647 
  ""
1648 
  "@
1649 
   or\t%0, %r1, %r2
1650 
   ori\t%0, %r1, %2"
1651 
  [(set_attr "type" "*,X01")])
1652 
 
1653 
(define_insn "*iorsi3_sext"
1654 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1655 
        (sign_extend:DI
1656 
         (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1657 
                 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1658 
  ""
1659 
  "@
1660 
   or\t%0, %r1, %r2
1661 
   ori\t%0, %r1, %2"
1662 
  [(set_attr "type" "*,X01")])
1663 
 
1664 
(define_insn "xor3"
1665 
  [(set (match_operand:IVMODE 0 "register_operand" "=r,r")
1666 
        (xor:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "%rO,rO")
1667 
                    (match_operand:IVMODE 2 "reg_or_s8bit_operand" "rO,I")))]
1668 
  ""
1669 
  "@
1670 
   xor\t%0, %r1, %r2
1671 
   xori\t%0, %r1, %2"
1672 
  [(set_attr "type" "*,X01")])
1673 
 
1674 
(define_insn "*xorsi3_sext"
1675 
  [(set (match_operand:DI 0 "register_operand" "=r,r")
1676 
        (sign_extend:DI
1677 
         (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rO,rO")
1678 
                 (match_operand:SI 2 "reg_or_s8bit_operand" "rO,I"))))]
1679 
  ""
1680 
  "@
1681 
   xor\t%0, %r1, %r2
1682 
   xori\t%0, %r1, %2"
1683 
  [(set_attr "type" "*,X01")])
1684 
 
1685 
(define_insn "clzdi2"
1686 
  [(set (match_operand:DI 0 "register_operand" "=r")
1687 
        (clz:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1688 
  ""
1689 
  "clz\t%0, %r1"
1690 
  [(set_attr "type" "Y0")])
1691 
 
1692 
(define_expand "clzsi2"
1693 
  [(set (match_dup 2)
1694 
        (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "")
1695 
                   (const_int 32)))
1696 
   (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0)
1697 
        (clz:DI (match_dup 2)))]
1698 
   ""
1699 
   {
1700 
     operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);
1701 
     operands[2] = gen_reg_rtx (DImode);
1702 
   })
1703 
 
1704 
(define_insn "ctz2"
1705 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1706 
        (ctz:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1707 
  ""
1708 
  "ctz\t%0, %r1"
1709 
  [(set_attr "type" "Y0")])
1710 
 
1711 
 
1712 
(define_insn "popcount2"
1713 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
1714 
        (popcount:I48MODE (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1715 
  ""
1716 
  "pcnt\t%0, %r1"
1717 
  [(set_attr "type" "Y0")])
1718 
 
1719 
(define_expand "parity2"
1720 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1721 
        (parity:I48MODE (match_operand:DI 1 "reg_or_0_operand" "")))]
1722 
  ""
1723 
  {
1724 
    rtx tmp = gen_reg_rtx (mode);
1725 
    emit_insn (gen_popcount2 (tmp, operands[1]));
1726 
    emit_insn (gen_and3 (operands[0], tmp, const1_rtx));
1727 
    DONE;
1728 
  })
1729 
 
1730 
(define_insn "bswapdi2"
1731 
  [(set (match_operand:DI 0 "register_operand" "=r")
1732 
        (bswap:DI (match_operand:DI 1 "reg_or_0_operand" "rO")))]
1733 
  ""
1734 
  "revbytes\t%0, %r1"
1735 
  [(set_attr "type" "Y0")])
1736 
 
1737 
(define_expand "bswapsi2"
1738 
  [(set (match_operand:SI 0 "register_operand" "")
1739 
        (bswap:SI (match_operand:SI 1 "reg_or_0_operand" "")))]
1740 
  ""
1741 
  {
1742 
    rtx tmp = gen_reg_rtx (DImode);
1743 
    emit_insn (gen_bswapdi2 (tmp, gen_lowpart (DImode, operands[1])));
1744 
    emit_insn (gen_ashrdi3 (gen_lowpart (DImode, operands[0]),
1745 
                            tmp, GEN_INT (32)));
1746 
    DONE;
1747 
  })
1748 
 
1749 
(define_insn "one_cmpl2"
1750 
  [(set (match_operand:IVMODE 0 "register_operand" "=r")
1751 
        (not:IVMODE (match_operand:IVMODE 1 "reg_or_0_operand" "rO")))]
1752 
  ""
1753 
  "nor\t%0, %r1, zero")
1754 
 
1755 
 
1756 
;;
1757 
;; Conditional moves
1758 
;;
1759 
 
1760 
(define_expand "movcc"
1761 
  [(set (match_operand:I48MODE 0 "register_operand" "")
1762 
        (if_then_else:I48MODE
1763 
         (match_operand 1 "comparison_operator" "")
1764 
         (match_operand:I48MODE 2 "reg_or_0_operand" "")
1765 
         (match_operand:I48MODE 3 "reg_or_0_operand" "")))]
1766 
  ""
1767 
  { operands[1] = tilegx_emit_conditional_move (operands[1]); })
1768 
 
1769 
(define_insn "movcc_insn_"
1770 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r,r")
1771 
        (if_then_else:I48MODE
1772 
         (match_operator 4 "eqne_operator"
1773 
          [(match_operand:I48MODE2 1 "reg_or_0_operand" "rO,rO,rO,rO")
1774 
           (const_int 0)])
1775 
         (match_operand:I48MODE 2 "reg_or_0_operand"    "rO,O,rO,0")
1776 
         (match_operand:I48MODE 3 "reg_or_0_operand"    "O,rO,0,rO")))]
1777 
  ""
1778 
  "@
1779 
   m%c4\t%0, %r1, %r2
1780 
   m%C4\t%0, %r1, %r3
1781 
   cmov%d4z\t%0, %r1, %r2
1782 
   cmov%D4z\t%0, %r1, %r3"
1783 
  [(set_attr "type" "*,*,Y0,Y0")])
1784 
 
1785 
(define_expand "insn_mz"
1786 
  [(set (match_operand:DI 0 "register_operand" "")
1787 
        (if_then_else:DI
1788 
         (eq (match_operand:DI 1 "reg_or_0_operand" "")
1789 
             (const_int 0))
1790 
         (match_operand:DI 2 "reg_or_0_operand" "")
1791 
         (const_int 0)))])
1792 
 
1793 
(define_expand "insn_mnz"
1794 
  [(set (match_operand:DI 0 "register_operand" "")
1795 
        (if_then_else:DI
1796 
         (ne (match_operand:DI 1 "reg_or_0_operand" "")
1797 
             (const_int 0))
1798 
         (match_operand:DI 2 "reg_or_0_operand" "")
1799 
         (const_int 0)))])
1800 
 
1801 
(define_expand "insn_cmoveqz"
1802 
  [(set (match_operand:DI 0 "register_operand" "")
1803 
        (if_then_else:DI
1804 
         (eq (match_operand:DI 2 "reg_or_0_operand" "")
1805 
             (const_int 0))
1806 
         (match_operand:DI 3 "reg_or_0_operand" "")
1807 
         (match_operand:DI 1 "reg_or_0_operand" "")))])
1808 
 
1809 
(define_expand "insn_cmovnez"
1810 
  [(set (match_operand:DI 0 "register_operand" "")
1811 
        (if_then_else:DI
1812 
         (ne (match_operand:DI 2 "reg_or_0_operand" "")
1813 
             (const_int 0))
1814 
         (match_operand:DI 3 "reg_or_0_operand" "")
1815 
         (match_operand:DI 1 "reg_or_0_operand" "")))])
1816 
 
1817 
 
1818 
;;
1819 
;; Conversions
1820 
;;
1821 
 
1822 
(define_insn "zero_extendqi2"
1823 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1824 
        (zero_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1825 
  ""
1826 
  "@
1827 
   bfextu\t%0, %r1, 0, 7
1828 
   ld1u\t%0, %1
1829 
   ld1u_add\t%0, %I1, %i1"
1830 
  [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1831 
 
1832 
(define_insn "zero_extendhi2"
1833 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1834 
        (zero_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1835 
  ""
1836 
  "@
1837 
   bfextu\t%0, %r1, 0, 15
1838 
   ld2u\t%0, %1
1839 
   ld2u_add\t%0, %I1, %i1"
1840 
  [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1841 
 
1842 
(define_insn "zero_extendsidi2"
1843 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1844 
        (zero_extend:DI (match_operand:SI 1 "move_operand" "rO,U,m")))]
1845 
  ""
1846 
  "@
1847 
   v4int_l\t%0, zero, %r1
1848 
   ld4u\t%0, %1
1849 
   ld4u_add\t%0, %I1, %i1"
1850 
  [(set_attr "type" "X01,Y2_2cycle,X1_2cycle")])
1851 
 
1852 
(define_insn "extendqi2"
1853 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1854 
        (sign_extend:I48MODE (match_operand:QI 1 "move_operand" "rO,U,m")))]
1855 
  ""
1856 
  "@
1857 
   bfexts\t%0, %r1, 0, 7
1858 
   ld1s\t%0, %1
1859 
   ld1s_add\t%0, %I1, %i1"
1860 
  [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1861 
 
1862 
(define_insn "extendhi2"
1863 
  [(set (match_operand:I48MODE 0 "register_operand" "=r,r,r")
1864 
        (sign_extend:I48MODE (match_operand:HI 1 "move_operand" "rO,U,m")))]
1865 
  ""
1866 
  "@
1867 
   bfexts\t%0, %r1, 0, 15
1868 
   ld2s\t%0, %1
1869 
   ld2s_add\t%0, %I1, %i1"
1870 
  [(set_attr "type" "X0,Y2_2cycle,X1_2cycle")])
1871 
 
1872 
;; All SImode integer registers should already be in sign-extended
1873 
;; form (see TRULY_NOOP_TRUNCATION and truncdisi2).  We can therefore
1874 
;; get rid of register->register instructions if we constrain the
1875 
;; source to be in the same register as the destination.
1876 
(define_insn_and_split "extendsidi2"
1877 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1878 
        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,U,m")))]
1879 
  ""
1880 
  "@
1881 
   #
1882 
   ld4s\t%0, %1
1883 
   ld4s_add\t%0, %I1, %i1"
1884 
  "&& reload_completed && register_operand (operands[1], VOIDmode)"
1885 
  [(const_int 0)]
1886 
{
1887 
  emit_note (NOTE_INSN_DELETED);
1888 
  DONE;
1889 
}
1890 
  [(set_attr "type" "*,Y2_2cycle,X1_2cycle")])
1891 
 
1892 
;; Integer truncation patterns.  Truncating SImode values to smaller
1893 
;; modes is a no-op, as it is for most other GCC ports.  Truncating
1894 
;; DImode values to SImode is not a no-op since we
1895 
;; need to make sure that the lower 32 bits are properly sign-extended
1896 
;; (see TRULY_NOOP_TRUNCATION).  Truncating DImode values into modes
1897 
;; smaller than SImode is equivalent to two separate truncations:
1898 
;;
1899 
;;                        A       B
1900 
;;    DI ---> HI  ==  DI ---> SI ---> HI
1901 
;;    DI ---> QI  ==  DI ---> SI ---> QI
1902 
;;
1903 
;; Step A needs a real instruction but step B does not.
1904 
 
1905 
(define_insn "truncdisi2"
1906 
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,U,m")
1907 
        (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
1908 
  ""
1909 
  "@
1910 
   addxi\t%0, %r1, 0
1911 
   st4\t%0, %r1
1912 
   st4_add\t%I0, %r1, %i0"
1913 
  [(set_attr "type" "Y01,Y2,X1")])
1914 
 
1915 
(define_insn "truncdihi2"
1916 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,U,m")
1917 
        (truncate:HI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
1918 
  ""
1919 
  "@
1920 
   addxi\t%0, %r1, 0
1921 
   st2\t%0, %r1
1922 
   st2_add\t%I0, %r1, %i0"
1923 
  [(set_attr "type" "Y01,Y2,X1")])
1924 
 
1925 
(define_insn "truncdiqi2"
1926 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,U,m")
1927 
        (truncate:QI (match_operand:DI 1 "reg_or_0_operand" "rO,rO,rO")))]
1928 
  ""
1929 
  "@
1930 
   addxi\t%0, %r1, 0
1931 
   st1\t%0, %r1
1932 
   st1_add\t%I0, %r1, %i0"
1933 
  [(set_attr "type" "Y01,Y2,X1")])
1934 
 
1935 
;; Combiner patterns to optimize away unnecessary truncates.
1936 
 
1937 
(define_insn "*zero_extendsidi_truncdisi"
1938 
  [(set (match_operand:DI 0 "register_operand" "=r")
1939 
        (zero_extend:DI
1940 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "0"))))]
1941 
  ""
1942 
  "v4int_l\t%0, zero, %r1"
1943 
  [(set_attr "type" "X01")])
1944 
 
1945 
(define_insn "*addsi_truncdisi"
1946 
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1947 
        (plus:SI
1948 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO"))
1949 
         (match_operand:SI 2 "add_operand" "r,I,JT")))]
1950 
  ""
1951 
  "@
1952 
   addx\t%0, %r1, %r2
1953 
   addxi\t%0, %r1, %2
1954 
   addxli\t%0, %r1, %H2"
1955 
  [(set_attr "type" "*,*,X01")])
1956 
 
1957 
(define_insn "*addsi_truncdisi2"
1958 
  [(set (match_operand:SI 0 "register_operand" "=r")
1959 
        (plus:SI
1960 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
1961 
         (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
1962 
  ""
1963 
  "addx\t%0, %r1, %r2")
1964 
 
1965 
(define_insn "*ashldi_truncdisi"
1966 
  [(set (match_operand:DI 0 "register_operand" "=r")
1967 
        (ashift:DI
1968 
         (match_operand:DI 1 "reg_or_0_operand" "rO")
1969 
         (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
1970 
  ""
1971 
  "shl\t%0, %r1, %r2")
1972 
 
1973 
(define_insn "*ashlsi_truncdisi"
1974 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
1975 
        (ashift:SI
1976 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
1977 
         (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
1978 
  ""
1979 
  "@
1980 
  shlxi\t%0, %r1, %2
1981 
  shlx\t%0, %r1, %r2"
1982 
  [(set_attr "type" "X01,X01")])
1983 
 
1984 
(define_insn "*ashlsi_truncdisi2"
1985 
  [(set (match_operand:SI 0 "register_operand" "=r")
1986 
        (ashift:SI
1987 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
1988 
         (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
1989 
  ""
1990 
  "shlx\t%0, %r1, %r2"
1991 
  [(set_attr "type" "X01")])
1992 
 
1993 
(define_insn "*ashrdi3_truncdisi"
1994 
  [(set (match_operand:DI 0 "register_operand" "=r")
1995 
        (ashiftrt:DI
1996 
         (match_operand:DI 1 "reg_or_0_operand" "rO")
1997 
         (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
1998 
  ""
1999 
  "shrs\t%0, %r1, %r2")
2000 
 
2001 
(define_insn "*lshrsi_truncdisi"
2002 
  [(set (match_operand:SI 0 "register_operand" "=r,r")
2003 
        (lshiftrt:SI
2004 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO,rO"))
2005 
         (match_operand:SI 2 "reg_or_u5bit_operand" "I,rO")))]
2006 
  ""
2007 
  "@
2008 
  shruxi\t%0, %r1, %2
2009 
  shrux\t%0, %r1, %r2"
2010 
  [(set_attr "type" "X01,X01")])
2011 
 
2012 
(define_insn "*lshrsi_truncdisi2"
2013 
  [(set (match_operand:SI 0 "register_operand" "=r")
2014 
        (lshiftrt:SI
2015 
         (truncate:SI (match_operand:DI 1 "reg_or_0_operand" "rO"))
2016 
         (truncate:SI (match_operand:DI 2 "reg_or_0_operand" "rO"))))]
2017 
  ""
2018 
  "shrux\t%0, %r1, %r2"
2019 
  [(set_attr "type" "X01")])
2020 
 
2021 
(define_insn "*lshrdi_truncdisi"
2022 
  [(set (match_operand:DI 0 "register_operand" "=r")
2023 
        (lshiftrt:DI
2024 
         (match_operand:DI 1 "reg_or_0_operand" "rO")
2025 
         (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2026 
  ""
2027 
  "shru\t%0, %r1, %r2")
2028 
 
2029 
(define_insn "*rotldi_truncdisi"
2030 
  [(set (match_operand:DI 0 "register_operand" "=r")
2031 
        (rotate:DI
2032 
         (match_operand:DI 1 "reg_or_0_operand" "rO")
2033 
         (truncate:SI (match_operand:DI 2 "reg_or_u6bit_operand" "rO"))))]
2034 
  ""
2035 
  "rotl\t%0, %r1, %r2")
2036 
 
2037 
 
2038 
;;
2039 
;; Multiplies
2040 
;;
2041 
 
2042 
(define_insn "mulsi3"
2043 
  [(set (match_operand:SI 0 "register_operand" "=r")
2044 
        (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rO")
2045 
                 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
2046 
  ""
2047 
  "mulx\t%0, %r1, %r2"
2048 
  [(set_attr "type" "Y0_2cycle")])
2049 
 
2050 
(define_insn "mulsidi3"
2051 
  [(set (match_operand:DI 0 "register_operand" "=r")
2052 
        (mult:DI (sign_extend:DI
2053 
                  (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2054 
                 (sign_extend:DI
2055 
                  (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2056 
  ""
2057 
  "mul_ls_ls\t%0, %r1, %r2"
2058 
  [(set_attr "type" "Y0_2cycle")])
2059 
 
2060 
(define_insn "umulsidi3"
2061 
  [(set (match_operand:DI 0 "register_operand" "=r")
2062 
        (mult:DI (zero_extend:DI
2063 
                  (match_operand:SI 1 "reg_or_0_operand" "%rO"))
2064 
                 (zero_extend:DI
2065 
                  (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2066 
  ""
2067 
  "mul_lu_lu\t%0, %r1, %r2"
2068 
  [(set_attr "type" "Y0_2cycle")])
2069 
 
2070 
(define_expand "muldi3"
2071 
  [(set (match_operand:DI 0 "register_operand" "")
2072 
        (unspec:DI [(match_operand:DI 1 "nonmemory_operand" "")
2073 
                    (match_operand:DI 2 "nonmemory_operand" "")]
2074 
                   UNSPEC_INSN_MUL_HU_LU))
2075 
   (set (match_dup 0)
2076 
        (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2077 
                   UNSPEC_INSN_MULA_HU_LU))
2078 
   (set (match_dup 0)
2079 
        (ashift:DI (match_dup 0) (const_int 32)))
2080 
   (set (match_dup 0)
2081 
        (unspec:DI [(match_dup 0) (match_dup 2) (match_dup 1)]
2082 
                   UNSPEC_INSN_MULA_LU_LU))]
2083 
  ""
2084 
  {
2085 
    operands[1] = force_reg (DImode, operands[1]);
2086 
    operands[1] = make_safe_from (operands[1], operands[0]);
2087 
 
2088 
    if (tilegx_expand_muldi (operands[0], operands[1], operands[2]))
2089 
      DONE;
2090 
    else
2091 
      {
2092 
        operands[2] = force_reg (DImode, operands[2]);
2093 
        operands[2] = make_safe_from (operands[2], operands[0]);
2094 
      }
2095 
  })
2096 
 
2097 
(define_insn "usmulsidi3"
2098 
  [(set (match_operand:DI 0 "register_operand" "=r")
2099 
        (mult:DI (zero_extend:DI
2100 
                  (match_operand:SI 1 "reg_or_0_operand" "rO"))
2101 
                 (sign_extend:DI
2102 
                  (match_operand:SI 2 "reg_or_0_operand" "rO"))))]
2103 
  ""
2104 
  "mul_ls_lu\t%0, %r2, %r1"
2105 
  [(set_attr "type" "X0_2cycle")])
2106 
 
2107 
(define_insn "maddsidi4"
2108 
  [(set (match_operand:DI 0 "register_operand" "=r")
2109 
        (plus:DI
2110 
         (mult:DI (sign_extend:DI
2111 
                   (match_operand:SI 1 "reg_or_0_operand" "rO"))
2112 
                  (sign_extend:DI
2113 
                   (match_operand:SI 2 "reg_or_0_operand" "rO")))
2114 
         (match_operand:DI 3 "register_operand" "0")))]
2115 
  ""
2116 
  "mula_ls_ls\t%0, %r1, %r2"
2117 
  [(set_attr "type" "Y0_2cycle")])
2118 
 
2119 
(define_insn "umaddsidi4"
2120 
  [(set (match_operand:DI 0 "register_operand" "=r")
2121 
        (plus:DI
2122 
         (mult:DI (zero_extend:DI
2123 
                   (match_operand:SI 1 "reg_or_0_operand" "rO"))
2124 
                  (zero_extend:DI
2125 
                   (match_operand:SI 2 "reg_or_0_operand" "rO")))
2126 
         (match_operand:DI 3 "register_operand" "0")))]
2127 
  ""
2128 
  "mula_lu_lu\t%0, %r1, %r2"
2129 
  [(set_attr "type" "Y0_2cycle")])
2130 
 
2131 
(define_expand "smulsi3_highpart"
2132 
  [(set (match_dup 3)
2133 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2134 
                 (sign_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2135 
   (set (match_dup 4)
2136 
        (ashiftrt:DI (match_dup 3) (const_int 32)))
2137 
   (set (match_operand:SI 0 "register_operand" "")
2138 
        (truncate:SI (match_dup 4)))]
2139 
  ""
2140 
  {
2141 
    operands[3] = gen_reg_rtx (DImode);
2142 
    operands[4] = gen_reg_rtx (DImode);
2143 
  })
2144 
 
2145 
(define_expand "umulsi3_highpart"
2146 
  [(set (match_dup 3)
2147 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))
2148 
                 (zero_extend:DI (match_operand:SI 2 "reg_or_0_operand" ""))))
2149 
   (set (match_dup 4)
2150 
        (lshiftrt:DI (match_dup 3) (const_int 32)))
2151 
   (set (match_operand:SI 0 "register_operand" "")
2152 
        (truncate:SI (match_dup 4)))]
2153 
  ""
2154 
  {
2155 
    operands[3] = gen_reg_rtx (DImode);
2156 
    operands[4] = gen_reg_rtx (DImode);
2157 
  })
2158 
 
2159 
(define_expand "smuldi3_highpart"
2160 
  [(set (match_operand:DI 0 "register_operand" "")
2161 
        (truncate:DI
2162 
         (ashiftrt:TI
2163 
          (mult:TI (sign_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2164 
                   (sign_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2165 
          (const_int 64))))]
2166 
  ""
2167 
  {
2168 
    tilegx_expand_smuldi3_highpart (operands[0], operands[1], operands[2]);
2169 
    DONE;
2170 
  })
2171 
 
2172 
(define_expand "umuldi3_highpart"
2173 
  [(set (match_operand:DI 0 "register_operand" "")
2174 
        (truncate:DI
2175 
         (lshiftrt:TI
2176 
          (mult:TI (zero_extend:TI (match_operand:DI 1 "reg_or_0_operand" ""))
2177 
                   (zero_extend:TI (match_operand:DI 2 "reg_or_0_operand" "")))
2178 
          (const_int 64))))]
2179 
  ""
2180 
{
2181 
  tilegx_expand_umuldi3_highpart (operands[0], operands[1], operands[2]);
2182 
  DONE;
2183 
})
2184 
 
2185 
 
2186 
;;
2187 
;; Divide stubs.  These exist to work around a bug in expmed.c, which
2188 
;; will not attempt to convert a divide by constant into a multiply
2189 
;; unless there is a pattern for a divide of the same mode.  The end
2190 
;; result is a 32-bit divide turns into 64-bit multiply.
2191 
;;
2192 
 
2193 
(define_expand "divsi3"
2194 
  [(set (match_operand:SI 0 "register_operand" "")
2195 
        (div:SI (match_operand:SI 1 "reg_or_0_operand" "")
2196 
                (match_operand:SI 2 "reg_or_0_operand" "")))]
2197 
  ""
2198 
{
2199 
  FAIL;
2200 
})
2201 
 
2202 
(define_expand "udivsi3"
2203 
  [(set (match_operand:SI 0 "register_operand" "")
2204 
        (udiv:SI (match_operand:SI 1 "reg_or_0_operand" "")
2205 
                 (match_operand:SI 2 "reg_or_0_operand" "")))]
2206 
  ""
2207 
{
2208 
  FAIL;
2209 
})
2210 
 
2211 
 
2212 
;;
2213 
;; Loops
2214 
;;
2215 
 
2216 
;; Define the subtract-one-and-jump insns so loop.c knows what to generate.
2217 
(define_expand "doloop_end"
2218 
  [(use (match_operand 0 "" ""))    ;; loop pseudo
2219 
   (use (match_operand 1 "" ""))    ;; iterations; zero if unknown
2220 
   (use (match_operand 2 "" ""))    ;; max iterations
2221 
   (use (match_operand 3 "" ""))    ;; loop level
2222 
   (use (match_operand 4 "" ""))]   ;; label
2223 
   ""
2224 
{
2225 
  if (optimize > 0 && flag_modulo_sched)
2226 
  {
2227 
     rtx s0;
2228 
     rtx bcomp;
2229 
     rtx loc_ref;
2230 
     enum machine_mode mode = GET_MODE (operands[0]);
2231 
 
2232 
     /* only do inner loop  */
2233 
     if (INTVAL (operands[3]) > 1)
2234 
       FAIL;
2235 
     /* only deal with loop counters in SImode or DImode  */
2236 
     if (mode != SImode && mode != DImode)
2237 
       FAIL;
2238 
 
2239 
     s0 = operands [0];
2240 
     emit_move_insn (s0, gen_rtx_PLUS (mode, s0, GEN_INT (-1)));
2241 
     bcomp = gen_rtx_NE(mode, s0, const0_rtx);
2242 
     loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
2243 
     emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2244 
                                  gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
2245 
                                                        loc_ref, pc_rtx)));
2246 
     DONE;
2247 
  }
2248 
  else
2249 
     FAIL;
2250 
 
2251 
})
2252 
 
2253 
;;
2254 
;; Prologue/epilogue
2255 
;;
2256 
(define_expand "prologue"
2257 
  [(const_int 0)]
2258 
  ""
2259 
{
2260 
  tilegx_expand_prologue ();
2261 
  DONE;
2262 
})
2263 
 
2264 
(define_expand "epilogue"
2265 
  [(const_int 0)]
2266 
  ""
2267 
{
2268 
  tilegx_expand_epilogue (false);
2269 
  DONE;
2270 
})
2271 
 
2272 
(define_expand "sibcall_epilogue"
2273 
  [(const_int 0)]
2274 
  ""
2275 
{
2276 
  tilegx_expand_epilogue (true);
2277 
  DONE;
2278 
})
2279 
 
2280 
;;
2281 
;; Stack manipulations
2282 
;;
2283 
 
2284 
;; An insn to allocate new stack space for dynamic use (e.g., alloca).
2285 
(define_expand "allocate_stack"
2286 
  [(set (match_operand 0 "register_operand" "")
2287 
        (minus (reg 54) (match_operand 1 "nonmemory_operand" "")))
2288 
   (set (reg 54)
2289 
        (minus (reg 54) (match_dup 1)))]
2290 
  ""
2291 
  "tilegx_allocate_stack (operands[0], operands[1]); DONE;")
2292 
 
2293 
;;
2294 
;; Branches
2295 
;;
2296 
 
2297 
(define_expand "call"
2298 
  [(parallel [(call (match_operand:DI 0 "call_operand" "")
2299 
                    (match_operand 1 "" ""))
2300 
              (use (reg:DI 54))
2301 
              (clobber (reg:DI 55))])]
2302 
  ""
2303 
  "")
2304 
 
2305 
(define_insn "*call_insn"
2306 
  [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2307 
         (match_operand 1 "" ""))
2308 
   (use (reg:DI 54))
2309 
   (clobber (reg:DI 55))]
2310 
  ""
2311 
  "@
2312 
   jalr\t%r0
2313 
   jal\t%p0"
2314 
  [(set_attr "type" "Y1,X1")])
2315 
 
2316 
(define_expand "call_value"
2317 
  [(parallel [(set (match_operand 0 "register_operand" "")
2318 
                   (call (match_operand:DI 1 "call_operand" "")
2319 
                         (match_operand 2 "" "")))
2320 
              (use (reg:DI 54))
2321 
              (clobber (reg:DI 55))])]
2322 
  "")
2323 
 
2324 
(define_insn "*call_value_insn"
2325 
  [(set (match_operand 0 "register_operand" "=r,r")
2326 
        (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2327 
              (match_operand 2 "" "")))
2328 
   (use (reg:DI 54))
2329 
   (clobber (reg:DI 55))]
2330 
  ""
2331 
  "@
2332 
   jalr\t%r1
2333 
   jal\t%p1"
2334 
  [(set_attr "type" "Y1,X1")])
2335 
 
2336 
(define_expand "sibcall"
2337 
  [(parallel [(call (match_operand:DI 0 "call_operand" "")
2338 
                    (match_operand 1 "" ""))
2339 
              (use (reg:DI 54))])]
2340 
  ""
2341 
  "")
2342 
 
2343 
(define_insn "*sibcall_insn"
2344 
  [(call (mem:DI (match_operand:I48MODE 0 "call_address_operand" "rO,i"))
2345 
         (match_operand 1 "" ""))
2346 
   (use (reg:DI 54))]
2347 
  "SIBLING_CALL_P(insn)"
2348 
  "@
2349 
   jr\t%r0
2350 
   j\t%p0"
2351 
  [(set_attr "type" "X1,X1")])
2352 
 
2353 
(define_expand "sibcall_value"
2354 
  [(parallel [(set (match_operand 0 "" "")
2355 
                   (call (match_operand:DI 1 "call_operand" "")
2356 
                         (match_operand 2 "" "")))
2357 
              (use (reg:DI 54))])]
2358 
  ""
2359 
  "")
2360 
 
2361 
(define_insn "*sibcall_value"
2362 
  [(set (match_operand 0 "" "")
2363 
        (call (mem:DI (match_operand:I48MODE 1 "call_address_operand" "rO,i"))
2364 
              (match_operand 2 "" "")))
2365 
   (use (reg:DI 54))]
2366 
  "SIBLING_CALL_P(insn)"
2367 
  "@
2368 
   jr\t%r1
2369 
   j\t%p1"
2370 
  [(set_attr "type" "X1,X1")])
2371 
 
2372 
(define_insn "jump"
2373 
  [(set (pc) (label_ref (match_operand 0 "" "")))]
2374 
  ""
2375 
  "j\t%l0"
2376 
  [(set_attr "type" "X1")])
2377 
 
2378 
(define_insn "indirect_jump"
2379 
  [(set (pc) (match_operand 0 "pointer_operand" "rO"))]
2380 
  ""
2381 
  "jr\t%r0"
2382 
  [(set_attr "type" "Y1")])
2383 
 
2384 
(define_expand "return"
2385 
  [(parallel
2386 
    [(return)
2387 
     (use (reg:DI 55))])]
2388 
  "tilegx_can_use_return_insn_p ()"
2389 
  "")
2390 
 
2391 
(define_insn "_return"
2392 
  [(return)
2393 
   (use (reg:DI 55))]
2394 
  "reload_completed"
2395 
  "jrp\tlr"
2396 
  [(set_attr "type" "Y1")])
2397 
 
2398 
(define_expand "tablejump"
2399 
  [(set (pc) (match_operand 0 "pointer_operand" ""))
2400 
   (use (label_ref (match_operand 1 "" "")))]
2401 
  ""
2402 
{
2403 
  tilegx_expand_tablejump (operands[0], operands[1]);
2404 
  DONE;
2405 
})
2406 
 
2407 
(define_insn "tablejump_aux"
2408 
  [(set (pc) (match_operand 0 "pointer_operand" "rO"))
2409 
   (use (label_ref (match_operand 1 "" "")))]
2410 
  ""
2411 
  "jr\t%r0"
2412 
  [(set_attr "type" "Y1")])
2413 
 
2414 
;; Call subroutine returning any type.
2415 
(define_expand "untyped_call"
2416 
  [(parallel [(call (match_operand 0 "" "")
2417 
                    (const_int 0))
2418 
              (match_operand 1 "" "")
2419 
              (match_operand 2 "" "")])]
2420 
  ""
2421 
{
2422 
  int i;
2423 
 
2424 
  emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2425 
 
2426 
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
2427 
    {
2428 
      rtx set = XVECEXP (operands[2], 0, i);
2429 
      emit_move_insn (SET_DEST (set), SET_SRC (set));
2430 
    }
2431 
 
2432 
  /* The optimizer does not know that the call sets the function value
2433 
     registers we stored in the result block.  We avoid problems by
2434 
     claiming that all hard registers are used and clobbered at this
2435 
     point.  */
2436 
  emit_insn (gen_blockage ());
2437 
 
2438 
  DONE;
2439 
})
2440 
 
2441 
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers
2442 
;; and all of memory.  This blocks insns from being moved across this
2443 
;; point.
2444 
(define_insn "blockage"
2445 
  [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
2446 
  ""
2447 
  "pseudo"
2448 
  [(set_attr "type" "nothing")
2449 
   (set_attr "length" "0")])
2450 
 
2451 
;; Internal expanders to prevent memory ops from moving around frame
2452 
;; allocation/deallocation.
2453 
;;
2454 
;; TODO: really this clobber should just clobber the frame memory.  Is
2455 
;; this possibly by clobbering memory @ the sp reg (as alpha does?)
2456 
;; or by explicitly setting the alias set to the frame?
2457 
(define_insn "sp_adjust"
2458 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
2459 
        (plus:DI
2460 
         (match_operand:DI 1 "register_operand" "%r,r,r")
2461 
         (match_operand:DI 2 "add_operand" "r,I,JT")))
2462 
   (clobber (mem:BLK (scratch)))]
2463 
 ""
2464 
 "@
2465 
  add\t%0, %1, %2
2466 
  addi\t%0, %1, %2
2467 
  addli\t%0, %1, %H2"
2468 
 [(set_attr "type" "*,*,X01")])
2469 
 
2470 
(define_insn "sp_adjust_32bit"
2471 
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2472 
        (plus:SI
2473 
         (match_operand:SI 1 "register_operand" "%r,r,r")
2474 
         (match_operand:SI 2 "add_operand" "r,I,JT")))
2475 
   (clobber (mem:BLK (scratch)))]
2476 
 ""
2477 
 "@
2478 
  addx\t%0, %1, %2
2479 
  addxi\t%0, %1, %2
2480 
  addxli\t%0, %1, %H2"
2481 
 [(set_attr "type" "*,*,X01")])
2482 
 
2483 
;; Used for move sp, r52, to pop a stack frame.  We need to make sure
2484 
;; that stack frame memory operations have been issued before we do this.
2485 
;; TODO: see above TODO.
2486 
(define_insn "sp_restore"
2487 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2488 
        (match_operand:I48MODE 1 "register_operand" "r"))
2489 
   (clobber (mem:BLK (scratch)))]
2490 
 ""
2491 
 "move\t%0, %1")
2492 
 
2493 
(define_insn "nop"
2494 
  [(const_int 0)]
2495 
  ""
2496 
  "nop"
2497 
  [(set_attr "type" "Y01")])
2498 
 
2499 
 
2500 
;;
2501 
;; Conditional branches
2502 
;;
2503 
 
2504 
(define_expand "cbranch4"
2505 
  [(set (pc)
2506 
      (if_then_else (match_operator 0 "ordered_comparison_operator"
2507 
                     [(match_operand:FI48MODE 1 "reg_or_cint_operand")
2508 
                        (match_operand:FI48MODE 2 "reg_or_cint_operand")])
2509 
                      (label_ref (match_operand 3 ""))
2510 
                    (pc)))]
2511 
   ""
2512 
{
2513 
  tilegx_emit_conditional_branch (operands, GET_MODE (operands[1]));
2514 
  DONE;
2515 
})
2516 
 
2517 
(define_insn "*bcc_normal"
2518 
  [(set (pc)
2519 
        (if_then_else
2520 
         (match_operator 1 "signed_comparison_operator"
2521 
                         [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2522 
                          (const_int 0)])
2523 
         (label_ref (match_operand 0 "" ""))
2524 
         (pc)))]
2525 
  ""
2526 
  { return tilegx_output_cbranch (insn, operands, false); }
2527 
  [(set_attr "type" "X1_branch")])
2528 
 
2529 
(define_insn "*bcc_reverse"
2530 
  [(set (pc)
2531 
        (if_then_else
2532 
         (match_operator 1 "signed_comparison_operator"
2533 
                         [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2534 
                          (const_int 0)])
2535 
         (pc)
2536 
         (label_ref (match_operand 0 "" ""))))]
2537 
  ""
2538 
  { return tilegx_output_cbranch (insn, operands, true); }
2539 
  [(set_attr "type" "X1_branch")])
2540 
 
2541 
(define_insn "*blbs_normal"
2542 
  [(set (pc)
2543 
        (if_then_else
2544 
         (ne (zero_extract:I48MODE
2545 
              (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2546 
              (const_int 1)
2547 
              (const_int 0))
2548 
             (const_int 0))
2549 
         (label_ref (match_operand 0 "" ""))
2550 
         (pc)))]
2551 
  ""
2552 
  { return tilegx_output_cbranch_with_opcode (insn, operands, "blbs", "blbc",
2553 
                                              1); }
2554 
  [(set_attr "type" "X1_branch")])
2555 
 
2556 
(define_insn "*blbc_normal"
2557 
  [(set (pc)
2558 
        (if_then_else
2559 
         (eq (zero_extract:I48MODE
2560 
              (match_operand:I48MODE 1 "reg_or_0_operand" "rO")
2561 
              (const_int 1)
2562 
              (const_int 0))
2563 
             (const_int 0))
2564 
         (label_ref (match_operand 0 "" ""))
2565 
         (pc)))]
2566 
  ""
2567 
  { return tilegx_output_cbranch_with_opcode (insn, operands, "blbc", "blbs",
2568 
                                              1); }
2569 
  [(set_attr "type" "X1_branch")])
2570 
 
2571 
;; Note that __insn_mf() expands to this.
2572 
(define_expand "memory_barrier"
2573 
  [(set (match_dup 0)
2574 
        (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2575 
  ""
2576 
{
2577 
  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
2578 
  MEM_VOLATILE_P (operands[0]) = 1;
2579 
})
2580 
 
2581 
(define_insn "*memory_barrier"
2582 
  [(set (match_operand:BLK 0 "" "")
2583 
        (unspec_volatile:BLK [(match_dup 0)] UNSPEC_MF))]
2584 
  ""
2585 
  "mf"
2586 
  [(set_attr "type" "X1")])
2587 
 
2588 
(define_insn "prefetch"
2589 
  [(prefetch (match_operand 0 "address_operand" "rO")
2590 
             (match_operand 1 "const_int_operand" "")
2591 
             (match_operand 2 "const_int_operand" ""))]
2592 
  ""
2593 
{
2594 
  switch (INTVAL (operands[2]))
2595 
    {
2596 
      case 0:
2597 
      case 1: return "prefetch_l3\t%r0";
2598 
      case 2: return "prefetch_l2\t%r0";
2599 
      case 3: return "prefetch_l1\t%r0";
2600 
      default: gcc_unreachable ();
2601 
    }
2602 
}
2603 
  [(set_attr "type" "Y2")])
2604 
 
2605 
 
2606 
;;
2607 
;; "__insn" Intrinsics (some expand directly to normal patterns above).
2608 
;;
2609 
 
2610 
(define_insn "insn_bfexts"
2611 
  [(set (match_operand:DI 0 "register_operand" "=r")
2612 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2613 
                    (match_operand:DI 2 "u6bit_cint_operand" "n")
2614 
                    (match_operand:DI 3 "u6bit_cint_operand" "n")]
2615 
                   UNSPEC_INSN_BFEXTS))]
2616 
  ""
2617 
  "bfexts\t%0, %r1, %2, %3"
2618 
  [(set_attr "type" "X0")])
2619 
 
2620 
(define_insn "insn_bfextu"
2621 
  [(set (match_operand:DI 0 "register_operand" "=r")
2622 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2623 
                    (match_operand:DI 2 "u6bit_cint_operand" "n")
2624 
                    (match_operand:DI 3 "u6bit_cint_operand" "n")]
2625 
                   UNSPEC_INSN_BFEXTU))]
2626 
  ""
2627 
  "bfextu\t%0, %r1, %2, %3"
2628 
  [(set_attr "type" "X0")])
2629 
 
2630 
(define_insn "*bfins"
2631 
  [(set (match_operand:DI 0 "register_operand" "=r")
2632 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2633 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2634 
                    (match_operand:DI 3 "u6bit_cint_operand" "n")
2635 
                    (match_operand:DI 4 "u6bit_cint_operand" "n")]
2636 
                   UNSPEC_INSN_BFINS))]
2637 
   ""
2638 
   "bfins\t%0, %r2, %3, %4"
2639 
   [(set_attr "type" "X0")])
2640 
 
2641 
(define_expand "insn_bfins"
2642 
  [(set (match_operand:DI 0 "register_operand" "")
2643 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "")
2644 
                    (match_operand:DI 2 "reg_or_0_operand" "")
2645 
                    (match_operand:DI 3 "u6bit_cint_operand" "")
2646 
                    (match_operand:DI 4 "u6bit_cint_operand" "")]
2647 
                   UNSPEC_INSN_BFINS))]
2648 
  "INTVAL (operands[3]) != 64"
2649 
{
2650 
  HOST_WIDE_INT first = INTVAL (operands[3]);
2651 
  HOST_WIDE_INT last = INTVAL (operands[4]);
2652 
 
2653 
  if (last >= first)
2654 
    {
2655 
      /* This is not a wacky wraparound case, so we can express this
2656 
         as a standard insv. */
2657 
      if (operands[0] != operands[1])
2658 
        {
2659 
          operands[2] = make_safe_from (operands[2], operands[0]);
2660 
          emit_move_insn (operands[0], operands[1]);
2661 
        }
2662 
 
2663 
      emit_insn (gen_insv (operands[0],
2664 
                           GEN_INT (last - first + 1), operands[3],
2665 
                           operands[2]));
2666 
 
2667 
      DONE;
2668 
    }
2669 
})
2670 
 
2671 
(define_insn "insn_cmpexch"
2672 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2673 
        (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
2674 
   (set (mem:I48MODE (match_dup 1))
2675 
        (unspec_volatile:I48MODE
2676 
         [(mem:I48MODE (match_dup 1))
2677 
          (reg:I48MODE TILEGX_CMPEXCH_REG)
2678 
          (match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
2679 
         UNSPEC_INSN_CMPEXCH))]
2680 
  ""
2681 
  "cmpexch\t%0, %r1, %r2"
2682 
  [(set_attr "type" "X1_L2")])
2683 
 
2684 
(define_insn "insn_cmul"
2685 
  [(set (match_operand:DI 0 "register_operand" "=r")
2686 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2687 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2688 
                   UNSPEC_INSN_CMUL))]
2689 
  ""
2690 
  "cmul\t%0, %r1, %r2"
2691 
  [(set_attr "type" "X0_2cycle")])
2692 
 
2693 
(define_insn "insn_cmula"
2694 
  [(set (match_operand:DI 0 "register_operand" "=r")
2695 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2696 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2697 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
2698 
                   UNSPEC_INSN_CMULA))]
2699 
  ""
2700 
  "cmula\t%0, %r2, %r3"
2701 
  [(set_attr "type" "X0_2cycle")])
2702 
 
2703 
(define_insn "insn_cmulaf"
2704 
  [(set (match_operand:DI 0 "register_operand" "=r")
2705 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2706 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2707 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
2708 
                   UNSPEC_INSN_CMULAF))]
2709 
  ""
2710 
  "cmulaf\t%0, %r2, %r3"
2711 
  [(set_attr "type" "X0_2cycle")])
2712 
 
2713 
(define_insn "insn_cmulf"
2714 
  [(set (match_operand:DI 0 "register_operand" "=r")
2715 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2716 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2717 
                   UNSPEC_INSN_CMULF))]
2718 
  ""
2719 
  "cmulf\t%0, %r1, %r2"
2720 
  [(set_attr "type" "X0_2cycle")])
2721 
 
2722 
(define_insn "insn_cmulfr"
2723 
  [(set (match_operand:DI 0 "register_operand" "=r")
2724 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2725 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2726 
                   UNSPEC_INSN_CMULFR))]
2727 
  ""
2728 
  "cmulfr\t%0, %r1, %r2"
2729 
  [(set_attr "type" "X0_2cycle")])
2730 
 
2731 
(define_insn "insn_cmulh"
2732 
  [(set (match_operand:DI 0 "register_operand" "=r")
2733 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2734 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2735 
                   UNSPEC_INSN_CMULH))]
2736 
  ""
2737 
  "cmulh\t%0, %r1, %r2"
2738 
  [(set_attr "type" "X0_2cycle")])
2739 
 
2740 
(define_insn "insn_cmulhr"
2741 
  [(set (match_operand:DI 0 "register_operand" "=r")
2742 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2743 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2744 
                   UNSPEC_INSN_CMULHR))]
2745 
  ""
2746 
  "cmulhr\t%0, %r1, %r2"
2747 
  [(set_attr "type" "X0_2cycle")])
2748 
 
2749 
(define_insn "insn_crc32_32"
2750 
  [(set (match_operand:DI 0 "register_operand" "=r")
2751 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2752 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2753 
                   UNSPEC_INSN_CRC32_32))]
2754 
  ""
2755 
  "crc32_32\t%0, %r1, %r2"
2756 
  [(set_attr "type" "X0")])
2757 
 
2758 
(define_insn "insn_crc32_8"
2759 
  [(set (match_operand:DI 0 "register_operand" "=r")
2760 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2761 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2762 
                   UNSPEC_INSN_CRC32_8))]
2763 
  ""
2764 
  "crc32_8\t%0, %r1, %r2"
2765 
  [(set_attr "type" "X0")])
2766 
 
2767 
(define_insn "insn_dblalign"
2768 
  [(set (match_operand:DI 0 "register_operand" "=r")
2769 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2770 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2771 
                    (match_operand 3 "pointer_operand" "rO")]
2772 
                   UNSPEC_INSN_DBLALIGN))]
2773 
  ""
2774 
  "dblalign\t%0, %r2, %r3"
2775 
  [(set_attr "type" "X0")])
2776 
 
2777 
(define_insn "insn_dblalign2"
2778 
  [(set (match_operand:DI 0 "register_operand" "=r")
2779 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2780 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2781 
                   UNSPEC_INSN_DBLALIGN2))]
2782 
  ""
2783 
  "dblalign2\t%0, %r1, %r2"
2784 
  [(set_attr "type" "X01")])
2785 
 
2786 
(define_insn "insn_dblalign4"
2787 
  [(set (match_operand:DI 0 "register_operand" "=r")
2788 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2789 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2790 
                   UNSPEC_INSN_DBLALIGN4))]
2791 
  ""
2792 
  "dblalign4\t%0, %r1, %r2"
2793 
  [(set_attr "type" "X01")])
2794 
 
2795 
(define_insn "insn_dblalign6"
2796 
  [(set (match_operand:DI 0 "register_operand" "=r")
2797 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2798 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2799 
                   UNSPEC_INSN_DBLALIGN6))]
2800 
  ""
2801 
  "dblalign6\t%0, %r1, %r2"
2802 
  [(set_attr "type" "X01")])
2803 
 
2804 
(define_insn "insn_dtlbpr"
2805 
  [(unspec_volatile:VOID [(match_operand:DI 0 "reg_or_0_operand" "rO")]
2806 
                         UNSPEC_INSN_DTLBPR)]
2807 
  ""
2808 
  "dtlbpr\t%r0"
2809 
  [(set_attr "type" "X1")])
2810 
 
2811 
(define_insn "insn_exch"
2812 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2813 
        (mem:I48MODE (match_operand 1 "pointer_operand" "rO")))
2814 
   (set (mem:I48MODE (match_dup 1))
2815 
        (unspec_volatile:I48MODE
2816 
         [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
2817 
         UNSPEC_INSN_EXCH))]
2818 
  ""
2819 
  "exch\t%0, %r1, %r2"
2820 
  [(set_attr "type" "X1_2cycle")])
2821 
 
2822 
(define_insn "insn_fdouble_add_flags"
2823 
  [(set (match_operand:DI 0 "register_operand" "=r")
2824 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2825 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2826 
                   UNSPEC_INSN_FDOUBLE_ADD_FLAGS))]
2827 
  ""
2828 
  "fdouble_add_flags\t%0, %r1, %r2"
2829 
  [(set_attr "type" "X0_2cycle")])
2830 
 
2831 
(define_insn "insn_fdouble_addsub"
2832 
  [(set (match_operand:DI 0 "register_operand" "=r")
2833 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2834 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2835 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
2836 
                   UNSPEC_INSN_FDOUBLE_ADDSUB))]
2837 
  ""
2838 
  "fdouble_addsub\t%0, %r2, %r3"
2839 
  [(set_attr "type" "X0_2cycle")])
2840 
 
2841 
(define_insn "insn_fdouble_mul_flags"
2842 
  [(set (match_operand:DI 0 "register_operand" "=r")
2843 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2844 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2845 
                   UNSPEC_INSN_FDOUBLE_MUL_FLAGS))]
2846 
  ""
2847 
  "fdouble_mul_flags\t%0, %r1, %r2"
2848 
  [(set_attr "type" "X0_2cycle")])
2849 
 
2850 
(define_insn "insn_fdouble_pack1"
2851 
  [(set (match_operand:DI 0 "register_operand" "=r")
2852 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2853 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2854 
                   UNSPEC_INSN_FDOUBLE_PACK1))]
2855 
  ""
2856 
  "fdouble_pack1\t%0, %r1, %r2"
2857 
  [(set_attr "type" "X0_2cycle")])
2858 
 
2859 
(define_insn "insn_fdouble_pack2"
2860 
  [(set (match_operand:DI 0 "register_operand" "=r")
2861 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2862 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2863 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
2864 
                   UNSPEC_INSN_FDOUBLE_PACK2))]
2865 
  ""
2866 
  "fdouble_pack2\t%0, %r2, %r3"
2867 
  [(set_attr "type" "X0_2cycle")])
2868 
 
2869 
(define_insn "insn_fdouble_sub_flags"
2870 
  [(set (match_operand:DI 0 "register_operand" "=r")
2871 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2872 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2873 
                   UNSPEC_INSN_FDOUBLE_SUB_FLAGS))]
2874 
  ""
2875 
  "fdouble_sub_flags\t%0, %r1, %r2"
2876 
  [(set_attr "type" "X0_2cycle")])
2877 
 
2878 
(define_insn "insn_fdouble_unpack_max"
2879 
  [(set (match_operand:DI 0 "register_operand" "=r")
2880 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2881 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2882 
                   UNSPEC_INSN_FDOUBLE_UNPACK_MAX))]
2883 
  ""
2884 
  "fdouble_unpack_max\t%0, %r1, %r2"
2885 
  [(set_attr "type" "X0_2cycle")])
2886 
 
2887 
(define_insn "insn_fdouble_unpack_min"
2888 
  [(set (match_operand:DI 0 "register_operand" "=r")
2889 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2890 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2891 
                   UNSPEC_INSN_FDOUBLE_UNPACK_MIN))]
2892 
  ""
2893 
  "fdouble_unpack_min\t%0, %r1, %r2"
2894 
  [(set_attr "type" "X0_2cycle")])
2895 
 
2896 
(define_insn "insn_fetchadd"
2897 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2898 
        (unspec_volatile:I48MODE
2899 
         [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
2900 
         UNSPEC_ATOMIC))
2901 
   (set (mem:I48MODE (match_dup 1))
2902 
        (plus:I48MODE (mem:I48MODE (match_dup 1))
2903 
                      (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
2904 
  ""
2905 
  "fetchadd\t%0, %r1, %r2"
2906 
  [(set_attr "type" "X1_2cycle")])
2907 
 
2908 
(define_insn "insn_fetchaddgez"
2909 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2910 
        (unspec_volatile:I48MODE
2911 
         [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
2912 
         UNSPEC_ATOMIC))
2913 
   (set (mem:I48MODE (match_dup 1))
2914 
        (unspec:I48MODE [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")
2915 
                         (mem:I48MODE (match_dup 1))]
2916 
                        UNSPEC_INSN_FETCHADDGEZ))]
2917 
  ""
2918 
  "fetchaddgez\t%0, %r1, %r2"
2919 
  [(set_attr "type" "X1_2cycle")])
2920 
 
2921 
(define_insn "insn_fetchand"
2922 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2923 
        (unspec_volatile:I48MODE
2924 
         [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
2925 
         UNSPEC_ATOMIC))
2926 
   (set (mem:I48MODE (match_dup 1))
2927 
        (and:I48MODE (mem:I48MODE (match_dup 1))
2928 
                     (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
2929 
  ""
2930 
  "fetchand\t%0, %r1, %r2"
2931 
  [(set_attr "type" "X1_2cycle")])
2932 
 
2933 
(define_insn "insn_fetchor"
2934 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
2935 
        (unspec_volatile:I48MODE
2936 
         [(mem:I48MODE (match_operand 1 "pointer_operand" "rO"))]
2937 
         UNSPEC_ATOMIC))
2938 
   (set (mem:I48MODE (match_dup 1))
2939 
        (ior:I48MODE (mem:I48MODE (match_dup 1))
2940 
                     (match_operand:I48MODE 2 "reg_or_0_operand" "rO")))]
2941 
  ""
2942 
  "fetchor\t%0, %r1, %r2"
2943 
  [(set_attr "type" "X1_2cycle")])
2944 
 
2945 
(define_insn "insn_finv"
2946 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
2947 
                         UNSPEC_INSN_FINV)]
2948 
  ""
2949 
  "finv\t%r0"
2950 
  [(set_attr "type" "X1")])
2951 
 
2952 
(define_insn "insn_flush"
2953 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
2954 
                         UNSPEC_INSN_FLUSH)]
2955 
  ""
2956 
  "flush\t%r0"
2957 
  [(set_attr "type" "X1")])
2958 
 
2959 
(define_insn "insn_flushwb"
2960 
  [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FLUSHWB)]
2961 
  ""
2962 
  "flushwb"
2963 
  [(set_attr "type" "X1")])
2964 
 
2965 
(define_insn "insn_fnop"
2966 
  [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_FNOP)]
2967 
  ""
2968 
  "fnop")
2969 
 
2970 
(define_insn "insn_fsingle_add1"
2971 
  [(set (match_operand:DI 0 "register_operand" "=r")
2972 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2973 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2974 
                   UNSPEC_INSN_FSINGLE_ADD1))]
2975 
  ""
2976 
  "fsingle_add1\t%0, %r1, %r2"
2977 
  [(set_attr "type" "X0")])
2978 
 
2979 
(define_insn "insn_fsingle_addsub2"
2980 
  [(set (match_operand:DI 0 "register_operand" "=r")
2981 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
2982 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
2983 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
2984 
                   UNSPEC_INSN_FSINGLE_ADDSUB2))]
2985 
  ""
2986 
  "fsingle_addsub2\t%0, %r2, %r3"
2987 
  [(set_attr "type" "X0_2cycle")])
2988 
 
2989 
(define_insn "insn_fsingle_mul1"
2990 
  [(set (match_operand:DI 0 "register_operand" "=r")
2991 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
2992 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
2993 
                   UNSPEC_INSN_FSINGLE_MUL1))]
2994 
  ""
2995 
  "fsingle_mul1\t%0, %r1, %r2"
2996 
  [(set_attr "type" "X0")])
2997 
 
2998 
(define_insn "insn_fsingle_mul2"
2999 
  [(set (match_operand:DI 0 "register_operand" "=r")
3000 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3001 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3002 
                   UNSPEC_INSN_FSINGLE_MUL2))]
3003 
  ""
3004 
  "fsingle_mul2\t%0, %r1, %r2"
3005 
  [(set_attr "type" "X0_2cycle")])
3006 
 
3007 
(define_insn "insn_fsingle_pack1"
3008 
  [(set (match_operand:DI 0 "register_operand" "=r")
3009 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3010 
                   UNSPEC_INSN_FSINGLE_PACK1))]
3011 
  ""
3012 
  "fsingle_pack1\t%0, %r1"
3013 
  [(set_attr "type" "Y0_2cycle")])
3014 
 
3015 
(define_insn "insn_fsingle_pack2"
3016 
  [(set (match_operand:DI 0 "register_operand" "=r")
3017 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3018 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3019 
                   UNSPEC_INSN_FSINGLE_PACK2))]
3020 
  ""
3021 
  "fsingle_pack2\t%0, %r1, %r2"
3022 
  [(set_attr "type" "X0_2cycle")])
3023 
 
3024 
(define_insn "insn_fsingle_sub1"
3025 
  [(set (match_operand:DI 0 "register_operand" "=r")
3026 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3027 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3028 
                   UNSPEC_INSN_FSINGLE_SUB1))]
3029 
  ""
3030 
  "fsingle_sub1\t%0, %r1, %r2"
3031 
  [(set_attr "type" "X0")])
3032 
 
3033 
(define_insn "insn_drain"
3034 
  [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_DRAIN)]
3035 
  ""
3036 
  "drain"
3037 
  [(set_attr "type" "cannot_bundle")])
3038 
 
3039 
(define_insn "insn_icoh"
3040 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3041 
                         UNSPEC_INSN_ICOH)]
3042 
  ""
3043 
  "icoh\t%r0"
3044 
  [(set_attr "type" "X1")])
3045 
 
3046 
(define_insn "insn_ill"
3047 
  [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_ILL)]
3048 
  ""
3049 
  "ill"
3050 
  [(set_attr "type" "cannot_bundle")])
3051 
 
3052 
(define_insn "insn_info"
3053 
  [(unspec_volatile:VOID [(match_operand:DI 0 "s8bit_cint_operand" "i")]
3054 
                         UNSPEC_INSN_INFO)]
3055 
  ""
3056 
  "info\t%0")
3057 
 
3058 
(define_insn "insn_infol"
3059 
  [(unspec_volatile:VOID [(match_operand:DI 0 "s16bit_cint_operand" "i")]
3060 
                         UNSPEC_INSN_INFOL)]
3061 
  ""
3062 
  "infol\t%0"
3063 
  [(set_attr "type" "X01")])
3064 
 
3065 
(define_insn "insn_inv"
3066 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3067 
                         UNSPEC_INSN_INV)]
3068 
  ""
3069 
  "inv\t%r0"
3070 
  [(set_attr "type" "X1")])
3071 
 
3072 
;; loads
3073 
 
3074 
(define_expand "insn_ld"
3075 
  [(set (match_operand:DI 0 "register_operand" "")
3076 
        (mem:DI (match_operand 1 "pointer_operand" "")))]
3077 
  "")
3078 
 
3079 
(define_insn "insn_ld_add"
3080 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3081 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3082 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3083 
   (set (match_operand:DI 0 "register_operand" "=r")
3084 
        (mem:DI (match_dup 3)))]
3085 
  ""
3086 
  "ld_add\t%0, %1, %2"
3087 
  [(set_attr "type" "X1_2cycle")])
3088 
 
3089 
(define_insn "insn_ldna"
3090 
  [(set (match_operand:DI 0 "register_operand" "=r")
3091 
        (mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3092 
                        (const_int -8))))]
3093 
  ""
3094 
  "ldna\t%0, %r1"
3095 
  [(set_attr "type" "X1_2cycle")])
3096 
 
3097 
(define_insn "insn_ldna_add"
3098 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3099 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3100 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3101 
   (set (match_operand:DI 0 "register_operand" "=r")
3102 
        (mem:DI (and:DI (match_dup 3) (const_int -8))))]
3103 
  ""
3104 
  "ldna_add\t%0, %1, %2"
3105 
  [(set_attr "type" "X1_2cycle")])
3106 
 
3107 
(define_expand "insn_ld"
3108 
  [(set (match_operand:DI 0 "register_operand" "")
3109 
        (any_extend:DI
3110 
         (mem:I124MODE (match_operand 1 "pointer_operand" ""))))]
3111 
  "")
3112 
 
3113 
(define_insn "insn_ld_add"
3114 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3115 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3116 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3117 
   (set (match_operand:DI 0 "register_operand" "=r")
3118 
        (any_extend:DI (mem:I124MODE (match_dup 3))))]
3119 
  ""
3120 
  "ld_add\t%0, %1, %2"
3121 
  [(set_attr "type" "X1_2cycle")])
3122 
 
3123 
;; non temporal loads
3124 
 
3125 
(define_insn "insn_ldnt"
3126 
  [(set (match_operand:DI 0 "register_operand" "=r")
3127 
        (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3128 
                   UNSPEC_NON_TEMPORAL))]
3129 
  ""
3130 
  "ldnt\t%0, %r1"
3131 
  [(set_attr "type" "X1_2cycle")])
3132 
 
3133 
(define_insn "insn_ldnt_add"
3134 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3135 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3136 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3137 
   (set (match_operand:DI 0 "register_operand" "=r")
3138 
        (unspec:DI [(mem:DI (match_dup 3))]
3139 
                   UNSPEC_NON_TEMPORAL))]
3140 
  ""
3141 
  "ldnt_add\t%0, %1, %2"
3142 
  [(set_attr "type" "X1_2cycle")])
3143 
 
3144 
(define_insn "insn_ldnt"
3145 
  [(set (match_operand:DI 0 "register_operand" "=r")
3146 
        (any_extend:DI
3147 
         (unspec:I124MODE
3148 
          [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3149 
          UNSPEC_NON_TEMPORAL)))]
3150 
  ""
3151 
  "ldnt\t%0, %r1"
3152 
  [(set_attr "type" "X1_2cycle")])
3153 
 
3154 
(define_insn "insn_ldnt_add"
3155 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3156 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3157 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3158 
   (set (match_operand:DI 0 "register_operand" "=r")
3159 
        (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3160 
                                        UNSPEC_NON_TEMPORAL)))]
3161 
  ""
3162 
  "ldnt_add\t%0, %1, %2"
3163 
  [(set_attr "type" "X1_2cycle")])
3164 
 
3165 
;; L2 hits
3166 
 
3167 
(define_insn "insn_ld_L2"
3168 
  [(set (match_operand:DI 0 "register_operand" "=r")
3169 
        (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3170 
                   UNSPEC_LATENCY_L2))]
3171 
  ""
3172 
  "ld\t%0, %r1"
3173 
  [(set_attr "type" "Y2_L2")])
3174 
 
3175 
(define_insn "insn_ld_add_L2"
3176 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3177 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3178 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3179 
   (set (match_operand:DI 0 "register_operand" "=r")
3180 
        (unspec:DI [(mem:DI (match_dup 3))]
3181 
                   UNSPEC_LATENCY_L2))]
3182 
  ""
3183 
  "ld_add\t%0, %1, %2"
3184 
  [(set_attr "type" "X1_L2")])
3185 
 
3186 
(define_insn "insn_ldna_L2"
3187 
  [(set (match_operand:DI 0 "register_operand" "=r")
3188 
        (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3189 
                                    (const_int -8)))]
3190 
                   UNSPEC_LATENCY_L2))]
3191 
  ""
3192 
  "ldna\t%0, %r1"
3193 
  [(set_attr "type" "X1_L2")])
3194 
 
3195 
(define_insn "insn_ldna_add_L2"
3196 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3197 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3198 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3199 
   (set (match_operand:DI 0 "register_operand" "=r")
3200 
        (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3201 
                   UNSPEC_LATENCY_L2))]
3202 
  ""
3203 
  "ldna_add\t%0, %1, %2"
3204 
  [(set_attr "type" "X1_L2")])
3205 
 
3206 
(define_insn "insn_ld_L2"
3207 
  [(set (match_operand:DI 0 "register_operand" "=r")
3208 
        (any_extend:DI
3209 
         (unspec:I124MODE
3210 
          [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3211 
          UNSPEC_LATENCY_L2)))]
3212 
  ""
3213 
  "ld\t%0, %r1"
3214 
  [(set_attr "type" "Y2_L2")])
3215 
 
3216 
(define_insn "insn_ld_add_L2"
3217 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3218 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3219 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3220 
   (set (match_operand:DI 0 "register_operand" "=r")
3221 
        (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3222 
                                        UNSPEC_LATENCY_L2)))]
3223 
  ""
3224 
  "ld_add\t%0, %1, %2"
3225 
  [(set_attr "type" "X1_L2")])
3226 
 
3227 
;; L2 hits, non temporal loads
3228 
 
3229 
(define_insn "insn_ldnt_L2"
3230 
  [(set (match_operand:DI 0 "register_operand" "=r")
3231 
        (unspec:DI [(unspec:DI
3232 
                     [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3233 
                     UNSPEC_NON_TEMPORAL)]
3234 
                   UNSPEC_LATENCY_L2))]
3235 
  ""
3236 
  "ldnt\t%0, %r1"
3237 
  [(set_attr "type" "X1_L2")])
3238 
 
3239 
(define_insn "insn_ldnt_add_L2"
3240 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3241 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3242 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3243 
   (set (match_operand:DI 0 "register_operand" "=r")
3244 
        (unspec:DI [(unspec:DI
3245 
                     [(mem:DI (match_dup 3))]
3246 
                     UNSPEC_NON_TEMPORAL)]
3247 
                   UNSPEC_LATENCY_L2))]
3248 
                   ""
3249 
  "ldnt_add\t%0, %1, %2"
3250 
  [(set_attr "type" "X1_L2")])
3251 
 
3252 
(define_insn "insn_ldnt_L2"
3253 
  [(set (match_operand:DI 0 "register_operand" "=r")
3254 
        (any_extend:DI
3255 
         (unspec:I124MODE
3256 
          [(unspec:I124MODE
3257 
            [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3258 
            UNSPEC_NON_TEMPORAL)]
3259 
          UNSPEC_LATENCY_L2)))]
3260 
  ""
3261 
  "ldnt\t%0, %r1"
3262 
  [(set_attr "type" "X1_L2")])
3263 
 
3264 
(define_insn "insn_ldnt_add_L2"
3265 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3266 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3267 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3268 
   (set (match_operand:DI 0 "register_operand" "=r")
3269 
        (any_extend:DI
3270 
         (unspec:I124MODE [(unspec:I124MODE
3271 
                            [(mem:I124MODE (match_dup 3))]
3272 
                            UNSPEC_NON_TEMPORAL)]
3273 
                          UNSPEC_LATENCY_L2)))]
3274 
  ""
3275 
  "ldnt_add\t%0, %1, %2"
3276 
  [(set_attr "type" "X1_L2")])
3277 
 
3278 
;; L2 miss
3279 
 
3280 
(define_insn "insn_ld_miss"
3281 
  [(set (match_operand:DI 0 "register_operand" "=r")
3282 
        (unspec:DI [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3283 
                   UNSPEC_LATENCY_MISS))]
3284 
  ""
3285 
  "ld\t%0, %r1"
3286 
  [(set_attr "type" "Y2_miss")])
3287 
 
3288 
(define_insn "insn_ld_add_miss"
3289 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3290 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3291 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3292 
   (set (match_operand:DI 0 "register_operand" "=r")
3293 
        (unspec:DI [(mem:DI (match_dup 3))]
3294 
                   UNSPEC_LATENCY_MISS))]
3295 
  ""
3296 
  "ld_add\t%0, %1, %2"
3297 
  [(set_attr "type" "X1_miss")])
3298 
 
3299 
(define_insn "insn_ldna_miss"
3300 
  [(set (match_operand:DI 0 "register_operand" "=r")
3301 
        (unspec:DI [(mem:DI (and:DI (match_operand 1 "pointer_operand" "rO")
3302 
                                    (const_int -8)))]
3303 
                   UNSPEC_LATENCY_MISS))]
3304 
  ""
3305 
  "ldna\t%0, %r1"
3306 
  [(set_attr "type" "X1_miss")])
3307 
 
3308 
(define_insn "insn_ldna_add_miss"
3309 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3310 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3311 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3312 
   (set (match_operand:DI 0 "register_operand" "=r")
3313 
        (unspec:DI [(mem:DI (and:DI (match_dup 3) (const_int -8)))]
3314 
                   UNSPEC_LATENCY_MISS))]
3315 
  ""
3316 
  "ldna_add\t%0, %1, %2"
3317 
  [(set_attr "type" "X1_miss")])
3318 
 
3319 
(define_insn "insn_ld_miss"
3320 
  [(set (match_operand:DI 0 "register_operand" "=r")
3321 
        (any_extend:DI
3322 
         (unspec:I124MODE
3323 
          [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3324 
          UNSPEC_LATENCY_MISS)))]
3325 
  ""
3326 
  "ld\t%0, %r1"
3327 
  [(set_attr "type" "Y2_miss")])
3328 
 
3329 
(define_insn "insn_ld_add_miss"
3330 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3331 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3332 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3333 
   (set (match_operand:DI 0 "register_operand" "=r")
3334 
        (any_extend:DI (unspec:I124MODE [(mem:I124MODE (match_dup 3))]
3335 
                                        UNSPEC_LATENCY_MISS)))]
3336 
  ""
3337 
  "ld_add\t%0, %1, %2"
3338 
  [(set_attr "type" "X1_miss")])
3339 
 
3340 
;; L2 miss, non temporal loads
3341 
 
3342 
(define_insn "insn_ldnt_miss"
3343 
  [(set (match_operand:DI 0 "register_operand" "=r")
3344 
        (unspec:DI [(unspec:DI
3345 
                     [(mem:DI (match_operand 1 "pointer_operand" "rO"))]
3346 
                     UNSPEC_NON_TEMPORAL)]
3347 
                   UNSPEC_LATENCY_MISS))]
3348 
  ""
3349 
  "ldnt\t%0, %r1"
3350 
  [(set_attr "type" "X1_miss")])
3351 
 
3352 
(define_insn "insn_ldnt_add_miss"
3353 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3354 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3355 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3356 
   (set (match_operand:DI 0 "register_operand" "=r")
3357 
        (unspec:DI [(unspec:DI
3358 
                     [(mem:DI (match_dup 3))]
3359 
                     UNSPEC_NON_TEMPORAL)]
3360 
                   UNSPEC_LATENCY_MISS))]
3361 
                   ""
3362 
  "ldnt_add\t%0, %1, %2"
3363 
  [(set_attr "type" "X1_miss")])
3364 
 
3365 
(define_insn "insn_ldnt_miss"
3366 
  [(set (match_operand:DI 0 "register_operand" "=r")
3367 
        (any_extend:DI
3368 
         (unspec:I124MODE
3369 
          [(unspec:I124MODE
3370 
            [(mem:I124MODE (match_operand 1 "pointer_operand" "rO"))]
3371 
            UNSPEC_NON_TEMPORAL)]
3372 
          UNSPEC_LATENCY_MISS)))]
3373 
  ""
3374 
  "ldnt\t%0, %r1"
3375 
  [(set_attr "type" "X1_miss")])
3376 
 
3377 
(define_insn "insn_ldnt_add_miss"
3378 
  [(set (match_operand:I48MODE 1 "pointer_operand" "=r")
3379 
        (plus:I48MODE (match_operand 3 "pointer_operand" "1")
3380 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3381 
   (set (match_operand:DI 0 "register_operand" "=r")
3382 
        (any_extend:DI
3383 
         (unspec:I124MODE [(unspec:I124MODE
3384 
                      [(mem:I124MODE (match_dup 3))]
3385 
                      UNSPEC_NON_TEMPORAL)]
3386 
                    UNSPEC_LATENCY_MISS)))]
3387 
  ""
3388 
  "ldnt_add\t%0, %1, %2"
3389 
  [(set_attr "type" "X1_miss")])
3390 
 
3391 
;; end loads
3392 
 
3393 
(define_insn "insn_lnk"
3394 
  [(set (match_operand:DI 0 "register_operand" "=r")
3395 
        (unspec:DI [(const_int 0)] UNSPEC_INSN_LNK))]
3396 
  ""
3397 
  "lnk\t%0"
3398 
  [(set_attr "type" "Y1")])
3399 
 
3400 
(define_insn "insn_mfspr"
3401 
  [(set (match_operand:DI 0 "register_operand" "=r")
3402 
        (unspec_volatile:DI [(match_operand:DI 1 "u14bit_cint_operand" "i")]
3403 
                            UNSPEC_INSN_MFSPR))
3404 
   (clobber (mem:BLK (const_int 0)))]
3405 
  ""
3406 
  "mfspr\t%0, %1"
3407 
  [(set_attr "type" "X1")])
3408 
 
3409 
(define_insn "insn_mtspr"
3410 
  [(unspec_volatile:DI [(match_operand:DI 0 "u14bit_cint_operand" "i")
3411 
                        (match_operand:DI 1 "reg_or_0_operand" "rO")]
3412 
                       UNSPEC_INSN_MTSPR)
3413 
   (clobber (mem:BLK (const_int 0)))]
3414 
  ""
3415 
  "mtspr\t%0, %r1"
3416 
  [(set_attr "type" "X1")])
3417 
 
3418 
(define_insn "insn_mm"
3419 
  [(set (match_operand:DI 0 "register_operand" "=r")
3420 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3421 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3422 
                    (match_operand:DI 3 "u6bit_cint_operand" "i")
3423 
                    (match_operand:DI 4 "u6bit_cint_operand" "i")]
3424 
                   UNSPEC_INSN_MM))]
3425 
  ""
3426 
  "mm\t%0, %r2, %3, %4"
3427 
  [(set_attr "type" "X0")])
3428 
 
3429 
(define_insn "insn_mul_hs_hs"
3430 
  [(set (match_operand:DI 0 "register_operand" "=r")
3431 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3432 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3433 
                   UNSPEC_INSN_MUL_HS_HS))]
3434 
  ""
3435 
  "mul_hs_hs\t%0, %r1, %r2"
3436 
  [(set_attr "type" "Y0_2cycle")])
3437 
 
3438 
(define_insn "insn_mul_hs_hu"
3439 
  [(set (match_operand:DI 0 "register_operand" "=r")
3440 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3441 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3442 
                   UNSPEC_INSN_MUL_HS_HU))]
3443 
  ""
3444 
  "mul_hs_hu\t%0, %r1, %r2"
3445 
  [(set_attr "type" "X0_2cycle")])
3446 
 
3447 
(define_insn "insn_mul_hs_ls"
3448 
  [(set (match_operand:DI 0 "register_operand" "=r")
3449 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3450 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3451 
                   UNSPEC_INSN_MUL_HS_LS))]
3452 
  ""
3453 
  "mul_hs_ls\t%0, %r1, %r2"
3454 
  [(set_attr "type" "X0_2cycle")])
3455 
 
3456 
(define_insn "insn_mul_hs_lu"
3457 
  [(set (match_operand:DI 0 "register_operand" "=r")
3458 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3459 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3460 
                   UNSPEC_INSN_MUL_HS_LU))]
3461 
  ""
3462 
  "mul_hs_lu\t%0, %r1, %r2"
3463 
  [(set_attr "type" "X0_2cycle")])
3464 
 
3465 
(define_insn "insn_mul_hu_hu"
3466 
  [(set (match_operand:DI 0 "register_operand" "=r")
3467 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3468 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3469 
                   UNSPEC_INSN_MUL_HU_HU))]
3470 
  ""
3471 
  "mul_hu_hu\t%0, %r1, %r2"
3472 
  [(set_attr "type" "Y0_2cycle")])
3473 
 
3474 
(define_insn "insn_mul_hu_ls"
3475 
  [(set (match_operand:DI 0 "register_operand" "=r")
3476 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3477 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3478 
                   UNSPEC_INSN_MUL_HU_LS))]
3479 
  ""
3480 
  "mul_hu_ls\t%0, %r1, %r2"
3481 
  [(set_attr "type" "X0_2cycle")])
3482 
 
3483 
(define_insn "insn_mul_hu_lu"
3484 
  [(set (match_operand:DI 0 "register_operand" "=r")
3485 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3486 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3487 
                   UNSPEC_INSN_MUL_HU_LU))]
3488 
  ""
3489 
  "mul_hu_lu\t%0, %r1, %r2"
3490 
  [(set_attr "type" "X0_2cycle")])
3491 
 
3492 
(define_insn "insn_mul_ls_ls"
3493 
  [(set (match_operand:DI 0 "register_operand" "=r")
3494 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3495 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3496 
                   UNSPEC_INSN_MUL_LS_LS))]
3497 
  ""
3498 
  "mul_ls_ls\t%0, %r1, %r2"
3499 
  [(set_attr "type" "Y0_2cycle")])
3500 
 
3501 
(define_insn "insn_mul_ls_lu"
3502 
  [(set (match_operand:DI 0 "register_operand" "=r")
3503 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3504 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3505 
                   UNSPEC_INSN_MUL_LS_LU))]
3506 
  ""
3507 
  "mul_ls_lu\t%0, %r1, %r2"
3508 
  [(set_attr "type" "X0_2cycle")])
3509 
 
3510 
(define_insn "insn_mul_lu_lu"
3511 
  [(set (match_operand:DI 0 "register_operand" "=r")
3512 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
3513 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3514 
                   UNSPEC_INSN_MUL_LU_LU))]
3515 
  ""
3516 
  "mul_lu_lu\t%0, %r1, %r2"
3517 
  [(set_attr "type" "Y0_2cycle")])
3518 
 
3519 
(define_insn "insn_mula_hs_hs"
3520 
  [(set (match_operand:DI 0 "register_operand" "=r")
3521 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3522 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3523 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3524 
                   UNSPEC_INSN_MULA_HS_HS))]
3525 
  ""
3526 
  "mula_hs_hs\t%0, %r2, %r3"
3527 
  [(set_attr "type" "Y0_2cycle")])
3528 
 
3529 
(define_insn "insn_mula_hs_hu"
3530 
  [(set (match_operand:DI 0 "register_operand" "=r")
3531 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3532 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3533 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3534 
                   UNSPEC_INSN_MULA_HS_HU))]
3535 
  ""
3536 
  "mula_hs_hu\t%0, %r2, %r3"
3537 
  [(set_attr "type" "X0_2cycle")])
3538 
 
3539 
(define_insn "insn_mula_hs_ls"
3540 
  [(set (match_operand:DI 0 "register_operand" "=r")
3541 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3542 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3543 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3544 
                   UNSPEC_INSN_MULA_HS_LS))]
3545 
  ""
3546 
  "mula_hs_ls\t%0, %r2, %r3"
3547 
  [(set_attr "type" "X0_2cycle")])
3548 
 
3549 
(define_insn "insn_mula_hs_lu"
3550 
  [(set (match_operand:DI 0 "register_operand" "=r")
3551 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3552 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3553 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3554 
                   UNSPEC_INSN_MULA_HS_LU))]
3555 
  ""
3556 
  "mula_hs_lu\t%0, %r2, %r3"
3557 
  [(set_attr "type" "X0_2cycle")])
3558 
 
3559 
(define_insn "insn_mula_hu_hu"
3560 
  [(set (match_operand:DI 0 "register_operand" "=r")
3561 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3562 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3563 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3564 
                   UNSPEC_INSN_MULA_HU_HU))]
3565 
  ""
3566 
  "mula_hu_hu\t%0, %r2, %r3"
3567 
  [(set_attr "type" "Y0_2cycle")])
3568 
 
3569 
(define_insn "insn_mula_hu_ls"
3570 
  [(set (match_operand:DI 0 "register_operand" "=r")
3571 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3572 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3573 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3574 
                   UNSPEC_INSN_MULA_HU_LS))]
3575 
  ""
3576 
  "mula_hu_ls\t%0, %r2, %r3"
3577 
  [(set_attr "type" "X0_2cycle")])
3578 
 
3579 
(define_insn "insn_mula_hu_lu"
3580 
  [(set (match_operand:DI 0 "register_operand" "=r")
3581 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3582 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3583 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3584 
                   UNSPEC_INSN_MULA_HU_LU))]
3585 
  ""
3586 
  "mula_hu_lu\t%0, %r2, %r3"
3587 
  [(set_attr "type" "X0_2cycle")])
3588 
 
3589 
(define_insn "insn_mula_ls_ls"
3590 
  [(set (match_operand:DI 0 "register_operand" "=r")
3591 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3592 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3593 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3594 
                   UNSPEC_INSN_MULA_LS_LS))]
3595 
  ""
3596 
  "mula_ls_ls\t%0, %r2, %r3"
3597 
  [(set_attr "type" "Y0_2cycle")])
3598 
 
3599 
(define_insn "insn_mula_ls_lu"
3600 
  [(set (match_operand:DI 0 "register_operand" "=r")
3601 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3602 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3603 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3604 
                   UNSPEC_INSN_MULA_LS_LU))]
3605 
  ""
3606 
  "mula_ls_lu\t%0, %r2, %r3"
3607 
  [(set_attr "type" "X0_2cycle")])
3608 
 
3609 
(define_insn "insn_mula_lu_lu"
3610 
  [(set (match_operand:DI 0 "register_operand" "=r")
3611 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3612 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3613 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3614 
                   UNSPEC_INSN_MULA_LU_LU))]
3615 
  ""
3616 
  "mula_lu_lu\t%0, %r2, %r3"
3617 
  [(set_attr "type" "Y0_2cycle")])
3618 
 
3619 
(define_insn "insn_mulax"
3620 
  [(set (match_operand:SI 0 "register_operand" "=r")
3621 
        (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "0")
3622 
                    (match_operand:SI 2 "reg_or_0_operand" "rO")
3623 
                    (match_operand:SI 3 "reg_or_0_operand" "rO")]
3624 
                   UNSPEC_INSN_MULAX))]
3625 
  ""
3626 
  "mulax\t%0, %r2, %r3"
3627 
  [(set_attr "type" "Y0_2cycle")])
3628 
 
3629 
(define_insn "insn_nap"
3630 
  [(unspec_volatile:VOID [(const_int 0)] UNSPEC_INSN_NAP)]
3631 
  ""
3632 
  "nap"
3633 
  [(set_attr "type" "cannot_bundle")])
3634 
 
3635 
(define_insn "insn_nor_"
3636 
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
3637 
        (and:I48MODE
3638 
         (not:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rO"))
3639 
         (not:I48MODE (match_operand:I48MODE 2 "reg_or_0_operand" "rO"))))]
3640 
  ""
3641 
  "nor\t%0, %r1, %r2")
3642 
 
3643 
(define_expand "insn_prefetch_l1"
3644 
  [(prefetch (match_operand 0 "pointer_operand" "")
3645 
             (const_int 0)
3646 
             (const_int 3))]
3647 
  "")
3648 
 
3649 
(define_expand "insn_prefetch_l2"
3650 
  [(prefetch (match_operand 0 "pointer_operand" "")
3651 
             (const_int 0)
3652 
             (const_int 2))]
3653 
  "")
3654 
 
3655 
(define_expand "insn_prefetch_l3"
3656 
  [(prefetch (match_operand 0 "pointer_operand" "")
3657 
             (const_int 0)
3658 
             (const_int 1))]
3659 
  "")
3660 
 
3661 
(define_insn "insn_prefetch_l1_fault"
3662 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3663 
                         UNSPEC_INSN_PREFETCH_L1_FAULT)]
3664 
  ""
3665 
  "prefetch_l1_fault\t%r0"
3666 
  [(set_attr "type" "Y2")])
3667 
 
3668 
(define_insn "insn_prefetch_l2_fault"
3669 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3670 
                         UNSPEC_INSN_PREFETCH_L2_FAULT)]
3671 
  ""
3672 
  "prefetch_l2_fault\t%r0"
3673 
  [(set_attr "type" "Y2")])
3674 
 
3675 
(define_insn "insn_prefetch_l3_fault"
3676 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
3677 
                         UNSPEC_INSN_PREFETCH_L3_FAULT)]
3678 
  ""
3679 
  "prefetch_l3_fault\t%r0"
3680 
  [(set_attr "type" "Y2")])
3681 
 
3682 
(define_insn "insn_revbits"
3683 
  [(set (match_operand:DI 0 "register_operand" "=r")
3684 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")]
3685 
                   UNSPEC_INSN_REVBITS))]
3686 
  ""
3687 
  "revbits\t%0, %r1"
3688 
  [(set_attr "type" "Y0")])
3689 
 
3690 
(define_insn "insn_shl1add"
3691 
  [(set (match_operand:DI 0 "register_operand" "=r")
3692 
        (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3693 
                          (const_int 2))
3694 
                 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3695 
  ""
3696 
  "shl1add\t%0, %r1, %r2")
3697 
 
3698 
(define_insn "insn_shl1addx"
3699 
  [(set (match_operand:SI 0 "register_operand" "=r")
3700 
        (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3701 
                          (const_int 2))
3702 
                 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3703 
  ""
3704 
  "shl1addx\t%0, %r1, %r2")
3705 
 
3706 
(define_insn "insn_shl2add"
3707 
  [(set (match_operand:DI 0 "register_operand" "=r")
3708 
        (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3709 
                          (const_int 4))
3710 
                 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3711 
  ""
3712 
  "shl2add\t%0, %r1, %r2")
3713 
 
3714 
(define_insn "insn_shl2addx"
3715 
  [(set (match_operand:SI 0 "register_operand" "=r")
3716 
        (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3717 
                          (const_int 4))
3718 
                 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3719 
  ""
3720 
  "shl2addx\t%0, %r1, %r2")
3721 
 
3722 
(define_insn "insn_shl3add"
3723 
  [(set (match_operand:DI 0 "register_operand" "=r")
3724 
        (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rO")
3725 
                          (const_int 8))
3726 
                 (match_operand:DI 2 "reg_or_0_operand" "rO")))]
3727 
  ""
3728 
  "shl3add\t%0, %r1, %r2")
3729 
 
3730 
(define_insn "insn_shl3addx"
3731 
  [(set (match_operand:SI 0 "register_operand" "=r")
3732 
        (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rO")
3733 
                          (const_int 8))
3734 
                 (match_operand:SI 2 "reg_or_0_operand" "rO")))]
3735 
  ""
3736 
  "shl3addx\t%0, %r1, %r2")
3737 
 
3738 
(define_insn "insn_shufflebytes"
3739 
  [(set (match_operand:DI 0 "register_operand" "=r")
3740 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3741 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
3742 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
3743 
                   UNSPEC_INSN_SHUFFLEBYTES))]
3744 
  ""
3745 
  "shufflebytes\t%0, %r2, %r3"
3746 
  [(set_attr "type" "X0")])
3747 
 
3748 
;; stores
3749 
 
3750 
(define_expand "insn_st"
3751 
  [(set (mem:DI (match_operand 0 "pointer_operand" ""))
3752 
        (match_operand:DI 1 "reg_or_0_operand" ""))]
3753 
  "")
3754 
 
3755 
(define_insn "insn_st_add"
3756 
  [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3757 
        (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3758 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3759 
   (set (mem:DI (match_dup 3))
3760 
        (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3761 
  ""
3762 
  "st_add\t%0, %r1, %2"
3763 
  [(set_attr "type" "X1")])
3764 
 
3765 
(define_expand "insn_st"
3766 
  [(set (mem:I124MODE (match_operand 0 "pointer_operand" ""))
3767 
        (match_operand:DI 1 "reg_or_0_operand" ""))]
3768 
  ""
3769 
{
3770 
  operands[1] = simplify_gen_subreg (mode, operands[1], DImode, 0);
3771 
})
3772 
 
3773 
(define_expand "insn_st_add"
3774 
  [(parallel
3775 
    [(set (match_operand:I48MODE 0 "pointer_operand" "")
3776 
          (plus:I48MODE (match_operand 3 "pointer_operand" "")
3777 
                        (match_operand 2 "s8bit_cint_operand" "")))
3778 
     (set (mem:I124MODE (match_dup 3))
3779 
          (match_operand:DI 1 "reg_or_0_operand" ""))])]
3780 
  ""
3781 
{
3782 
  operands[1] = simplify_gen_subreg (mode, operands[1],
3783 
                                     DImode, 0);
3784 
})
3785 
 
3786 
(define_insn "*insn_st_add"
3787 
  [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3788 
        (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3789 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3790 
   (set (mem:I124MODE (match_dup 3))
3791 
        (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3792 
  ""
3793 
  "st_add\t%0, %r1, %2"
3794 
  [(set_attr "type" "X1")])
3795 
 
3796 
;; non-temporal stores
3797 
 
3798 
(define_insn "insn_stnt"
3799 
  [(set (mem:DI (unspec [(match_operand 0 "pointer_operand" "rO")]
3800 
                        UNSPEC_NON_TEMPORAL))
3801 
        (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3802 
  ""
3803 
  "stnt\t%0, %r1"
3804 
  [(set_attr "type" "X1")])
3805 
 
3806 
(define_insn "insn_stnt_add"
3807 
  [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3808 
        (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3809 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3810 
   (set (mem:DI (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3811 
        (match_operand:DI 1 "reg_or_0_operand" "rO"))]
3812 
  ""
3813 
  "stnt_add\t%0, %r1, %2"
3814 
  [(set_attr "type" "X1")])
3815 
 
3816 
(define_expand "insn_stnt"
3817 
  [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "")]
3818 
                              UNSPEC_NON_TEMPORAL))
3819 
        (match_operand:DI 1 "reg_or_0_operand" ""))]
3820 
  ""
3821 
{
3822 
  operands[1] = simplify_gen_subreg (mode, operands[1], DImode, 0);
3823 
})
3824 
 
3825 
(define_insn "*insn_stnt"
3826 
  [(set (mem:I124MODE (unspec [(match_operand 0 "pointer_operand" "rO")]
3827 
                              UNSPEC_NON_TEMPORAL))
3828 
        (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3829 
  ""
3830 
  "stnt\t%0, %r1"
3831 
  [(set_attr "type" "X1")])
3832 
 
3833 
(define_expand "insn_stnt_add"
3834 
  [(parallel
3835 
    [(set (match_operand:I48MODE 0 "pointer_operand" "")
3836 
          (plus:I48MODE (match_operand 3 "pointer_operand" "")
3837 
                        (match_operand 2 "s8bit_cint_operand" "")))
3838 
     (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3839 
          (match_operand:DI 1 "reg_or_0_operand" "rO"))])]
3840 
  ""
3841 
{
3842 
  operands[1] = simplify_gen_subreg (mode, operands[1],
3843 
                                     DImode, 0);
3844 
})
3845 
 
3846 
(define_insn "*insn_stnt_add"
3847 
  [(set (match_operand:I48MODE 0 "pointer_operand" "=r")
3848 
        (plus:I48MODE (match_operand 3 "pointer_operand" "0")
3849 
                      (match_operand 2 "s8bit_cint_operand" "i")))
3850 
   (set (mem:I124MODE (unspec:I48MODE [(match_dup 3)] UNSPEC_NON_TEMPORAL))
3851 
        (match_operand:I124MODE 1 "reg_or_0_operand" "rO"))]
3852 
  ""
3853 
  "stnt_add\t%0, %r1, %2"
3854 
  [(set_attr "type" "X1")])
3855 
 
3856 
;; end stores
3857 
 
3858 
(define_insn "insn_tblidxb0"
3859 
  [(set (match_operand:DI 0 "register_operand" "=r")
3860 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3861 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3862 
                   UNSPEC_INSN_TBLIDXB0))]
3863 
  ""
3864 
  "tblidxb0\t%0, %r2"
3865 
  [(set_attr "type" "Y0")])
3866 
 
3867 
(define_insn "insn_tblidxb1"
3868 
  [(set (match_operand:DI 0 "register_operand" "=r")
3869 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3870 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3871 
                   UNSPEC_INSN_TBLIDXB1))]
3872 
  ""
3873 
  "tblidxb1\t%0, %r2"
3874 
  [(set_attr "type" "Y0")])
3875 
 
3876 
(define_insn "insn_tblidxb2"
3877 
  [(set (match_operand:DI 0 "register_operand" "=r")
3878 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3879 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3880 
                   UNSPEC_INSN_TBLIDXB2))]
3881 
  ""
3882 
  "tblidxb2\t%0, %r2"
3883 
  [(set_attr "type" "Y0")])
3884 
 
3885 
(define_insn "insn_tblidxb3"
3886 
  [(set (match_operand:DI 0 "register_operand" "=r")
3887 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
3888 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
3889 
                   UNSPEC_INSN_TBLIDXB3))]
3890 
  ""
3891 
  "tblidxb3\t%0, %r2"
3892 
  [(set_attr "type" "Y0")])
3893 
 
3894 
;; insn_v1add
3895 
;; insn_v1addi
3896 
;; insn_v1cmpeq
3897 
;; insn_v1cmpeqi
3898 
;; insn_v1cmplts
3899 
;; insn_v1cmpltsi
3900 
;; insn_v1cmpltu
3901 
;; insn_v1cmpltui
3902 
;; insn_v1maxu
3903 
;; insn_v1maxui
3904 
;; insn_v1minu
3905 
;; insn_v1minui
3906 
(define_insn "v8qi3"
3907 
  [(set (match_operand:V8QI 0 "register_operand" "=r,r")
3908 
        (v1op_immed:V8QI
3909 
         (match_operand:V8QI 1 "reg_or_0_operand" "rO,rO")
3910 
         (match_operand:V8QI 2 "reg_or_v8s8bit_operand" "W,rO")))]
3911 
  ""
3912 
  "@
3913 
   v1i\t%0, %r1, %j2
3914 
   v1\t%0, %r1, %r2"
3915 
  [(set_attr "type" ",")])
3916 
 
3917 
(define_expand "insn_v1"
3918 
  [(set (match_operand:DI 0 "register_operand" "")
3919 
        (v1op_immed:V8QI
3920 
         (match_operand:DI 1 "reg_or_0_operand" "")
3921 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
3922 
  ""
3923 
{
3924 
  tilegx_expand_builtin_vector_binop (gen_v8qi3, V8QImode, operands[0],
3925 
                                      V8QImode, operands[1], operands[2], true);
3926 
  DONE;
3927 
})
3928 
 
3929 
(define_expand "insn_v1i"
3930 
  [(set (match_operand:DI 0 "register_operand" "")
3931 
        (v1op_immed:V8QI
3932 
         (match_operand:DI 1 "reg_or_0_operand" "")
3933 
         (match_operand:DI 2 "s8bit_cint_operand" "")))]
3934 
  ""
3935 
{
3936 
  /* Tile out immediate and expand to general case. */
3937 
  rtx n = tilegx_simd_int (operands[2], QImode);
3938 
  tilegx_expand_builtin_vector_binop (gen_v8qi3, V8QImode, operands[0],
3939 
                                      V8QImode, operands[1], n, true);
3940 
  DONE;
3941 
})
3942 
 
3943 
;; insn_v1shl
3944 
;; insn_v1shli
3945 
;; insn_v1shrs
3946 
;; insn_v1shrsi
3947 
;; insn_v1shru
3948 
;; insn_v1shrui
3949 
(define_insn "v8qi3"
3950 
  [(set (match_operand:V8QI 0 "register_operand" "=r,r")
3951 
        (any_shift:V8QI
3952 
         (match_operand:V8QI 1 "reg_or_0_operand" "rO,rO")
3953 
         (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
3954 
  ""
3955 
  "@
3956 
   v1i\t%0, %r1, %2
3957 
   v1\t%0, %r1, %r2"
3958 
  [(set_attr "type" ",")])
3959 
 
3960 
(define_expand "insn_v1"
3961 
  [(set (match_operand:DI 0 "register_operand" "")
3962 
        (any_shift:V8QI
3963 
         (match_operand:DI 1 "reg_or_0_operand" "")
3964 
         (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
3965 
  ""
3966 
{
3967 
  tilegx_expand_builtin_vector_binop (gen_v8qi3, V8QImode, operands[0],
3968 
                                      V8QImode, operands[1], operands[2], false);
3969 
  DONE;
3970 
})
3971 
 
3972 
;; insn_v2add
3973 
;; insn_v2addi
3974 
;; insn_v2maxs
3975 
;; insn_v2maxsi
3976 
;; insn_v2mins
3977 
;; insn_v2minsi
3978 
;; insn_v2cmpeq
3979 
;; insn_v2cmpeqi
3980 
;; insn_v2cmplts
3981 
;; insn_v2cmpltsi
3982 
;; insn_v2cmpltu
3983 
;; insn_v2cmpltui
3984 
(define_insn "v4hi3"
3985 
  [(set (match_operand:V4HI 0 "register_operand" "=r,r")
3986 
        (v2op_immed:V4HI
3987 
         (match_operand:V4HI 1 "reg_or_0_operand" "rO,rO")
3988 
         (match_operand:V4HI 2 "reg_or_v4s8bit_operand" "Y,rO")))]
3989 
  ""
3990 
  "@
3991 
   v2i\t%0, %r1, %j2
3992 
   v2\t%0, %r1, %r2"
3993 
  [(set_attr "type" ",")])
3994 
 
3995 
(define_expand "insn_v2"
3996 
  [(set (match_operand:DI 0 "register_operand" "")
3997 
        (v2op_immed:V4HI
3998 
         (match_operand:DI 1 "reg_or_0_operand" "")
3999 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4000 
  ""
4001 
{
4002 
  tilegx_expand_builtin_vector_binop (gen_v4hi3, V4HImode, operands[0],
4003 
                                      V4HImode, operands[1], operands[2], true);
4004 
  DONE;
4005 
})
4006 
 
4007 
(define_expand "insn_v2i"
4008 
  [(set (match_operand:DI 0 "register_operand" "")
4009 
        (v2op_immed:V4HI
4010 
         (match_operand:DI 1 "reg_or_0_operand" "")
4011 
         (match_operand:DI 2 "s8bit_cint_operand" "")))]
4012 
  ""
4013 
{
4014 
  /* Tile out immediate and expand to general case. */
4015 
  rtx n = tilegx_simd_int (operands[2], HImode);
4016 
  tilegx_expand_builtin_vector_binop (gen_v4hi3, V4HImode, operands[0],
4017 
                                      V4HImode, operands[1], n, true);
4018 
  DONE;
4019 
})
4020 
 
4021 
;; insn_v2shl
4022 
;; insn_v2shli
4023 
;; insn_v2shrs
4024 
;; insn_v2shrsi
4025 
;; insn_v2shru
4026 
;; insn_v2shrui
4027 
(define_insn "v4hi3"
4028 
  [(set (match_operand:V4HI 0 "register_operand" "=r,r")
4029 
        (any_shift:V4HI
4030 
         (match_operand:V4HI 1 "reg_or_0_operand" "rO,rO")
4031 
         (match_operand:DI 2 "reg_or_u5bit_operand" "I,rO")))]
4032 
  ""
4033 
  "@
4034 
   v2i\t%0, %r1, %2
4035 
   v2\t%0, %r1, %r2"
4036 
  [(set_attr "type" ",")])
4037 
 
4038 
(define_expand "insn_v2"
4039 
  [(set (match_operand:DI 0 "register_operand" "")
4040 
        (any_shift:V4HI
4041 
         (match_operand:DI 1 "reg_or_0_operand" "")
4042 
         (match_operand:DI 2 "reg_or_u5bit_operand" "")))]
4043 
  ""
4044 
{
4045 
  tilegx_expand_builtin_vector_binop (gen_v4hi3, V4HImode, operands[0],
4046 
                                      V4HImode, operands[1], operands[2], false);
4047 
  DONE;
4048 
})
4049 
 
4050 
;; insn_v1adduc
4051 
;; insn_v1subuc
4052 
;; insn_v1sub
4053 
;; insn_v1cmpne
4054 
;; insn_v1cmples
4055 
;; insn_v1cmpleu
4056 
;; insn_v1multu
4057 
(define_insn "v8qi3"
4058 
  [(set (match_operand:V8QI 0 "register_operand" "=r")
4059 
        (v1op:V8QI
4060 
         (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4061 
         (match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
4062 
  ""
4063 
  "v1\t%0, %r1, %r2"
4064 
  [(set_attr "type" "")])
4065 
 
4066 
(define_expand "insn_v1"
4067 
  [(set (match_operand:DI 0 "register_operand" "")
4068 
        (v1op:V8QI
4069 
         (match_operand:DI 1 "reg_or_0_operand" "")
4070 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4071 
  ""
4072 
{
4073 
  tilegx_expand_builtin_vector_binop (gen_v8qi3, V8QImode, operands[0],
4074 
                                      V8QImode, operands[1], operands[2], true);
4075 
  DONE;
4076 
})
4077 
 
4078 
;; insn_v2addsc
4079 
;; insn_v2subsc
4080 
;; insn_v2sub
4081 
;; insn_v2cmpne
4082 
;; insn_v2cmples
4083 
;; insn_v2cmpleu
4084 
(define_insn "v4hi3"
4085 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4086 
        (v2op:V4HI
4087 
         (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4088 
         (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4089 
  ""
4090 
  "v2\t%0, %r1, %r2"
4091 
  [(set_attr "type" "")])
4092 
 
4093 
(define_expand "insn_v2"
4094 
  [(set (match_operand:DI 0 "register_operand" "")
4095 
        (v2op:V4HI
4096 
         (match_operand:DI 1 "reg_or_0_operand" "")
4097 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4098 
  ""
4099 
{
4100 
  tilegx_expand_builtin_vector_binop (gen_v4hi3, V4HImode, operands[0],
4101 
                                      V4HImode, operands[1], operands[2], true);
4102 
  DONE;
4103 
})
4104 
 
4105 
;; insn_v2mults
4106 
(define_insn "mulv4hi3"
4107 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4108 
        (mult:V4HI
4109 
         (match_operand:V4HI 1 "reg_or_0_operand" "%rO")
4110 
         (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
4111 
  ""
4112 
  "v2mults\t%0, %r1, %r2"
4113 
  [(set_attr "type" "X0_2cycle")])
4114 
 
4115 
(define_expand "insn_v2mults"
4116 
  [(set (match_operand:DI 0 "register_operand" "")
4117 
        (mult:V4HI
4118 
         (match_operand:DI 1 "reg_or_0_operand" "")
4119 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4120 
  ""
4121 
{
4122 
  tilegx_expand_builtin_vector_binop (gen_mulv4hi3, V4HImode, operands[0],
4123 
                                      V4HImode, operands[1], operands[2], true);
4124 
  DONE;
4125 
})
4126 
 
4127 
;; insn_v2shlsc
4128 
(define_insn "v4hi3"
4129 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4130 
        (v2shift:V4HI
4131 
         (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4132 
         (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4133 
  ""
4134 
  "v2\t%0, %r1, %r2"
4135 
  [(set_attr "type" "")])
4136 
 
4137 
(define_expand "insn_v2"
4138 
  [(set (match_operand:DI 0 "register_operand" "")
4139 
        (v2shift:V4HI
4140 
         (match_operand:DI 1 "reg_or_0_operand" "")
4141 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4142 
  ""
4143 
{
4144 
  tilegx_expand_builtin_vector_binop (gen_v4hi3, V4HImode, operands[0],
4145 
                                      V4HImode, operands[1], operands[2], false);
4146 
  DONE;
4147 
})
4148 
 
4149 
;; insn_v4addsc
4150 
;; insn_v4subsc
4151 
;; insn_v4add
4152 
;; insn_v4sub
4153 
(define_insn "v2si3"
4154 
  [(set (match_operand:V2SI 0 "register_operand" "=r")
4155 
        (v4op:V2SI
4156 
         (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4157 
         (match_operand:V2SI 2 "reg_or_0_operand" "rO")))]
4158 
  ""
4159 
  "v4\t%0, %r1, %r2"
4160 
  [(set_attr "type" "")])
4161 
 
4162 
(define_expand "insn_v4"
4163 
  [(set (match_operand:DI 0 "register_operand" "")
4164 
        (v4op:V2SI
4165 
         (match_operand:DI 1 "reg_or_0_operand" "")
4166 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4167 
  ""
4168 
{
4169 
  tilegx_expand_builtin_vector_binop (gen_v2si3, V2SImode, operands[0],
4170 
                                      V2SImode, operands[1], operands[2], true);
4171 
  DONE;
4172 
})
4173 
 
4174 
;; insn_v4shl
4175 
;; insn_v4shrs
4176 
;; insn_v4shru
4177 
;; insn_v4shlsc
4178 
(define_insn "v2si3"
4179 
  [(set (match_operand:V2SI 0 "register_operand" "=r")
4180 
        (v4shift:V2SI
4181 
         (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4182 
         (match_operand:DI 2 "reg_or_0_operand" "rO")))]
4183 
  ""
4184 
  "v4\t%0, %r1, %r2"
4185 
  [(set_attr "type" "")])
4186 
 
4187 
(define_expand "insn_v4"
4188 
  [(set (match_operand:DI 0 "register_operand" "")
4189 
        (v4shift:V2SI
4190 
         (match_operand:DI 1 "reg_or_0_operand" "")
4191 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4192 
  ""
4193 
{
4194 
  tilegx_expand_builtin_vector_binop (gen_v2si3, V2SImode, operands[0],
4195 
                                      V2SImode, operands[1], operands[2], false);
4196 
  DONE;
4197 
})
4198 
 
4199 
;; insn_v1int_h
4200 
;;    {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4201 
;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4202 
;; => {A7,B7,A6,B6,A5,B5,A4,B4}
4203 
(define_insn "vec_interleave_highv8qi"
4204 
  [(set (match_operand:V8QI 0 "register_operand" "=r")
4205 
        (vec_select:V8QI
4206 
         (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4207 
                           (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4208 
         (parallel [(const_int 4) (const_int 12)
4209 
                    (const_int 5) (const_int 13)
4210 
                    (const_int 6) (const_int 14)
4211 
                    (const_int 7) (const_int 15)])))]
4212 
  ""
4213 
  "v1int_h\t%0, %r2, %r1"
4214 
  [(set_attr "type" "X01")])
4215 
 
4216 
(define_expand "insn_v1int_h"
4217 
  [(match_operand:DI 0 "register_operand" "")
4218 
   (match_operand:DI 1 "reg_or_0_operand" "")
4219 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4220 
  ""
4221 
{
4222 
  /* Our instruction interleaves opposite of the way vec_interleave
4223 
     works, so we need to reverse the source operands.  */
4224 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv8qi, V8QImode,
4225 
                                      operands[0], V8QImode, operands[2],
4226 
                                      operands[1], true);
4227 
  DONE;
4228 
})
4229 
 
4230 
;; insn_v1int_l
4231 
;;    {B7,B6,B5,B4,B3,B2,B1,B0} {A7,A6,A5,A4,A3,A2,A1,A0}
4232 
;; => {A7,A6,A5,A4,A3,A2,A1,A0,B7,B6,B5,B4,B3,B2,B1,B0}
4233 
;; => {A3,B3,A2,B2,A1,B1,A0,B0}
4234 
(define_insn "vec_interleave_lowv8qi"
4235 
  [(set (match_operand:V8QI 0 "register_operand" "=r")
4236 
        (vec_select:V8QI
4237 
         (vec_concat:V16QI (match_operand:V8QI 1 "reg_or_0_operand" "rO")
4238 
                           (match_operand:V8QI 2 "reg_or_0_operand" "rO"))
4239 
         (parallel [(const_int 0) (const_int 8)
4240 
                    (const_int 1) (const_int 9)
4241 
                    (const_int 2) (const_int 10)
4242 
                    (const_int 3) (const_int 11)])))]
4243 
  ""
4244 
  "v1int_l\t%0, %r2, %r1"
4245 
  [(set_attr "type" "X01")])
4246 
 
4247 
(define_expand "insn_v1int_l"
4248 
  [(match_operand:DI 0 "register_operand" "")
4249 
   (match_operand:DI 1 "reg_or_0_operand" "")
4250 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4251 
  ""
4252 
{
4253 
  /* Our instruction interleaves opposite of the way vec_interleave
4254 
     works, so we need to reverse the source operands.  */
4255 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv8qi, V8QImode,
4256 
                                      operands[0], V8QImode, operands[2],
4257 
                                      operands[1], true);
4258 
  DONE;
4259 
})
4260 
 
4261 
;; insn_v2int_h
4262 
;;    {B3,B2,B1,B0} {A3,A2,A1,A0}
4263 
;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4264 
;; => {A3,B3,A2,B2}
4265 
(define_insn "vec_interleave_highv4hi"
4266 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4267 
        (vec_select:V4HI
4268 
         (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4269 
                          (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4270 
         (parallel [(const_int 2) (const_int 6)
4271 
                    (const_int 3) (const_int 7)])))]
4272 
  ""
4273 
  "v2int_h\t%0, %r2, %r1"
4274 
  [(set_attr "type" "X01")])
4275 
 
4276 
(define_expand "insn_v2int_h"
4277 
  [(match_operand:DI 0 "register_operand" "")
4278 
   (match_operand:DI 1 "reg_or_0_operand" "")
4279 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4280 
  ""
4281 
{
4282 
  /* Our instruction interleaves opposite of the way vec_interleave
4283 
     works, so we need to reverse the source operands.  */
4284 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv4hi, V4HImode,
4285 
                                      operands[0], V4HImode, operands[2],
4286 
                                      operands[1], true);
4287 
  DONE;
4288 
})
4289 
 
4290 
;; insn_v2int_l
4291 
;;    {B3,B2,B1,B0} {A3,A2,A1,A0}
4292 
;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4293 
;; => {A1,B1,A0,B0}
4294 
(define_insn "vec_interleave_lowv4hi"
4295 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4296 
        (vec_select:V4HI
4297 
         (vec_concat:V8HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4298 
                          (match_operand:V4HI 2 "reg_or_0_operand" "rO"))
4299 
         (parallel [(const_int 0) (const_int 4)
4300 
                    (const_int 1) (const_int 5)])))]
4301 
  ""
4302 
  "v2int_l\t%0, %r2, %r1"
4303 
  [(set_attr "type" "X01")])
4304 
 
4305 
(define_expand "insn_v2int_l"
4306 
  [(match_operand:DI 0 "register_operand" "")
4307 
   (match_operand:DI 1 "reg_or_0_operand" "")
4308 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4309 
  ""
4310 
{
4311 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv4hi, V4HImode,
4312 
                                      operands[0], V4HImode, operands[2],
4313 
                                      operands[1], true);
4314 
  DONE;
4315 
})
4316 
 
4317 
;; insn_v4int_h
4318 
;;    {B1,B0} {A1,A0}
4319 
;; => {A1,A0,B1,B0}
4320 
;; => {A1,B1}
4321 
(define_insn "vec_interleave_highv2si"
4322 
  [(set (match_operand:V2SI 0 "register_operand" "=r")
4323 
        (vec_select:V2SI
4324 
         (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4325 
                          (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4326 
         (parallel [(const_int 1) (const_int 3)])))]
4327 
  ""
4328 
  "v4int_h\t%0, %r2, %r1"
4329 
  [(set_attr "type" "X01")])
4330 
 
4331 
(define_expand "insn_v4int_h"
4332 
  [(match_operand:DI 0 "register_operand" "")
4333 
   (match_operand:DI 1 "reg_or_0_operand" "")
4334 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4335 
  ""
4336 
{
4337 
  /* Our instruction interleaves opposite of the way vec_interleave
4338 
     works, so we need to reverse the source operands.  */
4339 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_highv2si, V2SImode,
4340 
                                      operands[0], V2SImode, operands[2],
4341 
                                      operands[1], true);
4342 
  DONE;
4343 
})
4344 
 
4345 
;; insn_v4int_l
4346 
;;    {B1,B0} {A1,A0}
4347 
;; => {A1,A0,B1,B0}
4348 
;; => {A0,B0}
4349 
(define_insn "vec_interleave_lowv2si"
4350 
  [(set (match_operand:V2SI 0 "register_operand" "=r")
4351 
        (vec_select:V2SI
4352 
         (vec_concat:V4SI (match_operand:V2SI 1 "reg_or_0_operand" "rO")
4353 
                          (match_operand:V2SI 2 "reg_or_0_operand" "rO"))
4354 
         (parallel [(const_int 0) (const_int 2)])))]
4355 
  ""
4356 
  "v4int_l\t%0, %r2, %r1"
4357 
  [(set_attr "type" "X01")])
4358 
 
4359 
(define_expand "insn_v4int_l"
4360 
  [(match_operand:DI 0 "register_operand" "")
4361 
   (match_operand:DI 1 "reg_or_0_operand" "")
4362 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4363 
  ""
4364 
{
4365 
  /* Our instruction interleaves opposite of the way vec_interleave
4366 
     works, so we need to reverse the source operands.  */
4367 
  tilegx_expand_builtin_vector_binop (gen_vec_interleave_lowv2si, V2SImode,
4368 
                                      operands[0], V2SImode, operands[2],
4369 
                                      operands[1], true);
4370 
  DONE;
4371 
})
4372 
 
4373 
;; insn_v1mnz
4374 
;; insn_v1mz
4375 
;; insn_v2mnz
4376 
;; insn_v2mz
4377 
(define_insn "insn_mnz_"
4378 
  [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
4379 
        (if_then_else:VEC48MODE
4380 
         (ne:VEC48MODE
4381 
          (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
4382 
          (const_int 0))
4383 
         (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")
4384 
         (const_int 0)))]
4385 
  ""
4386 
  "vmnz\t%0, %r1, %r2"
4387 
  [(set_attr "type" "X01")])
4388 
 
4389 
(define_expand "insn_vmnz"
4390 
  [(set (match_operand:DI 0 "register_operand" "")
4391 
        (if_then_else:VEC48MODE
4392 
         (ne:VEC48MODE
4393 
          (match_operand:DI 1 "reg_or_0_operand" "")
4394 
          (const_int 0))
4395 
         (match_operand:DI 2 "reg_or_0_operand" "")
4396 
         (const_int 0)))]
4397 
  ""
4398 
{
4399 
  tilegx_expand_builtin_vector_binop (gen_insn_mnz_, mode,
4400 
                                      operands[0], mode, operands[1],
4401 
                                      operands[2], true);
4402 
  DONE;
4403 
})
4404 
 
4405 
(define_insn "insn_mz_"
4406 
  [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
4407 
        (if_then_else:VEC48MODE
4408 
         (ne:VEC48MODE
4409 
          (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
4410 
          (const_int 0))
4411 
         (const_int 0)
4412 
         (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))]
4413 
  ""
4414 
  "vmz\t%0, %r1, %r2"
4415 
  [(set_attr "type" "X01")])
4416 
(define_expand "insn_vmz"
4417 
  [(set (match_operand:DI 0 "register_operand" "")
4418 
        (if_then_else:VEC48MODE
4419 
         (ne:VEC48MODE
4420 
          (match_operand:DI 1 "reg_or_0_operand" "")
4421 
          (const_int 0))
4422 
         (const_int 0)
4423 
         (match_operand:DI 2 "reg_or_0_operand" "")))]
4424 
  ""
4425 
{
4426 
  tilegx_expand_builtin_vector_binop (gen_insn_mz_, mode,
4427 
                                      operands[0], mode, operands[1],
4428 
                                      operands[2], true);
4429 
  DONE;
4430 
})
4431 
 
4432 
;; insn_v1mulu
4433 
(define_insn "vec_widen_umult_lo_v8qi"
4434 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4435 
        (mult:V4HI
4436 
         (zero_extend:V4HI
4437 
          (vec_select:V4QI
4438 
           (match_operand:V8QI 1 "register_operand" "r")
4439 
           (parallel [(const_int 0) (const_int 1)
4440 
                      (const_int 2) (const_int 3)])))
4441 
         (zero_extend:V4HI
4442 
          (vec_select:V4QI
4443 
           (match_operand:V8QI 2 "register_operand" "r")
4444 
           (parallel [(const_int 0) (const_int 1)
4445 
                      (const_int 2) (const_int 3)])))))]
4446 
  ""
4447 
  "v1mulu\t%0, %r1, %r2"
4448 
  [(set_attr "type" "X0_2cycle")])
4449 
 
4450 
(define_expand "insn_v1mulu"
4451 
  [(match_operand:DI 0 "register_operand" "")
4452 
   (match_operand:DI 1 "reg_or_0_operand" "")
4453 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4454 
  ""
4455 
{
4456 
  tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
4457 
                                      operands[0], V8QImode, operands[1],
4458 
                                      operands[2], true);
4459 
  DONE;
4460 
})
4461 
 
4462 
;; insn_v1mulus
4463 
(define_insn "vec_widen_usmult_lo_v8qi"
4464 
  [(set (match_operand:V4HI 0 "register_operand" "=r")
4465 
        (mult:V4HI
4466 
         (zero_extend:V4HI
4467 
          (vec_select:V4QI
4468 
           (match_operand:V8QI 1 "register_operand" "r")
4469 
           (parallel [(const_int 0) (const_int 1)
4470 
                      (const_int 2) (const_int 3)])))
4471 
         (sign_extend:V4HI
4472 
          (vec_select:V4QI
4473 
           (match_operand:V8QI 2 "register_operand" "r")
4474 
           (parallel [(const_int 0) (const_int 1)
4475 
                      (const_int 2) (const_int 3)])))))]
4476 
  ""
4477 
  "v1mulus\t%0, %r1, %r2"
4478 
  [(set_attr "type" "X0_2cycle")])
4479 
 
4480 
(define_expand "insn_v1mulus"
4481 
  [(match_operand:DI 0 "register_operand" "")
4482 
   (match_operand:DI 1 "reg_or_0_operand" "")
4483 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4484 
  ""
4485 
{
4486 
  tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
4487 
                                      operands[0], V8QImode, operands[1],
4488 
                                      operands[2], true);
4489 
  DONE;
4490 
})
4491 
 
4492 
;; insn_v2muls
4493 
(define_insn "vec_widen_smult_lo_v4qi"
4494 
  [(set (match_operand:V2SI 0 "register_operand" "=r")
4495 
        (mult:V2SI
4496 
         (sign_extend:V2SI
4497 
          (vec_select:V2HI
4498 
           (match_operand:V4HI 1 "register_operand" "r")
4499 
           (parallel [(const_int 0) (const_int 1)])))
4500 
         (sign_extend:V2SI
4501 
          (vec_select:V2HI
4502 
           (match_operand:V4HI 2 "register_operand" "r")
4503 
           (parallel [(const_int 0) (const_int 1)])))))]
4504 
  ""
4505 
  "v2muls\t%0, %r1, %r2"
4506 
  [(set_attr "type" "X0_2cycle")])
4507 
 
4508 
(define_expand "insn_v2muls"
4509 
  [(match_operand:DI 0 "register_operand" "")
4510 
   (match_operand:DI 1 "reg_or_0_operand" "")
4511 
   (match_operand:DI 2 "reg_or_0_operand" "")]
4512 
  ""
4513 
{
4514 
  tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,
4515 
                                      operands[0], V4HImode, operands[1],
4516 
                                      operands[2], true);
4517 
  DONE;
4518 
})
4519 
 
4520 
;; v2packl
4521 
;; v2packuc
4522 
;;    {B3,B2,B1,B0} {A3,A2,A1,A0}
4523 
;; => {A3,A2,A1,A0,B3,B2,B1,B0}
4524 
(define_insn "vec_pack__v4hi"
4525 
  [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r")
4526 
        (vec_concat:V8QI
4527 
         (v2pack:V4QI (match_operand:V4HI 1 "reg_or_0_operand" "rO"))
4528 
         (v2pack:V4QI (match_operand:V4HI 2 "reg_or_0_operand" "rO"))))]
4529 
  ""
4530 
  "v2\t%0, %r2, %r1"
4531 
  [(set_attr "type" "X01")])
4532 
 
4533 
(define_expand "insn_v2"
4534 
  [(set (match_operand:DI 0 "reg_or_0_operand" "")
4535 
        (vec_concat:V8QI
4536 
         (v2pack:V4QI (match_operand:DI 2 "reg_or_0_operand" ""))
4537 
         (v2pack:V4QI (match_operand:DI 1 "reg_or_0_operand" ""))))]
4538 
  ""
4539 
{
4540 
  /* Our instruction concats opposite of the way vec_pack works, so we
4541 
     need to reverse the source operands.  */
4542 
  tilegx_expand_builtin_vector_binop (gen_vec_pack__v4hi,
4543 
                                      V8QImode, operands[0], V4HImode,
4544 
                                      operands[2], operands[1], true);
4545 
  DONE;
4546 
})
4547 
 
4548 
;; v2packh
4549 
;;    {B3,B2,B1,B0} {A3,A2,A1,A0}
4550 
;; => {A3_hi,A2_hi,A1_hi,A0_hi,B3_hi,B2_hi,B1_hi,B0_hi}
4551 
(define_insn "vec_pack_hipart_v4hi"
4552 
  [(set (match_operand:V8QI 0 "reg_or_0_operand" "=r")
4553 
        (vec_concat:V8QI
4554 
         (truncate:V4QI
4555 
          (ashiftrt:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rO")
4556 
                         (const_int 8)))
4557 
         (truncate:V4QI
4558 
          (ashiftrt:V4HI (match_operand:V4HI 2 "reg_or_0_operand" "rO")
4559 
                         (const_int 8)))))]
4560 
  ""
4561 
  "v2packh\t%0, %r2, %r1"
4562 
  [(set_attr "type" "X01")])
4563 
 
4564 
(define_expand "insn_v2packh"
4565 
  [(set (match_operand:DI 0 "reg_or_0_operand" "")
4566 
        (vec_concat:V8QI
4567 
         (truncate:V4QI
4568 
          (ashiftrt:V4HI (match_operand:DI 2 "reg_or_0_operand" "")
4569 
                         (const_int 8)))
4570 
         (truncate:V4QI
4571 
          (ashiftrt:V4HI (match_operand:DI 1 "reg_or_0_operand" "")
4572 
                         (const_int 8)))))]
4573 
  ""
4574 
{
4575 
  /* Our instruction concats opposite of the way vec_pack works, so we
4576 
     need to reverse the source operands.  */
4577 
  tilegx_expand_builtin_vector_binop (gen_vec_pack_hipart_v4hi, V8QImode,
4578 
                                      operands[0], V4HImode, operands[2],
4579 
                                      operands[1], true);
4580 
  DONE;
4581 
})
4582 
 
4583 
;; v4packsc
4584 
;;    {B1,B0} {A1,A0}
4585 
;; => {A1,A0,B1,B0}
4586 
(define_insn "vec_pack_ssat_v2si"
4587 
  [(set (match_operand:V4HI 0 "reg_or_0_operand" "=r")
4588 
        (vec_concat:V4HI
4589 
         (us_truncate:V2HI (match_operand:V2SI 1 "reg_or_0_operand" "rO"))
4590 
         (us_truncate:V2HI (match_operand:V2SI 2 "reg_or_0_operand" "rO"))))]
4591 
  ""
4592 
  "v4packsc\t%0, %r2, %r1"
4593 
  [(set_attr "type" "X01")])
4594 
 
4595 
(define_expand "insn_v4packsc"
4596 
  [(set (match_operand:DI 0 "reg_or_0_operand" "")
4597 
        (vec_concat:V4HI
4598 
         (us_truncate:V2HI (match_operand:DI 2 "reg_or_0_operand" ""))
4599 
         (us_truncate:V2HI (match_operand:DI 1 "reg_or_0_operand" ""))))]
4600 
  ""
4601 
{
4602 
  /* Our instruction concats opposite of the way vec_pack works, so we
4603 
     need to reverse the source operands.  */
4604 
  tilegx_expand_builtin_vector_binop (gen_vec_pack_ssat_v2si, V4HImode,
4605 
                                      operands[0], V2SImode, operands[2],
4606 
                                      operands[1], true);
4607 
  DONE;
4608 
})
4609 
 
4610 
;; Rest of the vector intrinsics
4611 
(define_insn "insn_v1adiffu"
4612 
  [(set (match_operand:DI 0 "register_operand" "=r")
4613 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4614 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4615 
                   UNSPEC_INSN_V1ADIFFU))]
4616 
  ""
4617 
  "v1adiffu\t%0, %r1, %r2"
4618 
  [(set_attr "type" "X0_2cycle")])
4619 
 
4620 
(define_insn "insn_v1avgu"
4621 
  [(set (match_operand:DI 0 "register_operand" "=r")
4622 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4623 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4624 
                   UNSPEC_INSN_V1AVGU))]
4625 
  ""
4626 
  "v1avgu\t%0, %r1, %r2"
4627 
  [(set_attr "type" "X0")])
4628 
 
4629 
(define_insn "insn_v1ddotpu"
4630 
  [(set (match_operand:DI 0 "register_operand" "=r")
4631 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4632 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4633 
                   UNSPEC_INSN_V1DDOTPU))]
4634 
  ""
4635 
  "v1ddotpu\t%0, %r1, %r2"
4636 
  [(set_attr "type" "X0_2cycle")])
4637 
 
4638 
(define_insn "insn_v1ddotpua"
4639 
  [(set (match_operand:DI 0 "register_operand" "=r")
4640 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4641 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4642 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4643 
                   UNSPEC_INSN_V1DDOTPUA))]
4644 
  ""
4645 
  "v1ddotpua\t%0, %r2, %r3"
4646 
  [(set_attr "type" "X0_2cycle")])
4647 
 
4648 
(define_insn "insn_v1ddotpus"
4649 
  [(set (match_operand:DI 0 "register_operand" "=r")
4650 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4651 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4652 
                   UNSPEC_INSN_V1DDOTPUS))]
4653 
  ""
4654 
  "v1ddotpus\t%0, %r1, %r2"
4655 
  [(set_attr "type" "X0_2cycle")])
4656 
 
4657 
(define_insn "insn_v1ddotpusa"
4658 
  [(set (match_operand:DI 0 "register_operand" "=r")
4659 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4660 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4661 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4662 
                   UNSPEC_INSN_V1DDOTPUSA))]
4663 
  ""
4664 
  "v1ddotpusa\t%0, %r2, %r3"
4665 
  [(set_attr "type" "X0_2cycle")])
4666 
 
4667 
(define_insn "insn_v1dotp"
4668 
  [(set (match_operand:DI 0 "register_operand" "=r")
4669 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4670 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4671 
                   UNSPEC_INSN_V1DOTP))]
4672 
  ""
4673 
  "v1dotp\t%0, %r1, %r2"
4674 
  [(set_attr "type" "X0_2cycle")])
4675 
 
4676 
(define_insn "insn_v1dotpa"
4677 
  [(set (match_operand:DI 0 "register_operand" "=r")
4678 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4679 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4680 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4681 
                   UNSPEC_INSN_V1DOTPA))]
4682 
  ""
4683 
  "v1dotpa\t%0, %r2, %r3"
4684 
  [(set_attr "type" "X0_2cycle")])
4685 
 
4686 
(define_insn "insn_v1dotpu"
4687 
  [(set (match_operand:DI 0 "register_operand" "=r")
4688 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4689 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4690 
                   UNSPEC_INSN_V1DOTPU))]
4691 
  ""
4692 
  "v1dotpu\t%0, %r1, %r2"
4693 
  [(set_attr "type" "X0_2cycle")])
4694 
 
4695 
(define_insn "insn_v1dotpua"
4696 
  [(set (match_operand:DI 0 "register_operand" "=r")
4697 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4698 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4699 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4700 
                   UNSPEC_INSN_V1DOTPUA))]
4701 
  ""
4702 
  "v1dotpua\t%0, %r2, %r3"
4703 
  [(set_attr "type" "X0_2cycle")])
4704 
 
4705 
(define_insn "insn_v1dotpus"
4706 
  [(set (match_operand:DI 0 "register_operand" "=r")
4707 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4708 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4709 
                   UNSPEC_INSN_V1DOTPUS))]
4710 
  ""
4711 
  "v1dotpus\t%0, %r1, %r2"
4712 
  [(set_attr "type" "X0_2cycle")])
4713 
 
4714 
(define_insn "insn_v1dotpusa"
4715 
  [(set (match_operand:DI 0 "register_operand" "=r")
4716 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4717 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4718 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4719 
                   UNSPEC_INSN_V1DOTPUSA))]
4720 
  ""
4721 
  "v1dotpusa\t%0, %r2, %r3"
4722 
  [(set_attr "type" "X0_2cycle")])
4723 
 
4724 
(define_insn "insn_v1sadau"
4725 
  [(set (match_operand:DI 0 "register_operand" "=r")
4726 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4727 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4728 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4729 
                   UNSPEC_INSN_V1SADAU))]
4730 
  ""
4731 
  "v1sadau\t%0, %r2, %r3"
4732 
  [(set_attr "type" "X0_2cycle")])
4733 
 
4734 
(define_insn "insn_v1sadu"
4735 
  [(set (match_operand:DI 0 "register_operand" "=r")
4736 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4737 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4738 
                   UNSPEC_INSN_V1SADU))]
4739 
  ""
4740 
  "v1sadu\t%0, %r1, %r2"
4741 
  [(set_attr "type" "X0_2cycle")])
4742 
 
4743 
(define_insn "*insn_v1sadu"
4744 
  [(set (match_operand:SI 0 "register_operand" "=r")
4745 
        (truncate:SI
4746 
         (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4747 
                     (match_operand:DI 2 "reg_or_0_operand" "rO")]
4748 
                    UNSPEC_INSN_V1SADU)))]
4749 
   ""
4750 
  "v1sadu\t%0, %r1, %r2"
4751 
  [(set_attr "type" "X0_2cycle")])
4752 
 
4753 
(define_insn "insn_v2adiffs"
4754 
  [(set (match_operand:DI 0 "register_operand" "=r")
4755 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4756 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4757 
                   UNSPEC_INSN_V2ADIFFS))]
4758 
  ""
4759 
  "v2adiffs\t%0, %r1, %r2"
4760 
  [(set_attr "type" "X0_2cycle")])
4761 
 
4762 
(define_insn "insn_v2avgs"
4763 
  [(set (match_operand:DI 0 "register_operand" "=r")
4764 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4765 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4766 
                   UNSPEC_INSN_V2AVGS))]
4767 
  ""
4768 
  "v2avgs\t%0, %r1, %r2"
4769 
  [(set_attr "type" "X0")])
4770 
 
4771 
(define_insn "insn_v2dotp"
4772 
  [(set (match_operand:DI 0 "register_operand" "=r")
4773 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4774 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4775 
                   UNSPEC_INSN_V2DOTP))]
4776 
  ""
4777 
  "v2dotp\t%0, %r1, %r2"
4778 
  [(set_attr "type" "X0_2cycle")])
4779 
 
4780 
(define_insn "insn_v2dotpa"
4781 
  [(set (match_operand:DI 0 "register_operand" "=r")
4782 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4783 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4784 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4785 
                   UNSPEC_INSN_V2DOTPA))]
4786 
  ""
4787 
  "v2dotpa\t%0, %r2, %r3"
4788 
  [(set_attr "type" "X0_2cycle")])
4789 
 
4790 
(define_insn "insn_v2mulfsc"
4791 
  [(set (match_operand:DI 0 "register_operand" "=r")
4792 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4793 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4794 
                   UNSPEC_INSN_V2MULFSC))]
4795 
  ""
4796 
  "v2mulfsc\t%0, %r1, %r2"
4797 
  [(set_attr "type" "X0_2cycle")])
4798 
 
4799 
(define_insn "insn_v2sadas"
4800 
  [(set (match_operand:DI 0 "register_operand" "=r")
4801 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4802 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4803 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4804 
                   UNSPEC_INSN_V2SADAS))]
4805 
  ""
4806 
  "v2sadas\t%0, %r2, %r3"
4807 
  [(set_attr "type" "X0_2cycle")])
4808 
 
4809 
(define_insn "insn_v2sadau"
4810 
  [(set (match_operand:DI 0 "register_operand" "=r")
4811 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "0")
4812 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")
4813 
                    (match_operand:DI 3 "reg_or_0_operand" "rO")]
4814 
                   UNSPEC_INSN_V2SADAU))]
4815 
  ""
4816 
  "v2sadau\t%0, %r2, %r3"
4817 
  [(set_attr "type" "X0_2cycle")])
4818 
 
4819 
(define_insn "insn_v2sads"
4820 
  [(set (match_operand:DI 0 "register_operand" "=r")
4821 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4822 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4823 
                   UNSPEC_INSN_V2SADS))]
4824 
  ""
4825 
  "v2sads\t%0, %r1, %r2"
4826 
  [(set_attr "type" "X0_2cycle")])
4827 
 
4828 
(define_insn "*insn_v2sads"
4829 
  [(set (match_operand:SI 0 "register_operand" "=r")
4830 
        (truncate:SI
4831 
         (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4832 
                     (match_operand:DI 2 "reg_or_0_operand" "rO")]
4833 
                    UNSPEC_INSN_V2SADS)))]
4834 
  ""
4835 
  "v2sads\t%0, %r1, %r2"
4836 
  [(set_attr "type" "X0_2cycle")])
4837 
 
4838 
(define_insn "insn_v2sadu"
4839 
  [(set (match_operand:DI 0 "register_operand" "=r")
4840 
        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4841 
                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
4842 
                   UNSPEC_INSN_V2SADU))]
4843 
  ""
4844 
  "v2sadu\t%0, %r1, %r2"
4845 
  [(set_attr "type" "X0_2cycle")])
4846 
 
4847 
(define_insn "*insn_v2sadu"
4848 
  [(set (match_operand:SI 0 "register_operand" "=r")
4849 
        (truncate:SI
4850 
         (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
4851 
                     (match_operand:DI 2 "reg_or_0_operand" "rO")]
4852 
                    UNSPEC_INSN_V2SADU)))]
4853 
  ""
4854 
  "v2sadu\t%0, %r1, %r2"
4855 
  [(set_attr "type" "X0_2cycle")])
4856 
 
4857 
(define_insn "insn_wh64"
4858 
  [(unspec_volatile:VOID [(match_operand 0 "pointer_operand" "rO")]
4859 
                         UNSPEC_INSN_WH64)
4860 
   (clobber (mem:BLK (const_int 0)))]
4861 
  ""
4862 
  "wh64\t%r0"
4863 
  [(set_attr "type" "X1")])
4864 
 
4865 
 
4866 
;; Network intrinsics
4867 
 
4868 
;; Note the "pseudo" text is handled specially by the
4869 
;; asm_output_opcode routine.  If the output is an empty string, the
4870 
;; instruction would bypass the asm_output_opcode routine, bypassing
4871 
;; the bundle handling code.
4872 
(define_insn "tilegx_network_barrier"
4873 
  [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)]
4874 
  ""
4875 
  "pseudo"
4876 
  [(set_attr "type" "nothing")
4877 
   (set_attr "length" "0")])
4878 
 
4879 
(define_insn "*netreg_receive"
4880 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,U,m")
4881 
        (unspec_volatile:DI [(match_operand:DI 1 "netreg_operand" "i,i,i")
4882 
                             (reg:DI TILEGX_NETORDER_REG)]
4883 
                            UNSPEC_NETWORK_RECEIVE))
4884 
   (clobber (reg:DI TILEGX_NETORDER_REG))]
4885 
 
4886 
  ""
4887 
  "@
4888 
   move\t%0, %N1
4889 
   st\t%0, %N1
4890 
   st_add\t%I0, %N1, %i0"
4891 
  [(set_attr "type" "*,Y2,X1")])
4892 
 
4893 
(define_insn "*netreg_send"
4894 
  [(unspec_volatile:DI
4895 
    [(match_operand:DI 0 "netreg_operand"  "i,i,i,i,i,i")
4896 
     (match_operand:DI 1 "reg_or_cint_operand" "r,I,J,K,N,P")
4897 
     (reg:DI TILEGX_NETORDER_REG)]
4898 
     UNSPEC_NETWORK_SEND)
4899 
   (clobber (reg:DI TILEGX_NETORDER_REG))]
4900 
  ""
4901 
  "@
4902 
   move\t%N0, %r1
4903 
   movei\t%N0, %1
4904 
   moveli\t%N0, %1
4905 
   shl16insli\t%N0, zero, %h1
4906 
   v1addi\t%N0, zero, %j1
4907 
   v2addi\t%N0, zero, %h1"
4908 
  [(set_attr "type" "*,*,X01,X01,X01,X01")])
4909 
 
4910 
(define_expand "tilegx_idn0_receive"
4911 
  [(parallel
4912 
    [(set (match_operand:DI 0 "register_operand" "")
4913 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
4914 
                               (reg:DI TILEGX_NETORDER_REG)]
4915 
                              UNSPEC_NETWORK_RECEIVE))
4916 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4917 
  "")
4918 
 
4919 
(define_expand "tilegx_idn1_receive"
4920 
  [(parallel
4921 
    [(set (match_operand:DI 0 "register_operand" "")
4922 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_IDN1)
4923 
                               (reg:DI TILEGX_NETORDER_REG)]
4924 
                              UNSPEC_NETWORK_RECEIVE))
4925 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4926 
  "")
4927 
 
4928 
(define_expand "tilegx_idn_send"
4929 
  [(parallel
4930 
    [(unspec_volatile:DI [(const_int TILEGX_NETREG_IDN0)
4931 
                          (match_operand:DI 0 "reg_or_cint_operand" "")
4932 
                          (reg:DI TILEGX_NETORDER_REG)]
4933 
                         UNSPEC_NETWORK_SEND)
4934 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4935 
  "")
4936 
 
4937 
(define_expand "tilegx_udn0_receive"
4938 
  [(parallel
4939 
    [(set (match_operand:DI 0 "register_operand" "")
4940 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
4941 
                               (reg:DI TILEGX_NETORDER_REG)]
4942 
                              UNSPEC_NETWORK_RECEIVE))
4943 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4944 
  "")
4945 
 
4946 
(define_expand "tilegx_udn1_receive"
4947 
  [(parallel
4948 
    [(set (match_operand:DI 0 "register_operand" "")
4949 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN1)
4950 
                               (reg:DI TILEGX_NETORDER_REG)]
4951 
                              UNSPEC_NETWORK_RECEIVE))
4952 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4953 
  "")
4954 
 
4955 
(define_expand "tilegx_udn2_receive"
4956 
  [(parallel
4957 
    [(set (match_operand:DI 0 "register_operand" "")
4958 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN2)
4959 
                               (reg:DI TILEGX_NETORDER_REG)]
4960 
                              UNSPEC_NETWORK_RECEIVE))
4961 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4962 
  "")
4963 
 
4964 
(define_expand "tilegx_udn3_receive"
4965 
  [(parallel
4966 
    [(set (match_operand:DI 0 "register_operand" "")
4967 
          (unspec_volatile:DI [(const_int TILEGX_NETREG_UDN3)
4968 
                               (reg:DI TILEGX_NETORDER_REG)]
4969 
                              UNSPEC_NETWORK_RECEIVE))
4970 
     (clobber (reg:DI TILEGX_NETORDER_REG))])]
4971 
  "")
4972 
 
4973 
(define_expand "tilegx_udn_send"
4974 
  [(parallel
4975 
    [(unspec_volatile:DI [(const_int TILEGX_NETREG_UDN0)
4976 
                          (match_operand:DI 0 "reg_or_cint_operand" "")
4977 
                          (reg:DI TILEGX_NETORDER_REG)]
4978 
                         UNSPEC_NETWORK_SEND)
4979 
    (clobber (reg:DI TILEGX_NETORDER_REG))])]
4980 
  "")
4981 
 
4982 
(define_insn "*netreg_adddi_to_network"
4983 
  [(unspec_volatile:DI
4984 
    [(match_operand:DI 0 "netreg_operand" "i,i,i")
4985 
     (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rO,rO,rO")
4986 
              (match_operand:DI 2 "add_operand" "r,I,JT"))
4987 
     (reg:DI TILEGX_NETORDER_REG)]
4988 
    UNSPEC_NETWORK_SEND)
4989 
   (clobber (reg:DI TILEGX_NETORDER_REG))]
4990 
  ""
4991 
  "@
4992 
   add\t%N0, %r1, %2
4993 
   addi\t%N0, %r1, %2
4994 
   addli\t%N0, %r1, %H2"
4995 
  [(set_attr "type" "*,*,X01")])
4996 
 
4997 
(define_insn "*netreg_adddi_from_network"
4998 
  [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4999 
        (plus:DI (unspec_volatile:DI
5000 
                  [(match_operand:DI 1 "netreg_operand" "%i,i,i")
5001 
                   (reg:DI TILEGX_NETORDER_REG)]
5002 
                  UNSPEC_NETWORK_RECEIVE)
5003 
                 (match_operand:DI 2 "add_operand" "rO,I,JT")))
5004 
   (clobber (reg:DI TILEGX_NETORDER_REG))]
5005 
  ""
5006 
  "@
5007 
   add\t%0, %N1, %r2
5008 
   addi\t%0, %N1, %2
5009 
   addli\t%0, %N1, %H2"
5010 
  [(set_attr "type" "*,*,X01")])
5011 
 
5012 
 
5013 
;;
5014 
;; Stack protector instructions.
5015 
;;
5016 
 
5017 
(define_expand "stack_protect_set"
5018 
  [(set (match_operand 0 "nonautoincmem_operand" "")
5019 
        (match_operand 1 "nonautoincmem_operand" ""))]
5020 
  ""
5021 
{
5022 
#ifdef TARGET_THREAD_SSP_OFFSET
5023 
  rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5024 
  rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5025 
  rtx ssp = gen_reg_rtx (Pmode);
5026 
 
5027 
  emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
5028 
 
5029 
  operands[1] = gen_rtx_MEM (Pmode, ssp);
5030 
#endif
5031 
 
5032 
  if (TARGET_32BIT)
5033 
    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
5034 
  else
5035 
    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
5036 
 
5037 
  DONE;
5038 
})
5039 
 
5040 
(define_insn "stack_protect_setsi"
5041 
  [(set (match_operand:SI 0 "nonautoincmem_operand" "=U")
5042 
        (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")]
5043 
                   UNSPEC_SP_SET))
5044 
   (set (match_scratch:SI 2 "=&r") (const_int 0))]
5045 
  ""
5046 
  "ld4s\t%2, %1; { st4\t%0, %2; move\t%2, zero }"
5047 
  [(set_attr "length" "16")
5048 
   (set_attr "type" "cannot_bundle_3cycle")])
5049 
 
5050 
(define_insn "stack_protect_setdi"
5051 
  [(set (match_operand:DI 0 "nonautoincmem_operand" "=U")
5052 
        (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")]
5053 
                   UNSPEC_SP_SET))
5054 
   (set (match_scratch:DI 2 "=&r") (const_int 0))]
5055 
  ""
5056 
  "ld\t%2, %1; { st\t%0, %2; move\t%2, zero }"
5057 
  [(set_attr "length" "16")
5058 
   (set_attr "type" "cannot_bundle_3cycle")])
5059 
 
5060 
(define_expand "stack_protect_test"
5061 
  [(match_operand 0 "nonautoincmem_operand" "")
5062 
   (match_operand 1 "nonautoincmem_operand" "")
5063 
   (match_operand 2 "" "")]
5064 
  ""
5065 
{
5066 
  rtx compare_result;
5067 
  rtx bcomp, loc_ref;
5068 
 
5069 
#ifdef TARGET_THREAD_SSP_OFFSET
5070 
  rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
5071 
  rtx ssp_addr = gen_rtx_PLUS (Pmode, tp, GEN_INT (TARGET_THREAD_SSP_OFFSET));
5072 
  rtx ssp = gen_reg_rtx (Pmode);
5073 
 
5074 
  emit_insn (gen_rtx_SET (VOIDmode, ssp, ssp_addr));
5075 
 
5076 
  operands[1] = gen_rtx_MEM (Pmode, ssp);
5077 
#endif
5078 
 
5079 
  compare_result = gen_reg_rtx (Pmode);
5080 
 
5081 
  if (TARGET_32BIT)
5082 
    emit_insn (gen_stack_protect_testsi (compare_result, operands[0],
5083 
                                         operands[1]));
5084 
  else
5085 
    emit_insn (gen_stack_protect_testdi (compare_result, operands[0],
5086 
                                         operands[1]));
5087 
 
5088 
  bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx);
5089 
 
5090 
  loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]);
5091 
 
5092 
  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
5093 
                               gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
5094 
                                                     loc_ref, pc_rtx)));
5095 
 
5096 
  DONE;
5097 
})
5098 
 
5099 
(define_insn "stack_protect_testsi"
5100 
  [(set (match_operand:SI 0 "register_operand" "=&r")
5101 
        (unspec:SI [(match_operand:SI 1 "nonautoincmem_operand" "U")
5102 
                    (match_operand:SI 2 "nonautoincmem_operand" "U")]
5103 
                   UNSPEC_SP_TEST))
5104 
   (set (match_scratch:SI 3 "=&r") (const_int 0))]
5105 
  ""
5106 
  "ld4s\t%0, %1; ld4s\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5107 
  [(set_attr "length" "24")
5108 
   (set_attr "type" "cannot_bundle_4cycle")])
5109 
 
5110 
(define_insn "stack_protect_testdi"
5111 
  [(set (match_operand:DI 0 "register_operand" "=&r")
5112 
        (unspec:DI [(match_operand:DI 1 "nonautoincmem_operand" "U")
5113 
                    (match_operand:DI 2 "nonautoincmem_operand" "U")]
5114 
                   UNSPEC_SP_TEST))
5115 
   (set (match_scratch:DI 3 "=&r") (const_int 0))]
5116 
  ""
5117 
  "ld\t%0, %1; ld\t%3, %2; { cmpeq\t%0, %0, %3; move\t%3, zero }"
5118 
  [(set_attr "length" "24")
5119 
   (set_attr "type" "cannot_bundle_4cycle")])
5120 
 
5121 
(include "sync.md")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.