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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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jeremybenn |
; Options for the TILE-Gx port of the compiler.
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; Copyright (C) 2011, 2012
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; Free Software Foundation, Inc.
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; Contributed by Walter Lee (walt@tilera.com)
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; .
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mcpu=
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Target RejectNegative Joined Enum(tilegx_cpu) Var(tilegx_cpu) Init(0)
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-mcpu=CPU Use features of and schedule code for given CPU
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Enum
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Name(tilegx_cpu) Type(int)
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Known TILE-Gx CPUs (for use with the -mcpu= option):
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EnumValue
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Enum(tilegx_cpu) String(tilegx) Value(0)
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m32
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Target Report RejectNegative Negative(m64) Mask(32BIT)
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Compile with 32 bit longs and pointers.
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m64
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Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
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Compile with 64 bit longs and pointers.
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