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1 709 jeremybenn
;; Machine description for GNU compiler, VAX Version
2
;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3
;; 2002, 2004, 2005, 2007, 2009 Free Software Foundation, Inc.
4
 
5
;; This file is part of GCC.
6
 
7
;; GCC is free software; you can redistribute it and/or modify
8
;; it under the terms of the GNU General Public License as published by
9
;; the Free Software Foundation; either version 3, or (at your option)
10
;; any later version.
11
 
12
;; GCC is distributed in the hope that it will be useful,
13
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
;; GNU General Public License for more details.
16
 
17
;; You should have received a copy of the GNU General Public License
18
;; along with GCC; see the file COPYING3.  If not see
19
;; .
20
 
21
 
22
;;- Instruction patterns.  When multiple patterns apply,
23
;;- the first one in the file is chosen.
24
;;-
25
;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
26
;;-
27
;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
28
;;- updates for most instructions.
29
 
30
;; UNSPEC_VOLATILE usage:
31
 
32
(define_c_enum "unspecv" [
33
  VUNSPEC_BLOCKAGE          ; 'blockage' insn to prevent scheduling across an
34
                            ; insn in the code.
35
  VUNSPEC_SYNC_ISTREAM      ; sequence of insns to sync the I-stream
36
  VUNSPEC_PEM               ; 'procedure_entry_mask' insn.
37
])
38
 
39
(define_constants
40
  [(VAX_AP_REGNUM 12)       ; Register 12 contains the argument pointer
41
   (VAX_FP_REGNUM 13)       ; Register 13 contains the frame pointer
42
   (VAX_SP_REGNUM 14)       ; Register 14 contains the stack pointer
43
   (VAX_PC_REGNUM 15)       ; Register 15 contains the program counter
44
  ]
45
)
46
 
47
;; Integer modes supported on VAX, with a mapping from machine mode
48
;; to mnemonic suffix.  DImode is always a special case.
49
(define_mode_iterator VAXint [QI HI SI])
50
(define_mode_iterator VAXintQH [QI HI])
51
(define_mode_iterator VAXintQHSD [QI HI SI DI])
52
(define_mode_attr  isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
53
 
54
;; Similar for float modes supported on VAX.
55
(define_mode_iterator VAXfp [SF DF])
56
(define_mode_attr  fsfx [(SF "f") (DF "%#")])
57
 
58
;; Some output patterns want integer immediates with a prefix...
59
(define_mode_attr  iprefx [(QI "B") (HI "H") (SI "N")])
60
 
61
;;
62
(include "constraints.md")
63
(include "predicates.md")
64
 
65
(define_insn "*cmp"
66
  [(set (cc0)
67
        (compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT,nrmT")
68
                 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
69
  ""
70
  "@
71
   tst %0
72
   cmp %0,%1")
73
 
74
(define_insn "*cmp"
75
  [(set (cc0)
76
        (compare (match_operand:VAXfp 0 "general_operand" "gF,gF")
77
                 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
78
  ""
79
  "@
80
   tst %0
81
   cmp %0,%1")
82
 
83
(define_insn "*bit"
84
  [(set (cc0)
85
        (compare (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
86
                             (match_operand:VAXint 1 "general_operand" "nrmT"))
87
                 (const_int 0)))]
88
  ""
89
  "bit %0,%1")
90
 
91
;; The VAX has no sCOND insns.  It does have add/subtract with carry
92
;; which could be used to implement the sltu and sgeu patterns.  However,
93
;; to do this properly requires a complete rewrite of the compare insns
94
;; to keep them together with the sltu/sgeu insns until after the
95
;; reload pass is complete.  The previous implementation didn't do this
96
;; and has been deleted.
97
 
98
 
99
(define_insn "mov"
100
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
101
        (match_operand:VAXfp 1 "general_operand" "G,gF"))]
102
  ""
103
  "@
104
   clr %0
105
   mov %1,%0")
106
 
107
;; Some VAXen don't support this instruction.
108
;;(define_insn "movti"
109
;;  [(set (match_operand:TI 0 "general_operand" "=g")
110
;;      (match_operand:TI 1 "general_operand" "g"))]
111
;;  ""
112
;;  "movh %1,%0")
113
 
114
(define_insn "movdi"
115
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
116
        (match_operand:DI 1 "general_operand" "g"))]
117
  ""
118
  "* return vax_output_int_move (insn, operands, DImode);")
119
 
120
;; The VAX move instructions have space-time tradeoffs.  On a MicroVAX
121
;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
122
;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
123
;; if the constant is smaller than 4 bytes, 3 cycles for a longword
124
;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
125
;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
126
;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
127
;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
128
;; instead of movl).
129
 
130
;; Cycle counts for other models may vary (on a VAX 750 they are similar,
131
;; but on a VAX 9000 most move and add instructions with one constant
132
;; operand take 1 cycle).
133
 
134
;;  Loads of constants between 64 and 128 used to be done with
135
;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
136
 
137
(define_expand "movsi"
138
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
139
        (match_operand:SI 1 "general_operand" ""))]
140
  ""
141
  "
142
{
143
#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
144
  if (flag_pic
145
      && GET_CODE (operands[1]) == CONST
146
      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
147
      && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
148
    {
149
      rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
150
      rtx const_int = XEXP (XEXP (operands[1], 0), 1);
151
      rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
152
      emit_move_insn (temp, symbol_ref);
153
      emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
154
      DONE;
155
    }
156
#endif
157
}")
158
 
159
(define_insn "movsi_2"
160
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
161
        (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
162
  ""
163
  "* return vax_output_int_move (insn, operands, SImode);")
164
 
165
(define_insn "mov"
166
  [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
167
        (match_operand:VAXintQH 1 "general_operand" "g"))]
168
  ""
169
  "* return vax_output_int_move (insn, operands, mode);")
170
 
171
(define_insn "movstricthi"
172
  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
173
        (match_operand:HI 1 "general_operand" "g"))]
174
  ""
175
  "*
176
{
177
  if (CONST_INT_P (operands[1]))
178
    {
179
      int i = INTVAL (operands[1]);
180
      if (i == 0)
181
        return \"clrw %0\";
182
      else if ((unsigned int)i < 64)
183
        return \"movw %1,%0\";
184
      else if ((unsigned int)~i < 64)
185
        return \"mcomw %H1,%0\";
186
      else if ((unsigned int)i < 256)
187
        return \"movzbw %1,%0\";
188
    }
189
  return \"movw %1,%0\";
190
}")
191
 
192
(define_insn "movstrictqi"
193
  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
194
        (match_operand:QI 1 "general_operand" "g"))]
195
  ""
196
  "*
197
{
198
  if (CONST_INT_P (operands[1]))
199
    {
200
      int i = INTVAL (operands[1]);
201
      if (i == 0)
202
        return \"clrb %0\";
203
      else if ((unsigned int)~i < 64)
204
        return \"mcomb %B1,%0\";
205
    }
206
  return \"movb %1,%0\";
207
}")
208
 
209
;; This is here to accept 4 arguments and pass the first 3 along
210
;; to the movmemhi1 pattern that really does the work.
211
(define_expand "movmemhi"
212
  [(set (match_operand:BLK 0 "general_operand" "=g")
213
        (match_operand:BLK 1 "general_operand" "g"))
214
   (use (match_operand:HI 2 "general_operand" "g"))
215
   (match_operand 3 "" "")]
216
  ""
217
  "
218
{
219
  emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
220
  DONE;
221
}")
222
 
223
;; The definition of this insn does not really explain what it does,
224
;; but it should suffice
225
;; that anything generated as this insn will be recognized as one
226
;; and that it won't successfully combine with anything.
227
 
228
(define_insn "movmemhi1"
229
  [(set (match_operand:BLK 0 "memory_operand" "=o")
230
        (match_operand:BLK 1 "memory_operand" "o"))
231
   (use (match_operand:HI 2 "general_operand" "g"))
232
   (clobber (reg:SI 0))
233
   (clobber (reg:SI 1))
234
   (clobber (reg:SI 2))
235
   (clobber (reg:SI 3))
236
   (clobber (reg:SI 4))
237
   (clobber (reg:SI 5))]
238
  ""
239
  "movc3 %2,%1,%0")
240
 
241
;; Extension and truncation insns.
242
 
243
(define_insn "truncsiqi2"
244
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
245
        (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
246
  ""
247
  "cvtlb %1,%0")
248
 
249
(define_insn "truncsihi2"
250
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
251
        (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
252
  ""
253
  "cvtlw %1,%0")
254
 
255
(define_insn "trunchiqi2"
256
  [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
257
        (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
258
  ""
259
  "cvtwb %1,%0")
260
 
261
(define_insn "extendhisi2"
262
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
263
        (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
264
  ""
265
  "cvtwl %1,%0")
266
 
267
(define_insn "extendqihi2"
268
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
269
        (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
270
  ""
271
  "cvtbw %1,%0")
272
 
273
(define_insn "extendqisi2"
274
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
275
        (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
276
  ""
277
  "cvtbl %1,%0")
278
 
279
(define_insn "extendsfdf2"
280
  [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
281
        (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
282
  ""
283
  "cvtf%# %1,%0")
284
 
285
(define_insn "truncdfsf2"
286
  [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
287
        (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
288
  ""
289
  "cvt%#f %1,%0")
290
 
291
(define_insn "zero_extendhisi2"
292
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
293
        (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
294
  ""
295
  "movzwl %1,%0")
296
 
297
(define_insn "zero_extendqihi2"
298
  [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
299
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
300
  ""
301
  "movzbw %1,%0")
302
 
303
(define_insn "zero_extendqisi2"
304
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
305
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
306
  ""
307
  "movzbl %1,%0")
308
 
309
;; Fix-to-float conversion insns.
310
 
311
(define_insn "float2"
312
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
313
        (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
314
  ""
315
  "cvt %1,%0")
316
 
317
;; Float-to-fix conversion insns.
318
 
319
(define_insn "fix_trunc2"
320
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
321
        (fix:VAXint (fix:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))))]
322
  ""
323
  "cvt %1,%0")
324
 
325
;;- All kinds of add instructions.
326
 
327
(define_insn "add3"
328
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
329
        (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
330
                    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
331
  ""
332
  "@
333
   add2 %2,%0
334
   add2 %1,%0
335
   add3 %1,%2,%0")
336
 
337
(define_insn "pushlclsymreg"
338
  [(set (match_operand:SI 0 "push_operand" "=g")
339
        (plus:SI (match_operand:SI 1 "register_operand" "%r")
340
                 (match_operand:SI 2 "local_symbolic_operand" "i")))]
341
  "flag_pic"
342
  "pushab %a2[%1]")
343
 
344
(define_insn "pushextsymreg"
345
  [(set (match_operand:SI 0 "push_operand" "=g")
346
        (plus:SI (match_operand:SI 1 "register_operand" "%r")
347
                 (match_operand:SI 2 "external_symbolic_operand" "i")))]
348
  "flag_pic"
349
  "pushab %a2[%1]")
350
 
351
(define_insn "movlclsymreg"
352
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
353
        (plus:SI (match_operand:SI 1 "register_operand" "%r")
354
                 (match_operand:SI 2 "local_symbolic_operand" "i")))]
355
  "flag_pic"
356
  "movab %a2[%1],%0")
357
 
358
(define_insn "movextsymreg"
359
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
360
        (plus:SI (match_operand:SI 1 "register_operand" "%r")
361
                 (match_operand:SI 2 "external_symbolic_operand" "i")))]
362
  "flag_pic"
363
  "movab %a2[%1],%0")
364
 
365
(define_insn "add3"
366
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
367
        (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
368
                    (match_operand:VAXint 2 "general_operand" "nrmT")))]
369
  ""
370
  "* return vax_output_int_add (insn, operands, mode);")
371
 
372
(define_expand "adddi3"
373
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
374
        (plus:DI (match_operand:DI 1 "general_operand" "g")
375
                 (match_operand:DI 2 "general_operand" "g")))]
376
  "!reload_in_progress"
377
  "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
378
 
379
(define_insn "adcdi3"
380
  [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
381
        (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
382
                 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
383
  "TARGET_QMATH"
384
  "* return vax_output_int_add (insn, operands, DImode);")
385
 
386
;; The add-with-carry (adwc) instruction only accepts two operands.
387
(define_insn "adddi3_old"
388
  [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
389
        (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
390
                 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
391
  "!TARGET_QMATH"
392
  "* return vax_output_int_add (insn, operands, DImode);")
393
 
394
;;- All kinds of subtract instructions.
395
 
396
(define_insn "sub3"
397
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
398
        (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
399
                     (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
400
  ""
401
  "@
402
   sub2 %2,%0
403
   sub3 %2,%1,%0")
404
 
405
(define_insn "sub3"
406
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
407
        (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
408
                     (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
409
  ""
410
  "@
411
   sub2 %2,%0
412
   sub3 %2,%1,%0")
413
 
414
(define_expand "subdi3"
415
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
416
        (minus:DI (match_operand:DI 1 "general_operand" "g")
417
                  (match_operand:DI 2 "general_operand" "g")))]
418
  "!reload_in_progress"
419
  "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
420
 
421
(define_insn "sbcdi3"
422
  [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
423
        (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
424
                  (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
425
  "TARGET_QMATH"
426
  "* return vax_output_int_subtract (insn, operands, DImode);")
427
 
428
;; The subtract-with-carry (sbwc) instruction only takes two operands.
429
(define_insn "subdi3_old"
430
  [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
431
        (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
432
                  (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
433
  "!TARGET_QMATH"
434
  "* return vax_output_int_subtract (insn, operands, DImode);")
435
 
436
;;- Multiply instructions.
437
 
438
(define_insn "mul3"
439
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
440
        (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
441
                    (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
442
  ""
443
  "@
444
   mul2 %2,%0
445
   mul2 %1,%0
446
   mul3 %1,%2,%0")
447
 
448
(define_insn "mul3"
449
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
450
        (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
451
                    (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
452
  ""
453
  "@
454
   mul2 %2,%0
455
   mul2 %1,%0
456
   mul3 %1,%2,%0")
457
 
458
(define_insn "mulsidi3"
459
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
460
        (mult:DI (sign_extend:DI
461
                  (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
462
                 (sign_extend:DI
463
                  (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))]
464
  ""
465
  "emul %1,%2,$0,%0")
466
 
467
(define_insn ""
468
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
469
        (plus:DI
470
         (mult:DI (sign_extend:DI
471
                   (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
472
                  (sign_extend:DI
473
                   (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
474
         (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
475
  ""
476
  "emul %1,%2,%3,%0")
477
 
478
;; 'F' constraint means type CONST_DOUBLE
479
(define_insn ""
480
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
481
        (plus:DI
482
         (mult:DI (sign_extend:DI
483
                   (match_operand:SI 1 "nonimmediate_operand" "nrmT"))
484
                  (sign_extend:DI
485
                   (match_operand:SI 2 "nonimmediate_operand" "nrmT")))
486
         (match_operand:DI 3 "immediate_operand" "F")))]
487
  "GET_CODE (operands[3]) == CONST_DOUBLE
488
    && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
489
  "*
490
{
491
  if (CONST_DOUBLE_HIGH (operands[3]))
492
    operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
493
  return \"emul %1,%2,%3,%0\";
494
}")
495
 
496
;;- Divide instructions.
497
 
498
(define_insn "div3"
499
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
500
        (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
501
                   (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
502
  ""
503
  "@
504
   div2 %2,%0
505
   div3 %2,%1,%0")
506
 
507
(define_insn "div3"
508
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
509
        (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
510
                   (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
511
  ""
512
  "@
513
   div2 %2,%0
514
   div3 %2,%1,%0")
515
 
516
;This is left out because it is very slow;
517
;we are better off programming around the "lack" of this insn.
518
;(define_insn "divmoddisi4"
519
;  [(set (match_operand:SI 0 "general_operand" "=g")
520
;       (div:SI (match_operand:DI 1 "general_operand" "g")
521
;               (match_operand:SI 2 "general_operand" "g")))
522
;   (set (match_operand:SI 3 "general_operand" "=g")
523
;       (mod:SI (match_operand:DI 1 "general_operand" "g")
524
;               (match_operand:SI 2 "general_operand" "g")))]
525
;  ""
526
;  "ediv %2,%1,%0,%3")
527
 
528
;; Bit-and on the VAX is done with a clear-bits insn.
529
(define_expand "and3"
530
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
531
        (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
532
                   (match_operand:VAXint 2 "general_operand" "")))]
533
  ""
534
  "
535
{
536
  rtx op1 = operands[1];
537
 
538
  /* If there is a constant argument, complement that one.  */
539
  if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
540
    {
541
      operands[1] = operands[2];
542
      operands[2] = op1;
543
      op1 = operands[1];
544
    }
545
 
546
  if (CONST_INT_P (op1))
547
    operands[1] = GEN_INT (~INTVAL (op1));
548
  else
549
    operands[1] = expand_unop (mode, one_cmpl_optab, op1, 0, 1);
550
}")
551
 
552
(define_insn "*and"
553
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
554
        (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
555
                    (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
556
  ""
557
  "@
558
   bic2 %1,%0
559
   bic3 %1,%2,%0")
560
 
561
;; The following used to be needed because constant propagation can
562
;; create them starting from the bic insn patterns above.  This is no
563
;; longer a problem.  However, having these patterns allows optimization
564
;; opportunities in combine.c.
565
 
566
(define_insn "*and_const_int"
567
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
568
        (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
569
                   (match_operand:VAXint 2 "const_int_operand" "n,n")))]
570
  ""
571
  "@
572
   bic2 %2,%0
573
   bic3 %2,%1,%0")
574
 
575
 
576
;;- Bit set instructions.
577
 
578
(define_insn "ior3"
579
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
580
        (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
581
                   (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
582
  ""
583
  "@
584
   bis2 %2,%0
585
   bis2 %1,%0
586
   bis3 %2,%1,%0")
587
 
588
;;- xor instructions.
589
 
590
(define_insn "xor3"
591
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
592
        (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
593
                   (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
594
  ""
595
  "@
596
   xor2 %2,%0
597
   xor2 %1,%0
598
   xor3 %2,%1,%0")
599
 
600
 
601
(define_insn "neg2"
602
  [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
603
        (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
604
  ""
605
  "mneg %1,%0")
606
 
607
(define_insn "neg2"
608
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
609
        (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
610
  ""
611
  "mneg %1,%0")
612
 
613
(define_insn "one_cmpl2"
614
  [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
615
        (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
616
  ""
617
  "mcom %1,%0")
618
 
619
 
620
;; Arithmetic right shift on the VAX works by negating the shift count,
621
;; then emitting a right shift with the shift count negated.  This means
622
;; that all actual shift counts in the RTL will be positive.  This
623
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
624
;; which isn't valid.
625
(define_expand "ashrsi3"
626
  [(set (match_operand:SI 0 "general_operand" "=g")
627
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
628
                   (match_operand:QI 2 "general_operand" "g")))]
629
  ""
630
  "
631
{
632
  if (! CONST_INT_P(operands[2]))
633
    operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
634
}")
635
 
636
(define_insn ""
637
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
638
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
639
                     (match_operand:QI 2 "const_int_operand" "n")))]
640
  ""
641
  "ashl $%n2,%1,%0")
642
 
643
(define_insn ""
644
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
645
        (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
646
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
647
  ""
648
  "ashl %2,%1,%0")
649
 
650
(define_insn "ashlsi3"
651
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
652
        (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
653
                   (match_operand:QI 2 "general_operand" "g")))]
654
  ""
655
  "*
656
{
657
  if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
658
    return \"addl2 %0,%0\";
659
  if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
660
    {
661
      int i = INTVAL (operands[2]);
662
      if (i == 1)
663
        return \"addl3 %1,%1,%0\";
664
      if (i == 2 && !optimize_size)
665
        {
666
          if (push_operand (operands[0], SImode))
667
            return \"pushal 0[%1]\";
668
          return \"moval 0[%1],%0\";
669
        }
670
      if (i == 3 && !optimize_size)
671
        {
672
          if (push_operand (operands[0], SImode))
673
            return \"pushaq 0[%1]\";
674
          return \"movaq 0[%1],%0\";
675
        }
676
    }
677
  return \"ashl %2,%1,%0\";
678
}")
679
 
680
;; Arithmetic right shift on the VAX works by negating the shift count.
681
(define_expand "ashrdi3"
682
  [(set (match_operand:DI 0 "general_operand" "=g")
683
        (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
684
                     (match_operand:QI 2 "general_operand" "g")))]
685
  ""
686
  "
687
{
688
  operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
689
}")
690
 
691
(define_insn "ashldi3"
692
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
693
        (ashift:DI (match_operand:DI 1 "general_operand" "g")
694
                   (match_operand:QI 2 "general_operand" "g")))]
695
  ""
696
  "ashq %2,%1,%0")
697
 
698
(define_insn ""
699
  [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
700
        (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
701
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
702
  ""
703
  "ashq %2,%1,%0")
704
 
705
;; We used to have expand_shift handle logical right shifts by using extzv,
706
;; but this make it very difficult to do lshrdi3.  Since the VAX is the
707
;; only machine with this kludge, it's better to just do this with a
708
;; define_expand and remove that case from expand_shift.
709
 
710
(define_expand "lshrsi3"
711
  [(set (match_dup 3)
712
        (minus:QI (const_int 32)
713
                  (match_dup 4)))
714
   (set (match_operand:SI 0 "nonimmediate_operand" "=g")
715
        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
716
                         (match_dup 3)
717
                         (match_operand:SI 2 "register_operand" "g")))]
718
  ""
719
  "
720
{
721
  operands[3] = gen_reg_rtx (QImode);
722
  operands[4] = gen_lowpart (QImode, operands[2]);
723
}")
724
 
725
;; Rotate right on the VAX works by negating the shift count.
726
(define_expand "rotrsi3"
727
  [(set (match_operand:SI 0 "general_operand" "=g")
728
        (rotatert:SI (match_operand:SI 1 "general_operand" "g")
729
                     (match_operand:QI 2 "general_operand" "g")))]
730
  ""
731
  "
732
{
733
  if (! CONST_INT_P (operands[2]))
734
    operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
735
}")
736
 
737
(define_insn "rotlsi3"
738
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
739
        (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
740
                   (match_operand:QI 2 "general_operand" "g")))]
741
  ""
742
  "rotl %2,%1,%0")
743
 
744
(define_insn ""
745
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
746
        (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
747
                     (match_operand:QI 2 "const_int_operand" "n")))]
748
  ""
749
  "rotl %R2,%1,%0")
750
 
751
(define_insn ""
752
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
753
        (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
754
                     (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
755
  ""
756
  "rotl %2,%1,%0")
757
 
758
;This insn is probably slower than a multiply and an add.
759
;(define_insn ""
760
;  [(set (match_operand:SI 0 "general_operand" "=g")
761
;       (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
762
;                         (match_operand:SI 2 "general_operand" "g"))
763
;                (match_operand:SI 3 "general_operand" "g")))]
764
;  ""
765
;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
766
 
767
;; Special cases of bit-field insns which we should
768
;; recognize in preference to the general case.
769
;; These handle aligned 8-bit and 16-bit fields,
770
;; which can usually be done with move instructions.
771
 
772
(define_insn ""
773
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
774
                         (match_operand:QI 1 "const_int_operand" "n")
775
                         (match_operand:SI 2 "const_int_operand" "n"))
776
        (match_operand:SI 3 "general_operand" "g"))]
777
   "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
778
   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
779
   && (REG_P (operands[0])
780
       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
781
  "*
782
{
783
  if (REG_P (operands[0]))
784
    {
785
      if (INTVAL (operands[2]) != 0)
786
        return \"insv %3,%2,%1,%0\";
787
    }
788
  else
789
    operands[0]
790
      = adjust_address (operands[0],
791
                        INTVAL (operands[1]) == 8 ? QImode : HImode,
792
                        INTVAL (operands[2]) / 8);
793
 
794
  CC_STATUS_INIT;
795
  if (INTVAL (operands[1]) == 8)
796
    return \"movb %3,%0\";
797
  return \"movw %3,%0\";
798
}")
799
 
800
(define_insn ""
801
  [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
802
        (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
803
                         (match_operand:QI 2 "const_int_operand" "n")
804
                         (match_operand:SI 3 "const_int_operand" "n")))]
805
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
806
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
807
   && (REG_P (operands[1])
808
       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
809
  "*
810
{
811
  if (REG_P (operands[1]))
812
    {
813
      if (INTVAL (operands[3]) != 0)
814
        return \"extzv %3,%2,%1,%0\";
815
    }
816
  else
817
    operands[1]
818
      = adjust_address (operands[1],
819
                        INTVAL (operands[2]) == 8 ? QImode : HImode,
820
                        INTVAL (operands[3]) / 8);
821
 
822
  if (INTVAL (operands[2]) == 8)
823
    return \"movzbl %1,%0\";
824
  return \"movzwl %1,%0\";
825
}")
826
 
827
(define_insn ""
828
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
829
        (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
830
                         (match_operand:QI 2 "const_int_operand" "n")
831
                         (match_operand:SI 3 "const_int_operand" "n")))]
832
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
833
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
834
   && (REG_P (operands[1])
835
       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
836
  "*
837
{
838
  if (REG_P (operands[1]))
839
    {
840
      if (INTVAL (operands[3]) != 0)
841
        return \"extv %3,%2,%1,%0\";
842
    }
843
  else
844
    operands[1]
845
      = adjust_address (operands[1],
846
                        INTVAL (operands[2]) == 8 ? QImode : HImode,
847
                        INTVAL (operands[3]) / 8);
848
 
849
  if (INTVAL (operands[2]) == 8)
850
    return \"cvtbl %1,%0\";
851
  return \"cvtwl %1,%0\";
852
}")
853
 
854
;; Register-only SImode cases of bit-field insns.
855
 
856
(define_insn ""
857
  [(set (cc0)
858
        (compare
859
         (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
860
                          (match_operand:QI 1 "general_operand" "g")
861
                          (match_operand:SI 2 "general_operand" "nrmT"))
862
         (match_operand:SI 3 "general_operand" "nrmT")))]
863
  ""
864
  "cmpv %2,%1,%0,%3")
865
 
866
(define_insn ""
867
  [(set (cc0)
868
        (compare
869
         (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
870
                          (match_operand:QI 1 "general_operand" "g")
871
                          (match_operand:SI 2 "general_operand" "nrmT"))
872
         (match_operand:SI 3 "general_operand" "nrmT")))]
873
  ""
874
  "cmpzv %2,%1,%0,%3")
875
 
876
;; When the field position and size are constant and the destination
877
;; is a register, extv and extzv are much slower than a rotate followed
878
;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
879
;; anyway, we can't allow immediate values for the primary source operand.
880
 
881
(define_insn ""
882
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
883
        (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
884
                         (match_operand:QI 2 "general_operand" "g")
885
                         (match_operand:SI 3 "general_operand" "nrmT")))]
886
  ""
887
  "*
888
{
889
  if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
890
      || ! REG_P (operands[0])
891
      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
892
    return \"extv %3,%2,%1,%0\";
893
  if (INTVAL (operands[2]) == 8)
894
    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
895
  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
896
}")
897
 
898
(define_insn ""
899
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
900
        (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
901
                         (match_operand:QI 2 "general_operand" "g")
902
                         (match_operand:SI 3 "general_operand" "nrmT")))]
903
  ""
904
  "*
905
{
906
  if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
907
      || ! REG_P (operands[0]))
908
    return \"extzv %3,%2,%1,%0\";
909
  if (INTVAL (operands[2]) == 8)
910
    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
911
  if (INTVAL (operands[2]) == 16)
912
    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
913
  if (INTVAL (operands[3]) & 31)
914
    return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
915
  if (rtx_equal_p (operands[0], operands[1]))
916
    return \"bicl2 %M2,%0\";
917
  return \"bicl3 %M2,%1,%0\";
918
}")
919
 
920
;; Non-register cases.
921
;; nonimmediate_operand is used to make sure that mode-ambiguous cases
922
;; don't match these (and therefore match the cases above instead).
923
 
924
(define_insn ""
925
  [(set (cc0)
926
        (compare
927
         (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
928
                          (match_operand:QI 1 "general_operand" "g")
929
                          (match_operand:SI 2 "general_operand" "nrmT"))
930
         (match_operand:SI 3 "general_operand" "nrmT")))]
931
  ""
932
  "cmpv %2,%1,%0,%3")
933
 
934
(define_insn ""
935
  [(set (cc0)
936
        (compare
937
         (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
938
                          (match_operand:QI 1 "general_operand" "g")
939
                          (match_operand:SI 2 "general_operand" "nrmT"))
940
         (match_operand:SI 3 "general_operand" "nrmT")))]
941
  ""
942
  "cmpzv %2,%1,%0,%3")
943
 
944
(define_insn "extv"
945
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
946
        (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
947
                         (match_operand:QI 2 "general_operand" "g")
948
                         (match_operand:SI 3 "general_operand" "nrmT")))]
949
  ""
950
  "*
951
{
952
  if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
953
      || !CONST_INT_P (operands[3])
954
      || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
955
      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
956
      || side_effects_p (operands[1])
957
      || (MEM_P (operands[1])
958
          && mode_dependent_address_p (XEXP (operands[1], 0))))
959
    return \"extv %3,%2,%1,%0\";
960
  if (INTVAL (operands[2]) == 8)
961
    return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
962
  return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
963
}")
964
 
965
(define_expand "extzv"
966
  [(set (match_operand:SI 0 "general_operand" "")
967
        (zero_extract:SI (match_operand:SI 1 "general_operand" "")
968
                         (match_operand:QI 2 "general_operand" "")
969
                         (match_operand:SI 3 "general_operand" "")))]
970
  ""
971
  "")
972
 
973
(define_insn ""
974
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
975
        (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
976
                         (match_operand:QI 2 "general_operand" "g")
977
                         (match_operand:SI 3 "general_operand" "nrmT")))]
978
  ""
979
  "*
980
{
981
  if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
982
      || !CONST_INT_P (operands[3])
983
      || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
984
      || side_effects_p (operands[1])
985
      || (MEM_P (operands[1])
986
          && mode_dependent_address_p (XEXP (operands[1], 0))))
987
    return \"extzv %3,%2,%1,%0\";
988
  if (INTVAL (operands[2]) == 8)
989
    return \"rotl %R3,%1,%0\;movzbl %0,%0\";
990
  if (INTVAL (operands[2]) == 16)
991
    return \"rotl %R3,%1,%0\;movzwl %0,%0\";
992
  if (MEM_P (operands[1])
993
      && GET_CODE (XEXP (operands[1], 0)) == PLUS
994
      && REG_P (XEXP (XEXP (operands[1], 0), 0))
995
      && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
996
      && CONST_INT_P (operands[2])
997
      && CONST_INT_P (operands[3]))
998
    {
999
      HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1000
      HOST_WIDE_INT l = INTVAL (operands[2]);
1001
      HOST_WIDE_INT v = INTVAL (operands[3]);
1002
      if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1003
        {
1004
          rtx tmp;
1005
          tmp = XEXP (XEXP (operands[1], 0), 0);
1006
          if (o & ~3)
1007
            tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1008
          operands[1] = gen_rtx_MEM (QImode, tmp);
1009
          operands[3] = GEN_INT (v + (o & 3) * 8);
1010
        }
1011
      if (optimize_size)
1012
        return \"extzv %3,%2,%1,%0\";
1013
    }
1014
  return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1015
}")
1016
 
1017
(define_expand "insv"
1018
  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1019
                         (match_operand:QI 1 "general_operand" "")
1020
                         (match_operand:SI 2 "general_operand" ""))
1021
        (match_operand:SI 3 "general_operand" ""))]
1022
  ""
1023
  "")
1024
 
1025
(define_insn ""
1026
  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1027
                         (match_operand:QI 1 "general_operand" "g")
1028
                         (match_operand:SI 2 "general_operand" "nrmT"))
1029
        (match_operand:SI 3 "general_operand" "nrmT"))]
1030
  ""
1031
  "*
1032
{
1033
  if (MEM_P (operands[0])
1034
      && GET_CODE (XEXP (operands[0], 0)) == PLUS
1035
      && REG_P (XEXP (XEXP (operands[0], 0), 0))
1036
      && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
1037
      && CONST_INT_P (operands[1])
1038
      && CONST_INT_P (operands[2]))
1039
    {
1040
      HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1041
      HOST_WIDE_INT v = INTVAL (operands[2]);
1042
      HOST_WIDE_INT l = INTVAL (operands[1]);
1043
      if ((o & 3) && (o & 3) * 8 + v + l <= 32)
1044
        {
1045
          rtx tmp;
1046
          tmp = XEXP (XEXP (operands[0], 0), 0);
1047
          if (o & ~3)
1048
            tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
1049
          operands[0] = gen_rtx_MEM (QImode, tmp);
1050
          operands[2] = GEN_INT (v + (o & 3) * 8);
1051
        }
1052
    }
1053
  return \"insv %3,%2,%1,%0\";
1054
}")
1055
 
1056
(define_insn ""
1057
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1058
                         (match_operand:QI 1 "general_operand" "g")
1059
                         (match_operand:SI 2 "general_operand" "nrmT"))
1060
        (match_operand:SI 3 "general_operand" "nrmT"))]
1061
  ""
1062
  "insv %3,%2,%1,%0")
1063
 
1064
;; Unconditional jump
1065
(define_insn "jump"
1066
  [(set (pc)
1067
        (label_ref (match_operand 0 "" "")))]
1068
  ""
1069
  "jbr %l0")
1070
 
1071
;; Conditional jumps
1072
 
1073
(define_expand "cbranch4"
1074
  [(set (cc0)
1075
        (compare (match_operand:VAXint 1 "nonimmediate_operand" "")
1076
                 (match_operand:VAXint 2 "general_operand" "")))
1077
   (set (pc)
1078
        (if_then_else
1079
              (match_operator 0 "ordered_comparison_operator" [(cc0)
1080
                                                               (const_int 0)])
1081
              (label_ref (match_operand 3 "" ""))
1082
              (pc)))]
1083
 "")
1084
 
1085
(define_expand "cbranch4"
1086
  [(set (cc0)
1087
        (compare (match_operand:VAXfp 1 "general_operand" "")
1088
                 (match_operand:VAXfp 2 "general_operand" "")))
1089
   (set (pc)
1090
        (if_then_else
1091
              (match_operator 0 "ordered_comparison_operator" [(cc0)
1092
                                                               (const_int 0)])
1093
              (label_ref (match_operand 3 "" ""))
1094
              (pc)))]
1095
 "")
1096
 
1097
(define_insn "*branch"
1098
  [(set (pc)
1099
        (if_then_else (match_operator 0 "ordered_comparison_operator"
1100
                                      [(cc0)
1101
                                       (const_int 0)])
1102
                      (label_ref (match_operand 1 "" ""))
1103
                      (pc)))]
1104
  ""
1105
  "j%c0 %l1")
1106
 
1107
;; Recognize reversed jumps.
1108
(define_insn "*branch_reversed"
1109
  [(set (pc)
1110
        (if_then_else (match_operator 0 "ordered_comparison_operator"
1111
                                      [(cc0)
1112
                                       (const_int 0)])
1113
                      (pc)
1114
                      (label_ref (match_operand 1 "" ""))))]
1115
  ""
1116
  "j%C0 %l1") ; %C0 negates condition
1117
 
1118
;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
1119
;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
1120
;; memory, we use QImode in the insn.  So we can't use those instructions
1121
;; for mode-dependent addresses.
1122
 
1123
(define_insn ""
1124
  [(set (pc)
1125
        (if_then_else
1126
         (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1127
                              (const_int 1)
1128
                              (match_operand:SI 1 "general_operand" "I,nrmT"))
1129
             (const_int 0))
1130
         (label_ref (match_operand 2 "" ""))
1131
         (pc)))]
1132
  ""
1133
  "@
1134
   jlbs %0,%l2
1135
   jbs %1,%0,%l2")
1136
 
1137
(define_insn ""
1138
  [(set (pc)
1139
        (if_then_else
1140
         (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1141
                              (const_int 1)
1142
                              (match_operand:SI 1 "general_operand" "I,nrmT"))
1143
             (const_int 0))
1144
         (label_ref (match_operand 2 "" ""))
1145
         (pc)))]
1146
  ""
1147
  "@
1148
   jlbc %0,%l2
1149
   jbc %1,%0,%l2")
1150
 
1151
(define_insn ""
1152
  [(set (pc)
1153
        (if_then_else
1154
         (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1155
                              (const_int 1)
1156
                              (match_operand:SI 1 "general_operand" "I,nrmT"))
1157
             (const_int 0))
1158
         (label_ref (match_operand 2 "" ""))
1159
         (pc)))]
1160
  ""
1161
  "@
1162
   jlbs %0,%l2
1163
   jbs %1,%0,%l2")
1164
 
1165
(define_insn ""
1166
  [(set (pc)
1167
        (if_then_else
1168
         (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1169
                              (const_int 1)
1170
                              (match_operand:SI 1 "general_operand" "I,nrmT"))
1171
             (const_int 0))
1172
         (label_ref (match_operand 2 "" ""))
1173
         (pc)))]
1174
  ""
1175
  "@
1176
   jlbc %0,%l2
1177
   jbc %1,%0,%l2")
1178
 
1179
;; Subtract-and-jump and Add-and-jump insns.
1180
;; These are not used when output is for the Unix assembler
1181
;; because it does not know how to modify them to reach far.
1182
 
1183
;; Normal sob insns.
1184
 
1185
(define_insn ""
1186
  [(set (pc)
1187
        (if_then_else
1188
         (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1189
                      (const_int -1))
1190
             (const_int 0))
1191
         (label_ref (match_operand 1 "" ""))
1192
         (pc)))
1193
   (set (match_dup 0)
1194
        (plus:SI (match_dup 0)
1195
                 (const_int -1)))]
1196
  "!TARGET_UNIX_ASM"
1197
  "jsobgtr %0,%l1")
1198
 
1199
(define_insn ""
1200
  [(set (pc)
1201
        (if_then_else
1202
         (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1203
                      (const_int -1))
1204
             (const_int 0))
1205
         (label_ref (match_operand 1 "" ""))
1206
         (pc)))
1207
   (set (match_dup 0)
1208
        (plus:SI (match_dup 0)
1209
                 (const_int -1)))]
1210
  "!TARGET_UNIX_ASM"
1211
  "jsobgeq %0,%l1")
1212
 
1213
;; Normal aob insns.  Define a version for when operands[1] is a constant.
1214
(define_insn ""
1215
  [(set (pc)
1216
        (if_then_else
1217
         (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1218
                      (const_int 1))
1219
             (match_operand:SI 1 "general_operand" "nrmT"))
1220
         (label_ref (match_operand 2 "" ""))
1221
         (pc)))
1222
   (set (match_dup 0)
1223
        (plus:SI (match_dup 0)
1224
                 (const_int 1)))]
1225
  "!TARGET_UNIX_ASM"
1226
  "jaoblss %1,%0,%l2")
1227
 
1228
(define_insn ""
1229
  [(set (pc)
1230
        (if_then_else
1231
         (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1232
             (match_operand:SI 1 "general_operand" "nrmT"))
1233
         (label_ref (match_operand 2 "" ""))
1234
         (pc)))
1235
   (set (match_dup 0)
1236
        (plus:SI (match_dup 0)
1237
                 (const_int 1)))]
1238
  "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
1239
  "jaoblss %P1,%0,%l2")
1240
 
1241
(define_insn ""
1242
  [(set (pc)
1243
        (if_then_else
1244
         (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1245
                      (const_int 1))
1246
             (match_operand:SI 1 "general_operand" "nrmT"))
1247
         (label_ref (match_operand 2 "" ""))
1248
         (pc)))
1249
   (set (match_dup 0)
1250
        (plus:SI (match_dup 0)
1251
                 (const_int 1)))]
1252
  "!TARGET_UNIX_ASM"
1253
  "jaobleq %1,%0,%l2")
1254
 
1255
(define_insn ""
1256
  [(set (pc)
1257
        (if_then_else
1258
         (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1259
             (match_operand:SI 1 "general_operand" "nrmT"))
1260
         (label_ref (match_operand 2 "" ""))
1261
         (pc)))
1262
   (set (match_dup 0)
1263
        (plus:SI (match_dup 0)
1264
                 (const_int 1)))]
1265
  "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
1266
  "jaobleq %P1,%0,%l2")
1267
 
1268
;; Something like a sob insn, but compares against -1.
1269
;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1270
 
1271
(define_insn ""
1272
  [(set (pc)
1273
        (if_then_else
1274
         (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1275
             (const_int 0))
1276
         (label_ref (match_operand 1 "" ""))
1277
         (pc)))
1278
   (set (match_dup 0)
1279
        (plus:SI (match_dup 0)
1280
                 (const_int -1)))]
1281
  ""
1282
  "decl %0\;jgequ %l1")
1283
 
1284
(define_expand "call_pop"
1285
  [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1286
                    (match_operand:SI 1 "const_int_operand" ""))
1287
              (set (reg:SI VAX_SP_REGNUM)
1288
                   (plus:SI (reg:SI VAX_SP_REGNUM)
1289
                            (match_operand:SI 3 "immediate_operand" "")))])]
1290
  ""
1291
{
1292
  gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
1293
 
1294
  /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1295
     during EH unwinding.  We must include the argument count pushed by
1296
     the calls instruction.  */
1297
  operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1298
})
1299
 
1300
(define_insn "*call_pop"
1301
  [(call (match_operand:QI 0 "memory_operand" "m")
1302
         (match_operand:SI 1 "const_int_operand" "n"))
1303
   (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1304
                                        (match_operand:SI 2 "immediate_operand" "i")))]
1305
  ""
1306
{
1307
  operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1308
  return "calls %1,%0";
1309
})
1310
 
1311
(define_expand "call_value_pop"
1312
  [(parallel [(set (match_operand 0 "" "")
1313
                   (call (match_operand:QI 1 "memory_operand" "")
1314
                         (match_operand:SI 2 "const_int_operand" "")))
1315
              (set (reg:SI VAX_SP_REGNUM)
1316
                   (plus:SI (reg:SI VAX_SP_REGNUM)
1317
                            (match_operand:SI 4 "immediate_operand" "")))])]
1318
  ""
1319
{
1320
  gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
1321
 
1322
  /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1323
     during EH unwinding.  We must include the argument count pushed by
1324
     the calls instruction.  */
1325
  operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1326
})
1327
 
1328
(define_insn "*call_value_pop"
1329
  [(set (match_operand 0 "" "")
1330
        (call (match_operand:QI 1 "memory_operand" "m")
1331
              (match_operand:SI 2 "const_int_operand" "n")))
1332
   (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
1333
                                        (match_operand:SI 3 "immediate_operand" "i")))]
1334
  ""
1335
  "*
1336
{
1337
  operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1338
  return \"calls %2,%1\";
1339
}")
1340
 
1341
(define_expand "call"
1342
  [(call (match_operand:QI 0 "memory_operand" "")
1343
      (match_operand:SI 1 "const_int_operand" ""))]
1344
  ""
1345
  "
1346
{
1347
  /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1348
     during EH unwinding.  We must include the argument count pushed by
1349
     the calls instruction.  */
1350
  operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1351
}")
1352
 
1353
(define_insn "*call"
1354
   [(call (match_operand:QI 0 "memory_operand" "m")
1355
       (match_operand:SI 1 "const_int_operand" ""))]
1356
  ""
1357
  "calls $0,%0")
1358
 
1359
(define_expand "call_value"
1360
  [(set (match_operand 0 "" "")
1361
      (call (match_operand:QI 1 "memory_operand" "")
1362
            (match_operand:SI 2 "const_int_operand" "")))]
1363
  ""
1364
  "
1365
{
1366
  /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1367
     during EH unwinding.  We must include the argument count pushed by
1368
     the calls instruction.  */
1369
  operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1370
}")
1371
 
1372
(define_insn "*call_value"
1373
  [(set (match_operand 0 "" "")
1374
        (call (match_operand:QI 1 "memory_operand" "m")
1375
              (match_operand:SI 2 "const_int_operand" "")))]
1376
  ""
1377
  "calls $0,%1")
1378
 
1379
;; Call subroutine returning any type.
1380
 
1381
(define_expand "untyped_call"
1382
  [(parallel [(call (match_operand 0 "" "")
1383
              (const_int 0))
1384
              (match_operand 1 "" "")
1385
              (match_operand 2 "" "")])]
1386
  ""
1387
  "
1388
{
1389
  int i;
1390
 
1391
  emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1392
 
1393
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
1394
    {
1395
      rtx set = XVECEXP (operands[2], 0, i);
1396
      emit_move_insn (SET_DEST (set), SET_SRC (set));
1397
    }
1398
 
1399
  /* The optimizer does not know that the call sets the function value
1400
     registers we stored in the result block.  We avoid problems by
1401
     claiming that all hard registers are used and clobbered at this
1402
     point.  */
1403
  emit_insn (gen_blockage ());
1404
 
1405
  DONE;
1406
}")
1407
 
1408
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1409
;; all of memory.  This blocks insns from being moved across this point.
1410
 
1411
(define_insn "blockage"
1412
  [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1413
  ""
1414
  "")
1415
 
1416
(define_insn "procedure_entry_mask"
1417
  [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)]
1418
  ""
1419
  ".word %x0")
1420
 
1421
(define_insn "return"
1422
  [(return)]
1423
  ""
1424
  "ret")
1425
 
1426
(define_expand "prologue"
1427
  [(const_int 0)]
1428
  ""
1429
{
1430
  vax_expand_prologue ();
1431
  DONE;
1432
})
1433
 
1434
(define_expand "epilogue"
1435
  [(return)]
1436
  ""
1437
  "
1438
{
1439
  emit_jump_insn (gen_return ());
1440
  DONE;
1441
}")
1442
 
1443
(define_insn "nop"
1444
  [(const_int 0)]
1445
  ""
1446
  "nop")
1447
 
1448
;; This had a wider constraint once, and it had trouble.
1449
;; If you are tempted to try `g', please don't--it's not worth
1450
;; the risk we will reopen the same bug.
1451
(define_insn "indirect_jump"
1452
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1453
  ""
1454
  "jmp (%0)")
1455
 
1456
;; This is here to accept 5 arguments (as passed by expand_end_case)
1457
;; and pass the first 4 along to the casesi1 pattern that really does
1458
;; the actual casesi work.  We emit a jump here to the default label
1459
;; _before_ the casesi so that we can be sure that the casesi never
1460
;; drops through.
1461
;; This is suboptimal perhaps, but so is much of the rest of this
1462
;; machine description.  For what it's worth, HPPA uses the same trick.
1463
;;
1464
;; operand 0 is index
1465
;; operand 1 is the minimum bound (a const_int)
1466
;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1467
;; operand 3 is CODE_LABEL for the table;
1468
;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1469
;;
1470
;; We emit:
1471
;;      i = index - minimum_bound
1472
;;      if (i > (maximum_bound - minimum_bound + 1) goto default;
1473
;;      casesi (i, 0, table);
1474
;;
1475
(define_expand "casesi"
1476
  [(match_operand:SI 0 "general_operand" "")
1477
   (match_operand:SI 1 "general_operand" "")
1478
   (match_operand:SI 2 "general_operand" "")
1479
   (match_operand 3 "" "")
1480
   (match_operand 4 "" "")]
1481
  ""
1482
{
1483
  rtx test;
1484
 
1485
  /* i = index - minimum_bound;
1486
     But only if the lower bound is not already zero.  */
1487
  if (operands[1] != const0_rtx)
1488
    {
1489
      rtx index = gen_reg_rtx (SImode);
1490
      emit_insn (gen_addsi3 (index,
1491
                             operands[0],
1492
                             GEN_INT (-INTVAL (operands[1]))));
1493
      operands[0] = index;
1494
    }
1495
 
1496
  /* if (i > (maximum_bound - minimum_bound + 1)) goto default;  */
1497
  test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
1498
  emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
1499
 
1500
  /* casesi (i, 0, table);  */
1501
  emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
1502
  DONE;
1503
})
1504
 
1505
;; This insn is a bit of a lier.  It actually falls through if no case
1506
;; matches.  But, we prevent that from ever happening by emitting a jump
1507
;; before this, see the define_expand above.
1508
(define_insn "casesi1"
1509
  [(match_operand:SI 1 "const_int_operand" "n")
1510
   (set (pc)
1511
        (plus:SI (sign_extend:SI
1512
                  (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT")
1513
                                            (const_int 2))
1514
                          (pc))))
1515
                 (label_ref:SI (match_operand 2 "" ""))))]
1516
  ""
1517
  "casel %0,$0,%1")
1518
 
1519
(define_insn "pushextsym"
1520
  [(set (match_operand:SI 0 "push_operand" "=g")
1521
        (match_operand:SI 1 "external_symbolic_operand" "i"))]
1522
  ""
1523
  "pushab %a1")
1524
 
1525
(define_insn "movextsym"
1526
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1527
        (match_operand:SI 1 "external_symbolic_operand" "i"))]
1528
  ""
1529
  "movab %a1,%0")
1530
 
1531
(define_insn "pushlclsym"
1532
  [(set (match_operand:SI 0 "push_operand" "=g")
1533
        (match_operand:SI 1 "local_symbolic_operand" "i"))]
1534
  ""
1535
  "pushab %a1")
1536
 
1537
(define_insn "movlclsym"
1538
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1539
        (match_operand:SI 1 "local_symbolic_operand" "i"))]
1540
  ""
1541
  "movab %a1,%0")
1542
 
1543
;;- load or push effective address
1544
;; These come after the move and add/sub patterns
1545
;; because we don't want pushl $1 turned into pushad 1.
1546
;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
1547
 
1548
;; It does not work to use constraints to distinguish pushes from moves,
1549
;; because < matches any autodecrement, not just a push.
1550
 
1551
(define_insn "pushaddr"
1552
  [(set (match_operand:SI 0 "push_operand" "=g")
1553
        (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1554
  ""
1555
  "pusha %a1")
1556
 
1557
(define_insn "movaddr"
1558
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1559
        (match_operand:VAXintQHSD 1 "address_operand" "p"))]
1560
  ""
1561
  "mova %a1,%0")
1562
 
1563
(define_insn "pushaddr"
1564
  [(set (match_operand:SI 0 "push_operand" "=g")
1565
        (match_operand:VAXfp 1 "address_operand" "p"))]
1566
  ""
1567
  "pusha %a1")
1568
 
1569
(define_insn "movaddr"
1570
  [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1571
        (match_operand:VAXfp 1 "address_operand" "p"))]
1572
  ""
1573
  "mova %a1,%0")
1574
 
1575
;; These used to be peepholes, but it is more straightforward to do them
1576
;; as single insns.  However, we must force the output to be a register
1577
;; if it is not an offsettable address so that we know that we can assign
1578
;; to it twice.
1579
 
1580
;; If we had a good way of evaluating the relative costs, these could be
1581
;; machine-independent.
1582
 
1583
;; Optimize   extzv ...,z;    andl2 ...,z
1584
;; or         ashl ...,z;     andl2 ...,z
1585
;; with other operands constant.  This is what the combiner converts the
1586
;; above sequences to before attempting to recognize the new insn.
1587
 
1588
(define_insn ""
1589
  [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1590
        (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1591
                             (match_operand:QI 2 "const_int_operand" "n"))
1592
                (match_operand:SI 3 "const_int_operand" "n")))]
1593
  "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
1594
  "*
1595
{
1596
  unsigned long mask1 = INTVAL (operands[3]);
1597
  unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
1598
 
1599
  if ((mask1 & mask2) != mask1)
1600
    operands[3] = GEN_INT (mask1 & mask2);
1601
 
1602
  return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
1603
}")
1604
 
1605
;; left-shift and mask
1606
;; The only case where `ashl' is better is if the mask only turns off
1607
;; bits that the ashl would anyways, in which case it should have been
1608
;; optimized away.
1609
 
1610
(define_insn ""
1611
  [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
1612
        (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1613
                           (match_operand:QI 2 "const_int_operand" "n"))
1614
                (match_operand:SI 3 "const_int_operand" "n")))]
1615
  ""
1616
  "*
1617
{
1618
  operands[3]
1619
    = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
1620
  return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
1621
}")
1622
 
1623
;; Instruction sequence to sync the VAX instruction stream.
1624
(define_insn "sync_istream"
1625
  [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
1626
  ""
1627
  "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
1628
 
1629
(define_expand "nonlocal_goto"
1630
  [(use (match_operand 0 "general_operand" ""))
1631
   (use (match_operand 1 "general_operand" ""))
1632
   (use (match_operand 2 "general_operand" ""))
1633
   (use (match_operand 3 "general_operand" ""))]
1634
  ""
1635
{
1636
  rtx lab = operands[1];
1637
  rtx stack = operands[2];
1638
  rtx fp = operands[3];
1639
 
1640
  emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
1641
  emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
1642
 
1643
  emit_move_insn (hard_frame_pointer_rtx, fp);
1644
  emit_stack_restore (SAVE_NONLOCAL, stack);
1645
 
1646
  emit_use (hard_frame_pointer_rtx);
1647
  emit_use (stack_pointer_rtx);
1648
 
1649
  /* We'll convert this to direct jump via a peephole optimization.  */
1650
  emit_indirect_jump (copy_to_reg (lab));
1651
  emit_barrier ();
1652
  DONE;
1653
})

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