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/* IRA hard register and memory cost calculation for allocnos or pseudos.

   Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012

   Free Software Foundation, Inc.

   Contributed by Vladimir Makarov <vmakarov@redhat.com>.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under

the terms of the GNU General Public License as published by the Free

Software Foundation; either version 3, or (at your option) any later

version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY

WARRANTY; without even the implied warranty of MERCHANTABILITY or

FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

for more details.

You should have received a copy of the GNU General Public License

along with GCC; see the file COPYING3.  If not see

<http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "hard-reg-set.h"

#include "rtl.h"

#include "expr.h"

#include "tm_p.h"

#include "flags.h"

#include "basic-block.h"

#include "regs.h"

#include "addresses.h"

#include "insn-config.h"

#include "recog.h"

#include "reload.h"

#include "diagnostic-core.h"

#include "target.h"

#include "params.h"

#include "ira-int.h"

/* The flags is set up every time when we calculate pseudo register

   classes through function ira_set_pseudo_classes.  */

static bool pseudo_classes_defined_p = false;

/* TRUE if we work with allocnos.  Otherwise we work with pseudos.  */

static bool allocno_p;

/* Number of elements in array `costs'.  */

static int cost_elements_num;

/* The `costs' struct records the cost of using hard registers of each

   class considered for the calculation and of using memory for each

   allocno or pseudo.  */

struct costs

{

  int mem_cost;

  /* Costs for register classes start here.  We process only some

     allocno classes.  */

  int cost[1];

};

#define max_struct_costs_size \

  (this_target_ira_int->x_max_struct_costs_size)

#define init_cost \

  (this_target_ira_int->x_init_cost)

#define temp_costs \

  (this_target_ira_int->x_temp_costs)

#define op_costs \

  (this_target_ira_int->x_op_costs)

#define this_op_costs \

  (this_target_ira_int->x_this_op_costs)

/* Costs of each class for each allocno or pseudo.  */

static struct costs *costs;

/* Accumulated costs of each class for each allocno.  */

static struct costs *total_allocno_costs;

/* It is the current size of struct costs.  */

static int struct_costs_size;

/* Return pointer to structure containing costs of allocno or pseudo

   with given NUM in array ARR.  */

#define COSTS(arr, num) \

  ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))

/* Return index in COSTS when processing reg with REGNO.  */

#define COST_INDEX(regno) (allocno_p                                         \

                           ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \

                           : (int) regno)

/* Record register class preferences of each allocno or pseudo.  Null

   value means no preferences.  It happens on the 1st iteration of the

   cost calculation.  */

static enum reg_class *pref;

/* Allocated buffers for pref.  */

static enum reg_class *pref_buffer;

/* Record allocno class of each allocno with the same regno.  */

static enum reg_class *regno_aclass;

/* Record cost gains for not allocating a register with an invariant

   equivalence.  */

static int *regno_equiv_gains;

/* Execution frequency of the current insn.  */

static int frequency;

/* Info about reg classes whose costs are calculated for a pseudo.  */

struct cost_classes

{

  /* Number of the cost classes in the subsequent array.  */

  int num;

  /* Container of the cost classes.  */

  enum reg_class classes[N_REG_CLASSES];

  /* Map reg class -> index of the reg class in the previous array.

     -1 if it is not a cost classe.  */

  int index[N_REG_CLASSES];

  /* Map hard regno index of first class in array CLASSES containing

     the hard regno, -1 otherwise.  */

  int hard_regno_index[FIRST_PSEUDO_REGISTER];

};

/* Types of pointers to the structure above.  */

typedef struct cost_classes *cost_classes_t;

typedef const struct cost_classes *const_cost_classes_t;

/* Info about cost classes for each pseudo.  */

static cost_classes_t *regno_cost_classes;

/* Returns hash value for cost classes info V.  */

static hashval_t

cost_classes_hash (const void *v)

{

  const_cost_classes_t hv = (const_cost_classes_t) v;

  return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0);

}

/* Compares cost classes info V1 and V2.  */

static int

cost_classes_eq (const void *v1, const void *v2)

{

  const_cost_classes_t hv1 = (const_cost_classes_t) v1;

  const_cost_classes_t hv2 = (const_cost_classes_t) v2;

  return hv1->num == hv2->num && memcmp (hv1->classes, hv2->classes,

                                         sizeof (enum reg_class) * hv1->num);

}

/* Delete cost classes info V from the hash table.  */

static void

cost_classes_del (void *v)

{

  ira_free (v);

}

/* Hash table of unique cost classes.  */

static htab_t cost_classes_htab;

/* Map allocno class -> cost classes for pseudo of given allocno

   class.  */

static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES];

/* Map mode -> cost classes for pseudo of give mode.  */

static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE];

/* Initialize info about the cost classes for each pseudo.  */

static void

initiate_regno_cost_classes (void)

{

  int size = sizeof (cost_classes_t) * max_reg_num ();

  regno_cost_classes = (cost_classes_t *) ira_allocate (size);

  memset (regno_cost_classes, 0, size);

  memset (cost_classes_aclass_cache, 0,

          sizeof (cost_classes_t) * N_REG_CLASSES);

  memset (cost_classes_mode_cache, 0,

          sizeof (cost_classes_t) * MAX_MACHINE_MODE);

  cost_classes_htab

    = htab_create (200, cost_classes_hash, cost_classes_eq, cost_classes_del);

}

/* Create new cost classes from cost classes FROM and set up members

   index and hard_regno_index.  Return the new classes.  The function

   implements some common code of two functions

   setup_regno_cost_classes_by_aclass and

   setup_regno_cost_classes_by_mode.  */

static cost_classes_t

setup_cost_classes (cost_classes_t from)

{

  cost_classes_t classes_ptr;

  enum reg_class cl;

  int i, j, hard_regno;

  classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes));

  classes_ptr->num = from->num;

  for (i = 0; i < N_REG_CLASSES; i++)

    classes_ptr->index[i] = -1;

  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

    classes_ptr->hard_regno_index[i] = -1;

  for (i = 0; i < from->num; i++)

    {

      cl = classes_ptr->classes[i] = from->classes[i];

      classes_ptr->index[cl] = i;

      for (j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--)

        {

          hard_regno = ira_class_hard_regs[cl][j];

          if (classes_ptr->hard_regno_index[hard_regno] < 0)

            classes_ptr->hard_regno_index[hard_regno] = i;

        }

    }

  return classes_ptr;

}

/* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.

   This function is used when we know an initial approximation of

   allocno class of the pseudo already, e.g. on the second iteration

   of class cost calculation or after class cost calculation in

   register-pressure sensitive insn scheduling or register-pressure

   sensitive loop-invariant motion.  */

static void

setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass)

{

  static struct cost_classes classes;

  cost_classes_t classes_ptr;

  enum reg_class cl;

  int i;

  PTR *slot;

  HARD_REG_SET temp, temp2;

  bool exclude_p;

  if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL)

    {

      COPY_HARD_REG_SET (temp, reg_class_contents[aclass]);

      AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);

      /* We exclude classes from consideration which are subsets of

         ACLASS only if ACLASS is a pressure class or subset of a

         pressure class.  It means by the definition of pressure classes

         that cost of moving between susbets of ACLASS is cheaper than

         load or store.  */

      for (i = 0; i < ira_pressure_classes_num; i++)

        {

          cl = ira_pressure_classes[i];

          if (cl == aclass)

            break;

          COPY_HARD_REG_SET (temp2, reg_class_contents[cl]);

          AND_COMPL_HARD_REG_SET (temp2, ira_no_alloc_regs);

          if (hard_reg_set_subset_p (temp, temp2))

            break;

        }

      exclude_p = i < ira_pressure_classes_num;

      classes.num = 0;

      for (i = 0; i < ira_important_classes_num; i++)

        {

          cl = ira_important_classes[i];

          if (exclude_p)

            {

              /* Exclude no-pressure classes which are subsets of

                 ACLASS.  */

              COPY_HARD_REG_SET (temp2, reg_class_contents[cl]);

              AND_COMPL_HARD_REG_SET (temp2, ira_no_alloc_regs);

              if (! ira_reg_pressure_class_p[cl]

                  && hard_reg_set_subset_p (temp2, temp) && cl != aclass)

                continue;

            }

          classes.classes[classes.num++] = cl;

        }

      slot = htab_find_slot (cost_classes_htab, &classes, INSERT);

      if (*slot == NULL)

        {

          classes_ptr = setup_cost_classes (&classes);

          *slot = classes_ptr;

        }

      classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot;

    }

  regno_cost_classes[regno] = classes_ptr;

}

/* Setup cost classes for pseudo REGNO with MODE.  Usage of MODE can

   decrease number of cost classes for the pseudo, if hard registers

   of some important classes can not hold a value of MODE.  So the

   pseudo can not get hard register of some important classes and cost

   calculation for such important classes is only waisting CPU

   time.  */

static void

setup_regno_cost_classes_by_mode (int regno, enum machine_mode mode)

{

  static struct cost_classes classes;

  cost_classes_t classes_ptr;

  enum reg_class cl;

  int i;

  PTR *slot;

  HARD_REG_SET temp;

  if ((classes_ptr = cost_classes_mode_cache[mode]) == NULL)

    {

      classes.num = 0;

      for (i = 0; i < ira_important_classes_num; i++)

        {

          cl = ira_important_classes[i];

          COPY_HARD_REG_SET (temp, ira_prohibited_class_mode_regs[cl][mode]);

          IOR_HARD_REG_SET (temp, ira_no_alloc_regs);

          if (hard_reg_set_subset_p (reg_class_contents[cl], temp))

            continue;

          classes.classes[classes.num++] = cl;

        }

      slot = htab_find_slot (cost_classes_htab, &classes, INSERT);

      if (*slot == NULL)

        {

          classes_ptr = setup_cost_classes (&classes);

          *slot = classes_ptr;

        }

      else

        classes_ptr = (cost_classes_t) *slot;

      cost_classes_mode_cache[mode] = (cost_classes_t) *slot;

    }

  regno_cost_classes[regno] = classes_ptr;

}

/* Finilize info about the cost classes for each pseudo.  */

static void

finish_regno_cost_classes (void)

{

  ira_free (regno_cost_classes);

  htab_delete (cost_classes_htab);

}

/* Compute the cost of loading X into (if TO_P is TRUE) or from (if

   TO_P is FALSE) a register of class RCLASS in mode MODE.  X must not

   be a pseudo register.  */

static int

copy_cost (rtx x, enum machine_mode mode, reg_class_t rclass, bool to_p,

           secondary_reload_info *prev_sri)

{

  secondary_reload_info sri;

  reg_class_t secondary_class = NO_REGS;

  /* If X is a SCRATCH, there is actually nothing to move since we are

     assuming optimal allocation.  */

  if (GET_CODE (x) == SCRATCH)

    return 0;

  /* Get the class we will actually use for a reload.  */

  rclass = targetm.preferred_reload_class (x, rclass);

  /* If we need a secondary reload for an intermediate, the cost is

     that to load the input into the intermediate register, then to

     copy it.  */

  sri.prev_sri = prev_sri;

  sri.extra_cost = 0;

  secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);

  if (secondary_class != NO_REGS)

    {

      if (!move_cost[mode])

        init_move_cost (mode);

      return (move_cost[mode][(int) secondary_class][(int) rclass]

              + sri.extra_cost

              + copy_cost (x, mode, secondary_class, to_p, &sri));

    }

  /* For memory, use the memory move cost, for (hard) registers, use

     the cost to move between the register classes, and use 2 for

     everything else (constants).  */

  if (MEM_P (x) || rclass == NO_REGS)

    return sri.extra_cost

           + ira_memory_move_cost[mode][(int) rclass][to_p != 0];

  else if (REG_P (x))

    {

      if (!move_cost[mode])

        init_move_cost (mode);

      return (sri.extra_cost

              + move_cost[mode][REGNO_REG_CLASS (REGNO (x))][(int) rclass]);

    }

  else

    /* If this is a constant, we may eventually want to call rtx_cost

       here.  */

    return sri.extra_cost + COSTS_N_INSNS (1);

}

/* Record the cost of using memory or hard registers of various

   classes for the operands in INSN.

   N_ALTS is the number of alternatives.

   N_OPS is the number of operands.

   OPS is an array of the operands.

   MODES are the modes of the operands, in case any are VOIDmode.

   CONSTRAINTS are the constraints to use for the operands.  This array

   is modified by this procedure.

   This procedure works alternative by alternative.  For each

   alternative we assume that we will be able to allocate all allocnos

   to their ideal register class and calculate the cost of using that

   alternative.  Then we compute, for each operand that is a

   pseudo-register, the cost of having the allocno allocated to each

   register class and using it in that alternative.  To this cost is

   added the cost of the alternative.

   The cost of each class for this insn is its lowest cost among all

   the alternatives.  */

static void

record_reg_classes (int n_alts, int n_ops, rtx *ops,

                    enum machine_mode *modes, const char **constraints,

                    rtx insn, enum reg_class *pref)

{

  int alt;

  int i, j, k;

  rtx set;

  int insn_allows_mem[MAX_RECOG_OPERANDS];

  for (i = 0; i < n_ops; i++)

    insn_allows_mem[i] = 0;

  /* Process each alternative, each time minimizing an operand's cost

     with the cost for each operand in that alternative.  */

  for (alt = 0; alt < n_alts; alt++)

    {

      enum reg_class classes[MAX_RECOG_OPERANDS];

      int allows_mem[MAX_RECOG_OPERANDS];

      enum reg_class rclass;

      int alt_fail = 0;

      int alt_cost = 0, op_cost_add;

      if (!recog_data.alternative_enabled_p[alt])

        {

          for (i = 0; i < recog_data.n_operands; i++)

            constraints[i] = skip_alternative (constraints[i]);

          continue;

        }

      for (i = 0; i < n_ops; i++)

        {

          unsigned char c;

          const char *p = constraints[i];

          rtx op = ops[i];

          enum machine_mode mode = modes[i];

          int allows_addr = 0;

          int win = 0;

          /* Initially show we know nothing about the register class.  */

          classes[i] = NO_REGS;

          allows_mem[i] = 0;

          /* If this operand has no constraints at all, we can

             conclude nothing about it since anything is valid.  */

          if (*p == 0)

            {

              if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)

                memset (this_op_costs[i], 0, struct_costs_size);

              continue;

            }

          /* If this alternative is only relevant when this operand

             matches a previous operand, we do different things

             depending on whether this operand is a allocno-reg or not.

             We must process any modifiers for the operand before we

             can make this test.  */

          while (*p == '%' || *p == '=' || *p == '+' || *p == '&')

            p++;

          if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))

            {

              /* Copy class and whether memory is allowed from the

                 matching alternative.  Then perform any needed cost

                 computations and/or adjustments.  */

              j = p[0] - '0';

              classes[i] = classes[j];

              allows_mem[i] = allows_mem[j];

              if (allows_mem[i])

                insn_allows_mem[i] = 1;

              if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)

                {

                  /* If this matches the other operand, we have no

                     added cost and we win.  */

                  if (rtx_equal_p (ops[j], op))

                    win = 1;

                  /* If we can put the other operand into a register,

                     add to the cost of this alternative the cost to

                     copy this operand to the register used for the

                     other operand.  */

                  else if (classes[j] != NO_REGS)

                    {

                      alt_cost += copy_cost (op, mode, classes[j], 1, NULL);

                      win = 1;

                    }

                }

              else if (! REG_P (ops[j])

                       || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)

                {

                  /* This op is an allocno but the one it matches is

                     not.  */

                  /* If we can't put the other operand into a

                     register, this alternative can't be used.  */

                  if (classes[j] == NO_REGS)

                    alt_fail = 1;

                  /* Otherwise, add to the cost of this alternative

                     the cost to copy the other operand to the hard

                     register used for this operand.  */

                  else

                    alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);

                }

              else

                {

                  /* The costs of this operand are not the same as the

                     other operand since move costs are not symmetric.

                     Moreover, if we cannot tie them, this alternative

                     needs to do a copy, which is one insn.  */

                  struct costs *pp = this_op_costs[i];

                  int *pp_costs = pp->cost;

                  cost_classes_t cost_classes_ptr

                    = regno_cost_classes[REGNO (op)];

                  enum reg_class *cost_classes = cost_classes_ptr->classes;

                  bool in_p = recog_data.operand_type[i] != OP_OUT;

                  bool out_p = recog_data.operand_type[i] != OP_IN;

                  enum reg_class op_class = classes[i];

                  move_table *move_in_cost, *move_out_cost;

                  ira_init_register_move_cost_if_necessary (mode);

                  if (! in_p)

                    {

                      ira_assert (out_p);

                      move_out_cost = ira_may_move_out_cost[mode];

                      for (k = cost_classes_ptr->num - 1; k >= 0; k--)

                        {

                          rclass = cost_classes[k];

                          pp_costs[k]

                            = move_out_cost[op_class][rclass] * frequency;

                        }

                    }

                  else if (! out_p)

                    {

                      ira_assert (in_p);

                      move_in_cost = ira_may_move_in_cost[mode];

                      for (k = cost_classes_ptr->num - 1; k >= 0; k--)

                        {

                          rclass = cost_classes[k];

                          pp_costs[k]

                            = move_in_cost[rclass][op_class] * frequency;

                        }

                    }

                  else

                    {

                      move_in_cost = ira_may_move_in_cost[mode];

                      move_out_cost = ira_may_move_out_cost[mode];

                      for (k = cost_classes_ptr->num - 1; k >= 0; k--)

                        {

                          rclass = cost_classes[k];

                          pp_costs[k] = ((move_in_cost[rclass][op_class]

                                          + move_out_cost[op_class][rclass])

                                         * frequency);

                        }

                    }

                  /* If the alternative actually allows memory, make

                     things a bit cheaper since we won't need an extra

                     insn to load it.  */

                  pp->mem_cost

                    = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)

                       + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)

                       - allows_mem[i]) * frequency;

                  /* If we have assigned a class to this allocno in

                     our first pass, add a cost to this alternative

                     corresponding to what we would add if this

                     allocno were not in the appropriate class.  */

                  if (pref)

                    {

                      enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];

                      if (pref_class == NO_REGS)

                        alt_cost

                          += ((out_p

                               ? ira_memory_move_cost[mode][op_class][0] : 0)

                              + (in_p

                                 ? ira_memory_move_cost[mode][op_class][1]

                                 : 0));

                      else if (ira_reg_class_intersect

                               [pref_class][op_class] == NO_REGS)

                        alt_cost

                          += ira_register_move_cost[mode][pref_class][op_class];

                    }

                  if (REGNO (ops[i]) != REGNO (ops[j])

                      && ! find_reg_note (insn, REG_DEAD, op))

                    alt_cost += 2;

                  /* This is in place of ordinary cost computation for

                     this operand, so skip to the end of the

                     alternative (should be just one character).  */

                  while (*p && *p++ != ',')

                    ;

                  constraints[i] = p;

                  continue;

                }

            }

          /* Scan all the constraint letters.  See if the operand

             matches any of the constraints.  Collect the valid

             register classes and see if this operand accepts

             memory.  */

          while ((c = *p))

            {

              switch (c)

                {

                case ',':

                  break;

                case '*':

                  /* Ignore the next letter for this pass.  */

                  c = *++p;

                  break;

                case '?':

                  alt_cost += 2;

                case '!':  case '#':  case '&':

                case '0':  case '1':  case '2':  case '3':  case '4':

                case '5':  case '6':  case '7':  case '8':  case '9':

                  break;

                case 'p':

                  allows_addr = 1;

                  win = address_operand (op, GET_MODE (op));

                  /* We know this operand is an address, so we want it

                     to be allocated to a register that can be the

                     base of an address, i.e. BASE_REG_CLASS.  */

                  classes[i]

                    = ira_reg_class_subunion[classes[i]]

                      [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,

                                       ADDRESS, SCRATCH)];

                  break;

                case 'm':  case 'o':  case 'V':

                  /* It doesn't seem worth distinguishing between

                     offsettable and non-offsettable addresses

                     here.  */

                  insn_allows_mem[i] = allows_mem[i] = 1;

                  if (MEM_P (op))

                    win = 1;

                  break;

                case '<':

                  if (MEM_P (op)

                      && (GET_CODE (XEXP (op, 0)) == PRE_DEC

                          || GET_CODE (XEXP (op, 0)) == POST_DEC))

                    win = 1;

                  break;

                case '>':

                  if (MEM_P (op)

                      && (GET_CODE (XEXP (op, 0)) == PRE_INC

                          || GET_CODE (XEXP (op, 0)) == POST_INC))

                    win = 1;

                  break;

                case 'E':

                case 'F':

                  if (GET_CODE (op) == CONST_DOUBLE

                      || (GET_CODE (op) == CONST_VECTOR

                          && (GET_MODE_CLASS (GET_MODE (op))

                              == MODE_VECTOR_FLOAT)))

                    win = 1;

                  break;

                case 'G':

                case 'H':