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/* Register renaming for the GNU compiler.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,

   2010 Free Software Foundation, Inc.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it

   under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 3, or (at your option)

   any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public

   License for more details.

   You should have received a copy of the GNU General Public License

   along with GCC; see the file COPYING3.  If not see

   <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "system.h"

#include "coretypes.h"

#include "tm.h"

#include "rtl-error.h"

#include "tm_p.h"

#include "insn-config.h"

#include "regs.h"

#include "addresses.h"

#include "hard-reg-set.h"

#include "basic-block.h"

#include "reload.h"

#include "output.h"

#include "function.h"

#include "recog.h"

#include "flags.h"

#include "obstack.h"

#include "timevar.h"

#include "tree-pass.h"

#include "df.h"

#include "target.h"

#include "emit-rtl.h"

#include "regrename.h"

/* This file implements the RTL register renaming pass of the compiler.  It is

   a semi-local pass whose goal is to maximize the usage of the register file

   of the processor by substituting registers for others in the solution given

   by the register allocator.  The algorithm is as follows:

     1. Local def/use chains are built: within each basic block, chains are

        opened and closed; if a chain isn't closed at the end of the block,

        it is dropped.  We pre-open chains if we have already examined a

        predecessor block and found chains live at the end which match

        live registers at the start of the new block.

     2. We try to combine the local chains across basic block boundaries by

        comparing chains that were open at the start or end of a block to

        those in successor/predecessor blocks.

     3. For each chain, the set of possible renaming registers is computed.

        This takes into account the renaming of previously processed chains.

        Optionally, a preferred class is computed for the renaming register.

     4. The best renaming register is computed for the chain in the above set,

        using a round-robin allocation.  If a preferred class exists, then the

        round-robin allocation is done within the class first, if possible.

        The round-robin allocation of renaming registers itself is global.

     5. If a renaming register has been found, it is substituted in the chain.

  Targets can parameterize the pass by specifying a preferred class for the

  renaming register for a given (super)class of registers to be renamed.  */

#if HOST_BITS_PER_WIDE_INT <= MAX_RECOG_OPERANDS

#error "Use a different bitmap implementation for untracked_operands."

#endif

enum scan_actions

{

  terminate_write,

  terminate_dead,

  mark_all_read,

  mark_read,

  mark_write,

  /* mark_access is for marking the destination regs in

     REG_FRAME_RELATED_EXPR notes (as if they were read) so that the

     note is updated properly.  */

  mark_access

};

static const char * const scan_actions_name[] =

{

  "terminate_write",

  "terminate_dead",

  "mark_all_read",

  "mark_read",

  "mark_write",

  "mark_access"

};

/* TICK and THIS_TICK are used to record the last time we saw each

   register.  */

static int tick[FIRST_PSEUDO_REGISTER];

static int this_tick = 0;

static struct obstack rename_obstack;

/* If nonnull, the code calling into the register renamer requested

   information about insn operands, and we store it here.  */

VEC(insn_rr_info, heap) *insn_rr;

static void scan_rtx (rtx, rtx *, enum reg_class, enum scan_actions,

                      enum op_type);

static bool build_def_use (basic_block);

/* The id to be given to the next opened chain.  */

static unsigned current_id;

/* A mapping of unique id numbers to chains.  */

static VEC(du_head_p, heap) *id_to_chain;

/* List of currently open chains.  */

static struct du_head *open_chains;

/* Bitmap of open chains.  The bits set always match the list found in

   open_chains.  */

static bitmap_head open_chains_set;

/* Record the registers being tracked in open_chains.  */

static HARD_REG_SET live_in_chains;

/* Record the registers that are live but not tracked.  The intersection

   between this and live_in_chains is empty.  */

static HARD_REG_SET live_hard_regs;

/* Set while scanning RTL if INSN_RR is nonnull, i.e. if the current analysis

   is for a caller that requires operand data.  Used in

   record_operand_use.  */

static operand_rr_info *cur_operand;

/* Return the chain corresponding to id number ID.  Take into account that

   chains may have been merged.  */

du_head_p

regrename_chain_from_id (unsigned int id)

{

  du_head_p first_chain = VEC_index (du_head_p, id_to_chain, id);

  du_head_p chain = first_chain;

  while (chain->id != id)

    {

      id = chain->id;

      chain = VEC_index (du_head_p, id_to_chain, id);

    }

  first_chain->id = id;

  return chain;

}

/* Dump all def/use chains, starting at id FROM.  */

static void

dump_def_use_chain (int from)

{

  du_head_p head;

  int i;

  FOR_EACH_VEC_ELT_FROM (du_head_p, id_to_chain, i, head, from)

    {

      struct du_chain *this_du = head->first;

      fprintf (dump_file, "Register %s (%d):",

               reg_names[head->regno], head->nregs);

      while (this_du)

        {

          fprintf (dump_file, " %d [%s]", INSN_UID (this_du->insn),

                   reg_class_names[this_du->cl]);

          this_du = this_du->next_use;

        }

      fprintf (dump_file, "\n");

      head = head->next_chain;

    }

}

static void

free_chain_data (void)

{

  int i;

  du_head_p ptr;

  for (i = 0; VEC_iterate(du_head_p, id_to_chain, i, ptr); i++)

    bitmap_clear (&ptr->conflicts);

  VEC_free (du_head_p, heap, id_to_chain);

}

/* Walk all chains starting with CHAINS and record that they conflict with

   another chain whose id is ID.  */

static void

mark_conflict (struct du_head *chains, unsigned id)

{

  while (chains)

    {

      bitmap_set_bit (&chains->conflicts, id);

      chains = chains->next_chain;

    }

}

/* Examine cur_operand, and if it is nonnull, record information about the

   use THIS_DU which is part of the chain HEAD.  */

static void

record_operand_use (struct du_head *head, struct du_chain *this_du)

{

  if (cur_operand == NULL)

    return;

  gcc_assert (cur_operand->n_chains < MAX_REGS_PER_ADDRESS);

  cur_operand->heads[cur_operand->n_chains] = head;

  cur_operand->chains[cur_operand->n_chains++] = this_du;

}

/* Create a new chain for THIS_NREGS registers starting at THIS_REGNO,

   and record its occurrence in *LOC, which is being written to in INSN.

   This access requires a register of class CL.  */

static du_head_p

create_new_chain (unsigned this_regno, unsigned this_nregs, rtx *loc,

                  rtx insn, enum reg_class cl)

{

  struct du_head *head = XOBNEW (&rename_obstack, struct du_head);

  struct du_chain *this_du;

  int nregs;

  head->next_chain = open_chains;

  head->regno = this_regno;

  head->nregs = this_nregs;

  head->need_caller_save_reg = 0;

  head->cannot_rename = 0;

  VEC_safe_push (du_head_p, heap, id_to_chain, head);

  head->id = current_id++;

  bitmap_initialize (&head->conflicts, &bitmap_default_obstack);

  bitmap_copy (&head->conflicts, &open_chains_set);

  mark_conflict (open_chains, head->id);

  /* Since we're tracking this as a chain now, remove it from the

     list of conflicting live hard registers and track it in

     live_in_chains instead.  */

  nregs = head->nregs;

  while (nregs-- > 0)

    {

      SET_HARD_REG_BIT (live_in_chains, head->regno + nregs);

      CLEAR_HARD_REG_BIT (live_hard_regs, head->regno + nregs);

    }

  COPY_HARD_REG_SET (head->hard_conflicts, live_hard_regs);

  bitmap_set_bit (&open_chains_set, head->id);

  open_chains = head;

  if (dump_file)

    {

      fprintf (dump_file, "Creating chain %s (%d)",

               reg_names[head->regno], head->id);

      if (insn != NULL_RTX)

        fprintf (dump_file, " at insn %d", INSN_UID (insn));

      fprintf (dump_file, "\n");

    }

  if (insn == NULL_RTX)

    {

      head->first = head->last = NULL;

      return head;

    }

  this_du = XOBNEW (&rename_obstack, struct du_chain);

  head->first = head->last = this_du;

  this_du->next_use = 0;

  this_du->loc = loc;

  this_du->insn = insn;

  this_du->cl = cl;

  record_operand_use (head, this_du);

  return head;

}

/* For a def-use chain HEAD, find which registers overlap its lifetime and

   set the corresponding bits in *PSET.  */

static void

merge_overlapping_regs (HARD_REG_SET *pset, struct du_head *head)

{

  bitmap_iterator bi;

  unsigned i;

  IOR_HARD_REG_SET (*pset, head->hard_conflicts);

  EXECUTE_IF_SET_IN_BITMAP (&head->conflicts, 0, i, bi)

    {

      du_head_p other = regrename_chain_from_id (i);

      unsigned j = other->nregs;

      gcc_assert (other != head);

      while (j-- > 0)

        SET_HARD_REG_BIT (*pset, other->regno + j);

    }

}

/* Check if NEW_REG can be the candidate register to rename for

   REG in THIS_HEAD chain.  THIS_UNAVAILABLE is a set of unavailable hard

   registers.  */

static bool

check_new_reg_p (int reg ATTRIBUTE_UNUSED, int new_reg,

                 struct du_head *this_head, HARD_REG_SET this_unavailable)

{

  enum machine_mode mode = GET_MODE (*this_head->first->loc);

  int nregs = hard_regno_nregs[new_reg][mode];

  int i;

  struct du_chain *tmp;

  for (i = nregs - 1; i >= 0; --i)

    if (TEST_HARD_REG_BIT (this_unavailable, new_reg + i)

        || fixed_regs[new_reg + i]

        || global_regs[new_reg + i]

        /* Can't use regs which aren't saved by the prologue.  */

        || (! df_regs_ever_live_p (new_reg + i)

            && ! call_used_regs[new_reg + i])

#ifdef LEAF_REGISTERS

        /* We can't use a non-leaf register if we're in a

           leaf function.  */

        || (current_function_is_leaf

            && !LEAF_REGISTERS[new_reg + i])

#endif

#ifdef HARD_REGNO_RENAME_OK

        || ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i)

#endif

        )

      return false;

  /* See whether it accepts all modes that occur in

     definition and uses.  */

  for (tmp = this_head->first; tmp; tmp = tmp->next_use)

    if ((! HARD_REGNO_MODE_OK (new_reg, GET_MODE (*tmp->loc))

         && ! DEBUG_INSN_P (tmp->insn))

        || (this_head->need_caller_save_reg

            && ! (HARD_REGNO_CALL_PART_CLOBBERED

                  (reg, GET_MODE (*tmp->loc)))

            && (HARD_REGNO_CALL_PART_CLOBBERED

                (new_reg, GET_MODE (*tmp->loc)))))

      return false;

  return true;

}

/* For the chain THIS_HEAD, compute and return the best register to

   rename to.  SUPER_CLASS is the superunion of register classes in

   the chain.  UNAVAILABLE is a set of registers that cannot be used.

   OLD_REG is the register currently used for the chain.  */

int

find_best_rename_reg (du_head_p this_head, enum reg_class super_class,

                      HARD_REG_SET *unavailable, int old_reg)

{

  bool has_preferred_class;

  enum reg_class preferred_class;

  int pass;

  int best_new_reg = old_reg;

  /* Further narrow the set of registers we can use for renaming.

     If the chain needs a call-saved register, mark the call-used

     registers as unavailable.  */

  if (this_head->need_caller_save_reg)

    IOR_HARD_REG_SET (*unavailable, call_used_reg_set);

  /* Mark registers that overlap this chain's lifetime as unavailable.  */

  merge_overlapping_regs (unavailable, this_head);

  /* Compute preferred rename class of super union of all the classes

     in the chain.  */

  preferred_class

    = (enum reg_class) targetm.preferred_rename_class (super_class);

  /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass

     over registers that belong to PREFERRED_CLASS and try to find the

     best register within the class.  If that failed, we iterate in

     the second pass over registers that don't belong to the class.

     If PREFERRED_CLASS is NO_REGS, we iterate over all registers in

     ascending order without any preference.  */

  has_preferred_class = (preferred_class != NO_REGS);

  for (pass = (has_preferred_class ? 0 : 1); pass < 2; pass++)

    {

      int new_reg;

      for (new_reg = 0; new_reg < FIRST_PSEUDO_REGISTER; new_reg++)

        {

          if (has_preferred_class

              && (pass == 0)

              != TEST_HARD_REG_BIT (reg_class_contents[preferred_class],

                                    new_reg))

            continue;

          /* In the first pass, we force the renaming of registers that

             don't belong to PREFERRED_CLASS to registers that do, even

             though the latters were used not very long ago.  */

          if (check_new_reg_p (old_reg, new_reg, this_head,

                               *unavailable)

              && ((pass == 0

                   && !TEST_HARD_REG_BIT (reg_class_contents[preferred_class],

                                          best_new_reg))

                  || tick[best_new_reg] > tick[new_reg]))

            best_new_reg = new_reg;

        }

      if (pass == 0 && best_new_reg != old_reg)

        break;

    }

  return best_new_reg;

}

/* Perform register renaming on the current function.  */

static void

rename_chains (void)

{

  HARD_REG_SET unavailable;

  du_head_p this_head;

  int i;

  memset (tick, 0, sizeof tick);

  CLEAR_HARD_REG_SET (unavailable);

  /* Don't clobber traceback for noreturn functions.  */

  if (frame_pointer_needed)

    {

      add_to_hard_reg_set (&unavailable, Pmode, FRAME_POINTER_REGNUM);

#if !HARD_FRAME_POINTER_IS_FRAME_POINTER

      add_to_hard_reg_set (&unavailable, Pmode, HARD_FRAME_POINTER_REGNUM);

#endif

    }

  FOR_EACH_VEC_ELT (du_head_p, id_to_chain, i, this_head)

    {

      int best_new_reg;

      int n_uses;

      struct du_chain *tmp;

      HARD_REG_SET this_unavailable;

      int reg = this_head->regno;

      enum reg_class super_class = NO_REGS;

      if (this_head->cannot_rename)

        continue;

      if (fixed_regs[reg] || global_regs[reg]

#if !HARD_FRAME_POINTER_IS_FRAME_POINTER

          || (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM)

#else

          || (frame_pointer_needed && reg == FRAME_POINTER_REGNUM)

#endif

          )

        continue;

      COPY_HARD_REG_SET (this_unavailable, unavailable);

      /* Iterate over elements in the chain in order to:

         1. Count number of uses, and narrow the set of registers we can

            use for renaming.

         2. Compute the superunion of register classes in this chain.  */

      n_uses = 0;

      super_class = NO_REGS;

      for (tmp = this_head->first; tmp; tmp = tmp->next_use)

        {

          if (DEBUG_INSN_P (tmp->insn))

            continue;

          n_uses++;

          IOR_COMPL_HARD_REG_SET (this_unavailable,

                                  reg_class_contents[tmp->cl]);

          super_class

            = reg_class_superunion[(int) super_class][(int) tmp->cl];

        }

      if (n_uses < 2)

        continue;

      best_new_reg = find_best_rename_reg (this_head, super_class,

                                           &this_unavailable, reg);

      if (dump_file)

        {

          fprintf (dump_file, "Register %s in insn %d",

                   reg_names[reg], INSN_UID (this_head->first->insn));

          if (this_head->need_caller_save_reg)

            fprintf (dump_file, " crosses a call");

        }

      if (best_new_reg == reg)

        {

          tick[reg] = ++this_tick;

          if (dump_file)

            fprintf (dump_file, "; no available better choice\n");

          continue;

        }

      if (dump_file)

        fprintf (dump_file, ", renamed as %s\n", reg_names[best_new_reg]);

      regrename_do_replace (this_head, best_new_reg);

      tick[best_new_reg] = ++this_tick;

      df_set_regs_ever_live (best_new_reg, true);

    }

}

/* A structure to record information for each hard register at the start of

   a basic block.  */

struct incoming_reg_info {

  /* Holds the number of registers used in the chain that gave us information

     about this register.  Zero means no information known yet, while a

     negative value is used for something that is part of, but not the first

     register in a multi-register value.  */

  int nregs;

  /* Set to true if we have accesses that conflict in the number of registers

     used.  */

  bool unusable;

};

/* A structure recording information about each basic block.  It is saved

   and restored around basic block boundaries.

   A pointer to such a structure is stored in each basic block's aux field

   during regrename_analyze, except for blocks we know can't be optimized

   (such as entry and exit blocks).  */

struct bb_rename_info

{

  /* The basic block corresponding to this structure.  */

  basic_block bb;

  /* Copies of the global information.  */

  bitmap_head open_chains_set;

  bitmap_head incoming_open_chains_set;

  struct incoming_reg_info incoming[FIRST_PSEUDO_REGISTER];

};

/* Initialize a rename_info structure P for basic block BB, which starts a new

   scan.  */

static void

init_rename_info (struct bb_rename_info *p, basic_block bb)

{

  int i;

  df_ref *def_rec;

  HARD_REG_SET start_chains_set;

  p->bb = bb;

  bitmap_initialize (&p->open_chains_set, &bitmap_default_obstack);

  bitmap_initialize (&p->incoming_open_chains_set, &bitmap_default_obstack);

  open_chains = NULL;

  bitmap_clear (&open_chains_set);

  CLEAR_HARD_REG_SET (live_in_chains);

  REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_in (bb));

  for (def_rec = df_get_artificial_defs (bb->index); *def_rec; def_rec++)

    {

      df_ref def = *def_rec;

      if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)

        SET_HARD_REG_BIT (live_hard_regs, DF_REF_REGNO (def));

    }

  /* Open chains based on information from (at least one) predecessor

     block.  This gives us a chance later on to combine chains across

     basic block boundaries.  Inconsistencies (in access sizes) will

     be caught normally and dealt with conservatively by disabling the

     chain for renaming, and there is no risk of losing optimization

     opportunities by opening chains either: if we did not open the

     chains, we'd have to track the live register as a hard reg, and

     we'd be unable to rename it in any case.  */

  CLEAR_HARD_REG_SET (start_chains_set);

  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

    {

      struct incoming_reg_info *iri = p->incoming + i;

      if (iri->nregs > 0 && !iri->unusable

          && range_in_hard_reg_set_p (live_hard_regs, i, iri->nregs))

        {

          SET_HARD_REG_BIT (start_chains_set, i);

          remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs);

        }

    }

  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)

    {

      struct incoming_reg_info *iri = p->incoming + i;

      if (TEST_HARD_REG_BIT (start_chains_set, i))

        {

          du_head_p chain;

          if (dump_file)

            fprintf (dump_file, "opening incoming chain\n");

          chain = create_new_chain (i, iri->nregs, NULL, NULL_RTX, NO_REGS);

          bitmap_set_bit (&p->incoming_open_chains_set, chain->id);

        }

    }

}

/* Record in RI that the block corresponding to it has an incoming

   live value, described by CHAIN.  */

static void

set_incoming_from_chain (struct bb_rename_info *ri, du_head_p chain)

{

  int i;

  int incoming_nregs = ri->incoming[chain->regno].nregs;

  int nregs;

  /* If we've recorded the same information before, everything is fine.  */

  if (incoming_nregs == chain->nregs)

    {

      if (dump_file)

        fprintf (dump_file, "reg %d/%d already recorded\n",

                 chain->regno, chain->nregs);

      return;

    }

  /* If we have no information for any of the involved registers, update

     the incoming array.  */

  nregs = chain->nregs;

  while (nregs-- > 0)

    if (ri->incoming[chain->regno + nregs].nregs != 0

        || ri->incoming[chain->regno + nregs].unusable)

      break;

  if (nregs < 0)

    {

      nregs = chain->nregs;

      ri->incoming[chain->regno].nregs = nregs;

      while (nregs-- > 1)

        ri->incoming[chain->regno + nregs].nregs = -nregs;

      if (dump_file)

        fprintf (dump_file, "recorded reg %d/%d\n",

                 chain->regno, chain->nregs);

      return;

    }

  /* There must be some kind of conflict.  Prevent both the old and

     new ranges from being used.  */

  if (incoming_nregs < 0)

    ri->incoming[chain->regno + incoming_nregs].unusable = true;

  for (i = 0; i < chain->nregs; i++)

    ri->incoming[chain->regno + i].unusable = true;

}

/* Merge the two chains C1 and C2 so that all conflict information is

   recorded and C1, and the id of C2 is changed to that of C1.  */

static void

merge_chains (du_head_p c1, du_head_p c2)

{

  if (c1 == c2)

    return;

  if (c2->first != NULL)

    {

      if (c1->first == NULL)

        c1->first = c2->first;

      else

        c1->last->next_use = c2->first;

      c1->last = c2->last;

    }

  c2->first = c2->last = NULL;

  c2->id = c1->id;

  IOR_HARD_REG_SET (c1->hard_conflicts, c2->hard_conflicts);

  bitmap_ior_into (&c1->conflicts, &c2->conflicts);

  c1->need_caller_save_reg |= c2->need_caller_save_reg;

  c1->cannot_rename |= c2->cannot_rename;

}

/* Analyze the current function and build chains for renaming.  */

void

regrename_analyze (bitmap bb_mask)

{

  struct bb_rename_info *rename_info;

  int i;

  basic_block bb;

  int n_bbs;

  int *inverse_postorder;

  inverse_postorder = XNEWVEC (int, last_basic_block);

  n_bbs = pre_and_rev_post_order_compute (NULL, inverse_postorder, false);

  /* Gather some information about the blocks in this function.  */

  rename_info = XCNEWVEC (struct bb_rename_info, n_basic_blocks);

  i = 0;

  FOR_EACH_BB (bb)

    {

      struct bb_rename_info *ri = rename_info + i;

      ri->bb = bb;

      if (bb_mask != NULL && !bitmap_bit_p (bb_mask, bb->index))

        bb->aux = NULL;

      else

        bb->aux = ri;

      i++;

    }

  current_id = 0;

  id_to_chain = VEC_alloc (du_head_p, heap, 0);

  bitmap_initialize (&open_chains_set, &bitmap_default_obstack);

  /* The order in which we visit blocks ensures that whenever

     possible, we only process a block after at least one of its

     predecessors, which provides a "seeding" effect to make the logic

     in set_incoming_from_chain and init_rename_info useful.  */

  for (i = 0; i < n_bbs; i++)

    {

      basic_block bb1 = BASIC_BLOCK (inverse_postorder[i]);

      struct bb_rename_info *this_info;

      bool success;

      edge e;