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/* This file contains the definitions and documentation for the
2
   Register Transfer Expressions (rtx's) that make up the
3
   Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4
   Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
5
   2005, 2006, 2007, 2008, 2009, 2010, 2011
6
   Free Software Foundation, Inc.
7
 
8
This file is part of GCC.
9
 
10
GCC is free software; you can redistribute it and/or modify it under
11
the terms of the GNU General Public License as published by the Free
12
Software Foundation; either version 3, or (at your option) any later
13
version.
14
 
15
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16
WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18
for more details.
19
 
20
You should have received a copy of the GNU General Public License
21
along with GCC; see the file COPYING3.  If not see
22
.  */
23
 
24
 
25
/* Expression definitions and descriptions for all targets are in this file.
26
   Some will not be used for some targets.
27
 
28
   The fields in the cpp macro call "DEF_RTL_EXPR()"
29
   are used to create declarations in the C source of the compiler.
30
 
31
   The fields are:
32
 
33
   1.  The internal name of the rtx used in the C source.
34
   It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35
   By convention these are in UPPER_CASE.
36
 
37
   2.  The name of the rtx in the external ASCII format read by
38
   read_rtx(), and printed by print_rtx().
39
   These names are stored in rtx_name[].
40
   By convention these are the internal (field 1) names in lower_case.
41
 
42
   3.  The print format, and type of each rtx->u.fld[] (field) in this rtx.
43
   These formats are stored in rtx_format[].
44
   The meaning of the formats is documented in front of this array in rtl.c
45
 
46
   4.  The class of the rtx.  These are stored in rtx_class and are accessed
47
   via the GET_RTX_CLASS macro.  They are defined as follows:
48
 
49
     RTX_CONST_OBJ
50
         an rtx code that can be used to represent a constant object
51
         (e.g, CONST_INT)
52
     RTX_OBJ
53
         an rtx code that can be used to represent an object (e.g, REG, MEM)
54
     RTX_COMPARE
55
         an rtx code for a comparison (e.g, LT, GT)
56
     RTX_COMM_COMPARE
57
         an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
58
     RTX_UNARY
59
         an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
60
     RTX_COMM_ARITH
61
         an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
62
     RTX_TERNARY
63
         an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
64
     RTX_BIN_ARITH
65
         an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
66
     RTX_BITFIELD_OPS
67
         an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
68
     RTX_INSN
69
         an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
70
     RTX_MATCH
71
         an rtx code for something that matches in insns (e.g, MATCH_DUP)
72
     RTX_AUTOINC
73
         an rtx code for autoincrement addressing modes (e.g. POST_DEC)
74
     RTX_EXTRA
75
         everything else
76
 
77
   All of the expressions that appear only in machine descriptions,
78
   not in RTL used by the compiler itself, are at the end of the file.  */
79
 
80
/* Unknown, or no such operation; the enumeration constant should have
81
   value zero.  */
82
DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83
 
84
/* Used in the cselib routines to describe a value.  Objects of this
85
   kind are only allocated in cselib.c, in an alloc pool instead of in
86
   GC memory.  The only operand of a VALUE is a cselib_val_struct.
87
   var-tracking requires this to have a distinct integral value from
88
   DECL codes in trees.  */
89
DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90
 
91
/* The RTL generated for a DEBUG_EXPR_DECL.  It links back to the
92
   DEBUG_EXPR_DECL in the first operand.  */
93
DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94
 
95
/* ---------------------------------------------------------------------
96
   Expressions used in constructing lists.
97
   --------------------------------------------------------------------- */
98
 
99
/* a linked list of expressions */
100
DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101
 
102
/* a linked list of instructions.
103
   The insns are represented in print by their uids.  */
104
DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105
 
106
/* SEQUENCE appears in the result of a `gen_...' function
107
   for a DEFINE_EXPAND that wants to make several insns.
108
   Its elements are the bodies of the insns that should be made.
109
   `emit_insn' takes the SEQUENCE apart and makes separate insns.  */
110
DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
111
 
112
/* Refers to the address of its argument.  This is only used in alias.c.  */
113
DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
114
 
115
/* ----------------------------------------------------------------------
116
   Expression types used for things in the instruction chain.
117
 
118
   All formats must start with "iuu" to handle the chain.
119
   Each insn expression holds an rtl instruction and its semantics
120
   during back-end processing.
121
   See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
122
 
123
   ---------------------------------------------------------------------- */
124
 
125
/* An annotation for variable assignment tracking.  */
126
DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN)
127
 
128
/* An instruction that cannot jump.  */
129
DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN)
130
 
131
/* An instruction that can possibly jump.
132
   Fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
133
DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN)
134
 
135
/* An instruction that can possibly call a subroutine
136
   but which will not change which instruction comes next
137
   in the current function.
138
   Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
139
   All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's.  */
140
DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN)
141
 
142
/* A marker that indicates that control will not flow through.  */
143
DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
144
 
145
/* Holds a label that is followed by instructions.
146
   Operand:
147
   4: is used in jump.c for the use-count of the label.
148
   5: is used in the sh backend.
149
   6: is a number that is unique in the entire compilation.
150
   7: is the user-given name of the label, if any.  */
151
DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
152
 
153
/* Say where in the code a source line starts, for symbol table's sake.
154
   Operand:
155
   4: note-specific data
156
   5: enum insn_note
157
   6: unique number if insn_note == note_insn_deleted_label.  */
158
DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
159
 
160
/* ----------------------------------------------------------------------
161
   Top level constituents of INSN, JUMP_INSN and CALL_INSN.
162
   ---------------------------------------------------------------------- */
163
 
164
/* Conditionally execute code.
165
   Operand 0 is the condition that if true, the code is executed.
166
   Operand 1 is the code to be executed (typically a SET).
167
 
168
   Semantics are that there are no side effects if the condition
169
   is false.  This pattern is created automatically by the if_convert
170
   pass run after reload or by target-specific splitters.  */
171
DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
172
 
173
/* Several operations to be done in parallel (perhaps under COND_EXEC).  */
174
DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
175
 
176
/* A string that is passed through to the assembler as input.
177
     One can obviously pass comments through by using the
178
     assembler comment syntax.
179
     These occur in an insn all by themselves as the PATTERN.
180
     They also appear inside an ASM_OPERANDS
181
     as a convenient way to hold a string.  */
182
DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
183
 
184
/* An assembler instruction with operands.
185
   1st operand is the instruction template.
186
   2nd operand is the constraint for the output.
187
   3rd operand is the number of the output this expression refers to.
188
     When an insn stores more than one value, a separate ASM_OPERANDS
189
     is made for each output; this integer distinguishes them.
190
   4th is a vector of values of input operands.
191
   5th is a vector of modes and constraints for the input operands.
192
     Each element is an ASM_INPUT containing a constraint string
193
     and whose mode indicates the mode of the input operand.
194
   6th is a vector of labels that may be branched to by the asm.
195
   7th is the source line number.  */
196
DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
197
 
198
/* A machine-specific operation.
199
   1st operand is a vector of operands being used by the operation so that
200
     any needed reloads can be done.
201
   2nd operand is a unique value saying which of a number of machine-specific
202
     operations is to be performed.
203
   (Note that the vector must be the first operand because of the way that
204
   genrecog.c record positions within an insn.)
205
 
206
   UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
207
   or inside an expression.
208
   UNSPEC by itself or as a component of a PARALLEL
209
   is currently considered not deletable.
210
 
211
   FIXME: Replace all uses of UNSPEC that appears by itself or as a component
212
   of a PARALLEL with USE.
213
   */
214
DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
215
 
216
/* Similar, but a volatile operation and one which may trap.  */
217
DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
218
 
219
/* Vector of addresses, stored as full words.  */
220
/* Each element is a LABEL_REF to a CODE_LABEL whose address we want.  */
221
DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
222
 
223
/* Vector of address differences X0 - BASE, X1 - BASE, ...
224
   First operand is BASE; the vector contains the X's.
225
   The machine mode of this rtx says how much space to leave
226
   for each difference and is adjusted by branch shortening if
227
   CASE_VECTOR_SHORTEN_MODE is defined.
228
   The third and fourth operands store the target labels with the
229
   minimum and maximum addresses respectively.
230
   The fifth operand stores flags for use by branch shortening.
231
  Set at the start of shorten_branches:
232
   min_align: the minimum alignment for any of the target labels.
233
   base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
234
   min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
235
   max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
236
   min_after_base: true iff minimum address target label is after BASE.
237
   max_after_base: true iff maximum address target label is after BASE.
238
  Set by the actual branch shortening process:
239
   offset_unsigned: true iff offsets have to be treated as unsigned.
240
   scale: scaling that is necessary to make offsets fit into the mode.
241
 
242
   The third, fourth and fifth operands are only valid when
243
   CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
244
   compilations.  */
245
 
246
DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
247
 
248
/* Memory prefetch, with attributes supported on some targets.
249
   Operand 1 is the address of the memory to fetch.
250
   Operand 2 is 1 for a write access, 0 otherwise.
251
   Operand 3 is the level of temporal locality; 0 means there is no
252
   temporal locality and 1, 2, and 3 are for increasing levels of temporal
253
   locality.
254
 
255
   The attributes specified by operands 2 and 3 are ignored for targets
256
   whose prefetch instructions do not support them.  */
257
DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
258
 
259
/* ----------------------------------------------------------------------
260
   At the top level of an instruction (perhaps under PARALLEL).
261
   ---------------------------------------------------------------------- */
262
 
263
/* Assignment.
264
   Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
265
   Operand 2 is the value stored there.
266
   ALL assignment must use SET.
267
   Instructions that do multiple assignments must use multiple SET,
268
   under PARALLEL.  */
269
DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
270
 
271
/* Indicate something is used in a way that we don't want to explain.
272
   For example, subroutine calls will use the register
273
   in which the static chain is passed.
274
 
275
   USE can not appear as an operand of other rtx except for PARALLEL.
276
   USE is not deletable, as it indicates that the operand
277
   is used in some unknown way.  */
278
DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
279
 
280
/* Indicate something is clobbered in a way that we don't want to explain.
281
   For example, subroutine calls will clobber some physical registers
282
   (the ones that are by convention not saved).
283
 
284
   CLOBBER can not appear as an operand of other rtx except for PARALLEL.
285
   CLOBBER of a hard register appearing by itself (not within PARALLEL)
286
   is considered undeletable before reload.  */
287
DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
288
 
289
/* Call a subroutine.
290
   Operand 1 is the address to call.
291
   Operand 2 is the number of arguments.  */
292
 
293
DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
294
 
295
/* Return from a subroutine.  */
296
 
297
DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
298
 
299
/* Like RETURN, but truly represents only a function return, while
300
   RETURN may represent an insn that also performs other functions
301
   of the function epilogue.  Like RETURN, this may also occur in
302
   conditional jumps.  */
303
DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
304
 
305
/* Special for EH return from subroutine.  */
306
 
307
DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
308
 
309
/* Conditional trap.
310
   Operand 1 is the condition.
311
   Operand 2 is the trap code.
312
   For an unconditional trap, make the condition (const_int 1).  */
313
DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
314
 
315
/* ----------------------------------------------------------------------
316
   Primitive values for use in expressions.
317
   ---------------------------------------------------------------------- */
318
 
319
/* numeric integer constant */
320
DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
321
 
322
/* fixed-point constant */
323
DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
324
 
325
/* numeric floating point constant.
326
   Operands hold the value.  They are all 'w' and there may be from 2 to 6;
327
   see real.h.  */
328
DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
329
 
330
/* Describes a vector constant.  */
331
DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
332
 
333
/* String constant.  Used for attributes in machine descriptions and
334
   for special cases in DWARF2 debug output.  NOT used for source-
335
   language string constants.  */
336
DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
337
 
338
/* This is used to encapsulate an expression whose value is constant
339
   (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
340
   recognized as a constant operand rather than by arithmetic instructions.  */
341
 
342
DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
343
 
344
/* program counter.  Ordinary jumps are represented
345
   by a SET whose first operand is (PC).  */
346
DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
347
 
348
/* A register.  The "operand" is the register number, accessed with
349
   the REGNO macro.  If this number is less than FIRST_PSEUDO_REGISTER
350
   than a hardware register is being referred to.  The second operand
351
   holds the original register number - this will be different for a
352
   pseudo register that got turned into a hard register.  The third
353
   operand points to a reg_attrs structure.
354
   This rtx needs to have as many (or more) fields as a MEM, since we
355
   can change REG rtx's into MEMs during reload.  */
356
DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
357
 
358
/* A scratch register.  This represents a register used only within a
359
   single insn.  It will be turned into a REG during register allocation
360
   or reload unless the constraint indicates that the register won't be
361
   needed, in which case it can remain a SCRATCH.  This code is
362
   marked as having one operand so it can be turned into a REG.  */
363
DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
364
 
365
/* A reference to a part of another value.  The first operand is the
366
   complete value and the second is the byte offset of the selected part.   */
367
DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
368
 
369
/* This one-argument rtx is used for move instructions
370
   that are guaranteed to alter only the low part of a destination.
371
   Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
372
   has an unspecified effect on the high part of REG,
373
   but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
374
   is guaranteed to alter only the bits of REG that are in HImode.
375
 
376
   The actual instruction used is probably the same in both cases,
377
   but the register constraints may be tighter when STRICT_LOW_PART
378
   is in use.  */
379
 
380
DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
381
 
382
/* (CONCAT a b) represents the virtual concatenation of a and b
383
   to make a value that has as many bits as a and b put together.
384
   This is used for complex values.  Normally it appears only
385
   in DECL_RTLs and during RTL generation, but not in the insn chain.  */
386
DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
387
 
388
/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
389
   all An to make a value.  This is an extension of CONCAT to larger
390
   number of components.  Like CONCAT, it should not appear in the
391
   insn chain.  Every element of the CONCATN is the same size.  */
392
DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
393
 
394
/* A memory location; operand is the address.  The second operand is the
395
   alias set to which this MEM belongs.  We use `0' instead of `w' for this
396
   field so that the field need not be specified in machine descriptions.  */
397
DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
398
 
399
/* Reference to an assembler label in the code for this function.
400
   The operand is a CODE_LABEL found in the insn chain.  */
401
DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
402
 
403
/* Reference to a named label:
404
   Operand 0: label name
405
   Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
406
   Operand 2: tree from which this symbol is derived, or null.
407
   This is either a DECL node, or some kind of constant.  */
408
DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
409
 
410
/* The condition code register is represented, in our imagination,
411
   as a register holding a value that can be compared to zero.
412
   In fact, the machine has already compared them and recorded the
413
   results; but instructions that look at the condition code
414
   pretend to be looking at the entire value and comparing it.  */
415
DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
416
 
417
/* ----------------------------------------------------------------------
418
   Expressions for operators in an rtl pattern
419
   ---------------------------------------------------------------------- */
420
 
421
/* if_then_else.  This is used in representing ordinary
422
   conditional jump instructions.
423
     Operand:
424
     0:  condition
425
     1:  then expr
426
     2:  else expr */
427
DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
428
 
429
/* Comparison, produces a condition code result.  */
430
DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
431
 
432
/* plus */
433
DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
434
 
435
/* Operand 0 minus operand 1.  */
436
DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
437
 
438
/* Minus operand 0.  */
439
DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
440
 
441
DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
442
 
443
/* Multiplication with signed saturation */
444
DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
445
/* Multiplication with unsigned saturation */
446
DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
447
 
448
/* Operand 0 divided by operand 1.  */
449
DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
450
/* Division with signed saturation */
451
DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
452
/* Division with unsigned saturation */
453
DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
454
 
455
/* Remainder of operand 0 divided by operand 1.  */
456
DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
457
 
458
/* Unsigned divide and remainder.  */
459
DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
460
DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
461
 
462
/* Bitwise operations.  */
463
DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
464
DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
465
DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
466
DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
467
 
468
/* Operand:
469
     0:  value to be shifted.
470
     1:  number of bits.  */
471
DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
472
DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
473
DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
474
DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
475
DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
476
 
477
/* Minimum and maximum values of two operands.  We need both signed and
478
   unsigned forms.  (We cannot use MIN for SMIN because it conflicts
479
   with a macro of the same name.)   The signed variants should be used
480
   with floating point.  Further, if both operands are zeros, or if either
481
   operand is NaN, then it is unspecified which of the two operands is
482
   returned as the result.  */
483
 
484
DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
485
DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
486
DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
487
DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
488
 
489
/* These unary operations are used to represent incrementation
490
   and decrementation as they occur in memory addresses.
491
   The amount of increment or decrement are not represented
492
   because they can be understood from the machine-mode of the
493
   containing MEM.  These operations exist in only two cases:
494
   1. pushes onto the stack.
495
   2. created automatically by the auto-inc-dec pass.  */
496
DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
497
DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
498
DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
499
DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
500
 
501
/* These binary operations are used to represent generic address
502
   side-effects in memory addresses, except for simple incrementation
503
   or decrementation which use the above operations.  They are
504
   created automatically by the life_analysis pass in flow.c.
505
   The first operand is a REG which is used as the address.
506
   The second operand is an expression that is assigned to the
507
   register, either before (PRE_MODIFY) or after (POST_MODIFY)
508
   evaluating the address.
509
   Currently, the compiler can only handle second operands of the
510
   form (plus (reg) (reg)) and (plus (reg) (const_int)), where
511
   the first operand of the PLUS has to be the same register as
512
   the first operand of the *_MODIFY.  */
513
DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
514
DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
515
 
516
/* Comparison operations.  The ordered comparisons exist in two
517
   flavors, signed and unsigned.  */
518
DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
519
DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
520
DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
521
DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
522
DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
523
DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
524
DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
525
DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
526
DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
527
DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
528
 
529
/* Additional floating point unordered comparison flavors.  */
530
DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
531
DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
532
 
533
/* These are equivalent to unordered or ...  */
534
DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
535
DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
536
DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
537
DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
538
DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
539
 
540
/* This is an ordered NE, ie !UNEQ, ie false for NaN.  */
541
DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
542
 
543
/* Represents the result of sign-extending the sole operand.
544
   The machine modes of the operand and of the SIGN_EXTEND expression
545
   determine how much sign-extension is going on.  */
546
DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
547
 
548
/* Similar for zero-extension (such as unsigned short to int).  */
549
DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
550
 
551
/* Similar but here the operand has a wider mode.  */
552
DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
553
 
554
/* Similar for extending floating-point values (such as SFmode to DFmode).  */
555
DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
556
DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
557
 
558
/* Conversion of fixed point operand to floating point value.  */
559
DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
560
 
561
/* With fixed-point machine mode:
562
   Conversion of floating point operand to fixed point value.
563
   Value is defined only when the operand's value is an integer.
564
   With floating-point machine mode (and operand with same mode):
565
   Operand is rounded toward zero to produce an integer value
566
   represented in floating point.  */
567
DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
568
 
569
/* Conversion of unsigned fixed point operand to floating point value.  */
570
DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
571
 
572
/* With fixed-point machine mode:
573
   Conversion of floating point operand to *unsigned* fixed point value.
574
   Value is defined only when the operand's value is an integer.  */
575
DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
576
 
577
/* Conversions involving fractional fixed-point types without saturation,
578
   including:
579
     fractional to fractional (of different precision),
580
     signed integer to fractional,
581
     fractional to signed integer,
582
     floating point to fractional,
583
     fractional to floating point.
584
   NOTE: fractional can be either signed or unsigned for conversions.  */
585
DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
586
 
587
/* Conversions involving fractional fixed-point types and unsigned integer
588
   without saturation, including:
589
     unsigned integer to fractional,
590
     fractional to unsigned integer.
591
   NOTE: fractional can be either signed or unsigned for conversions.  */
592
DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
593
 
594
/* Conversions involving fractional fixed-point types with saturation,
595
   including:
596
     fractional to fractional (of different precision),
597
     signed integer to fractional,
598
     floating point to fractional.
599
   NOTE: fractional can be either signed or unsigned for conversions.  */
600
DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
601
 
602
/* Conversions involving fractional fixed-point types and unsigned integer
603
   with saturation, including:
604
     unsigned integer to fractional.
605
   NOTE: fractional can be either signed or unsigned for conversions.  */
606
DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
607
 
608
/* Absolute value */
609
DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
610
 
611
/* Square root */
612
DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
613
 
614
/* Swap bytes.  */
615
DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
616
 
617
/* Find first bit that is set.
618
   Value is 1 + number of trailing zeros in the arg.,
619
   or 0 if arg is 0.  */
620
DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
621
 
622
/* Count number of leading redundant sign bits (number of leading
623
   sign bits minus one).  */
624
DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
625
 
626
/* Count leading zeros.  */
627
DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
628
 
629
/* Count trailing zeros.  */
630
DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
631
 
632
/* Population count (number of 1 bits).  */
633
DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
634
 
635
/* Population parity (number of 1 bits modulo 2).  */
636
DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
637
 
638
/* Reference to a signed bit-field of specified size and position.
639
   Operand 0 is the memory unit (usually SImode or QImode) which
640
   contains the field's first bit.  Operand 1 is the width, in bits.
641
   Operand 2 is the number of bits in the memory unit before the
642
   first bit of this field.
643
   If BITS_BIG_ENDIAN is defined, the first bit is the msb and
644
   operand 2 counts from the msb of the memory unit.
645
   Otherwise, the first bit is the lsb and operand 2 counts from
646
   the lsb of the memory unit.
647
   This kind of expression can not appear as an lvalue in RTL.  */
648
DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
649
 
650
/* Similar for unsigned bit-field.
651
   But note!  This kind of expression _can_ appear as an lvalue.  */
652
DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
653
 
654
/* For RISC machines.  These save memory when splitting insns.  */
655
 
656
/* HIGH are the high-order bits of a constant expression.  */
657
DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
658
 
659
/* LO_SUM is the sum of a register and the low-order bits
660
   of a constant expression.  */
661
DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
662
 
663
/* Describes a merge operation between two vector values.
664
   Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
665
   that specifies where the parts of the result are taken from.  Set bits
666
   indicate operand 0, clear bits indicate operand 1.  The parts are defined
667
   by the mode of the vectors.  */
668
DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
669
 
670
/* Describes an operation that selects parts of a vector.
671
   Operands 0 is the source vector, operand 1 is a PARALLEL that contains
672
   a CONST_INT for each of the subparts of the result vector, giving the
673
   number of the source subpart that should be stored into it.  */
674
DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
675
 
676
/* Describes a vector concat operation.  Operands 0 and 1 are the source
677
   vectors, the result is a vector that is as long as operands 0 and 1
678
   combined and is the concatenation of the two source vectors.  */
679
DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
680
 
681
/* Describes an operation that converts a small vector into a larger one by
682
   duplicating the input values.  The output vector mode must have the same
683
   submodes as the input vector mode, and the number of output parts must be
684
   an integer multiple of the number of input parts.  */
685
DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
686
 
687
/* Addition with signed saturation */
688
DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
689
 
690
/* Addition with unsigned saturation */
691
DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
692
 
693
/* Operand 0 minus operand 1, with signed saturation.  */
694
DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
695
 
696
/* Negation with signed saturation.  */
697
DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
698
/* Negation with unsigned saturation.  */
699
DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
700
 
701
/* Absolute value with signed saturation.  */
702
DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
703
 
704
/* Shift left with signed saturation.  */
705
DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
706
 
707
/* Shift left with unsigned saturation.  */
708
DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
709
 
710
/* Operand 0 minus operand 1, with unsigned saturation.  */
711
DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
712
 
713
/* Signed saturating truncate.  */
714
DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
715
 
716
/* Unsigned saturating truncate.  */
717
DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
718
 
719
/* Floating point multiply/add combined instruction.  */
720
DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
721
 
722
/* Information about the variable and its location.  */
723
/* Changed 'te' to 'tei'; the 'i' field is for recording
724
   initialization status of variables.  */
725
DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
726
 
727
/* Used in VAR_LOCATION for a pointer to a decl that is no longer
728
   addressable.  */
729
DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
730
 
731
/* Represents value that argument had on function entry.  The
732
   single argument is the DECL_INCOMING_RTL of the corresponding
733
   parameter.  */
734
DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
735
 
736
/* Used in VAR_LOCATION for a reference to a parameter that has
737
   been optimized away completely.  */
738
DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
739
 
740
/* All expressions from this point forward appear only in machine
741
   descriptions.  */
742
#ifdef GENERATOR_FILE
743
 
744
/* Pattern-matching operators:  */
745
 
746
/* Use the function named by the second arg (the string)
747
   as a predicate; if matched, store the structure that was matched
748
   in the operand table at index specified by the first arg (the integer).
749
   If the second arg is the null string, the structure is just stored.
750
 
751
   A third string argument indicates to the register allocator restrictions
752
   on where the operand can be allocated.
753
 
754
   If the target needs no restriction on any instruction this field should
755
   be the null string.
756
 
757
   The string is prepended by:
758
   '=' to indicate the operand is only written to.
759
   '+' to indicate the operand is both read and written to.
760
 
761
   Each character in the string represents an allocable class for an operand.
762
   'g' indicates the operand can be any valid class.
763
   'i' indicates the operand can be immediate (in the instruction) data.
764
   'r' indicates the operand can be in a register.
765
   'm' indicates the operand can be in memory.
766
   'o' a subset of the 'm' class.  Those memory addressing modes that
767
       can be offset at compile time (have a constant added to them).
768
 
769
   Other characters indicate target dependent operand classes and
770
   are described in each target's machine description.
771
 
772
   For instructions with more than one operand, sets of classes can be
773
   separated by a comma to indicate the appropriate multi-operand constraints.
774
   There must be a 1 to 1 correspondence between these sets of classes in
775
   all operands for an instruction.
776
   */
777
DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
778
 
779
/* Match a SCRATCH or a register.  When used to generate rtl, a
780
   SCRATCH is generated.  As for MATCH_OPERAND, the mode specifies
781
   the desired mode and the first argument is the operand number.
782
   The second argument is the constraint.  */
783
DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
784
 
785
/* Apply a predicate, AND match recursively the operands of the rtx.
786
   Operand 0 is the operand-number, as in match_operand.
787
   Operand 1 is a predicate to apply (as a string, a function name).
788
   Operand 2 is a vector of expressions, each of which must match
789
   one subexpression of the rtx this construct is matching.  */
790
DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
791
 
792
/* Match a PARALLEL of arbitrary length.  The predicate is applied
793
   to the PARALLEL and the initial expressions in the PARALLEL are matched.
794
   Operand 0 is the operand-number, as in match_operand.
795
   Operand 1 is a predicate to apply to the PARALLEL.
796
   Operand 2 is a vector of expressions, each of which must match the
797
   corresponding element in the PARALLEL.  */
798
DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
799
 
800
/* Match only something equal to what is stored in the operand table
801
   at the index specified by the argument.  Use with MATCH_OPERAND.  */
802
DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
803
 
804
/* Match only something equal to what is stored in the operand table
805
   at the index specified by the argument.  Use with MATCH_OPERATOR.  */
806
DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
807
 
808
/* Match only something equal to what is stored in the operand table
809
   at the index specified by the argument.  Use with MATCH_PARALLEL.  */
810
DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
811
 
812
/* Appears only in define_predicate/define_special_predicate
813
   expressions.  Evaluates true only if the operand has an RTX code
814
   from the set given by the argument (a comma-separated list).  If the
815
   second argument is present and nonempty, it is a sequence of digits
816
   and/or letters which indicates the subexpression to test, using the
817
   same syntax as genextract/genrecog's location strings: 0-9 for
818
   XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
819
   the result of the one before it.  */
820
DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
821
 
822
/* Used to inject a C conditional expression into an .md file.  It can
823
   appear in a predicate definition or an attribute expression.  */
824
DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
825
 
826
/* Insn (and related) definitions.  */
827
 
828
/* Definition of the pattern for one kind of instruction.
829
   Operand:
830
   0: names this instruction.
831
      If the name is the null string, the instruction is in the
832
      machine description just to be recognized, and will never be emitted by
833
      the tree to rtl expander.
834
   1: is the pattern.
835
   2: is a string which is a C expression
836
      giving an additional condition for recognizing this pattern.
837
      A null string means no extra condition.
838
   3: is the action to execute if this pattern is matched.
839
      If this assembler code template starts with a * then it is a fragment of
840
      C code to run to decide on a template to use.  Otherwise, it is the
841
      template to use.
842
   4: optionally, a vector of attributes for this insn.
843
     */
844
DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
845
 
846
/* Definition of a peephole optimization.
847
   1st operand: vector of insn patterns to match
848
   2nd operand: C expression that must be true
849
   3rd operand: template or C code to produce assembler output.
850
   4: optionally, a vector of attributes for this insn.
851
 
852
   This form is deprecated; use define_peephole2 instead.  */
853
DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
854
 
855
/* Definition of a split operation.
856
   1st operand: insn pattern to match
857
   2nd operand: C expression that must be true
858
   3rd operand: vector of insn patterns to place into a SEQUENCE
859
   4th operand: optionally, some C code to execute before generating the
860
        insns.  This might, for example, create some RTX's and store them in
861
        elements of `recog_data.operand' for use by the vector of
862
        insn-patterns.
863
        (`operands' is an alias here for `recog_data.operand').  */
864
DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
865
 
866
/* Definition of an insn and associated split.
867
   This is the concatenation, with a few modifications, of a define_insn
868
   and a define_split which share the same pattern.
869
   Operand:
870
   0: names this instruction.
871
      If the name is the null string, the instruction is in the
872
      machine description just to be recognized, and will never be emitted by
873
      the tree to rtl expander.
874
   1: is the pattern.
875
   2: is a string which is a C expression
876
      giving an additional condition for recognizing this pattern.
877
      A null string means no extra condition.
878
   3: is the action to execute if this pattern is matched.
879
      If this assembler code template starts with a * then it is a fragment of
880
      C code to run to decide on a template to use.  Otherwise, it is the
881
      template to use.
882
   4: C expression that must be true for split.  This may start with "&&"
883
      in which case the split condition is the logical and of the insn
884
      condition and what follows the "&&" of this operand.
885
   5: vector of insn patterns to place into a SEQUENCE
886
   6: optionally, some C code to execute before generating the
887
        insns.  This might, for example, create some RTX's and store them in
888
        elements of `recog_data.operand' for use by the vector of
889
        insn-patterns.
890
        (`operands' is an alias here for `recog_data.operand').
891
   7: optionally, a vector of attributes for this insn.  */
892
DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
893
 
894
/* Definition of an RTL peephole operation.
895
   Follows the same arguments as define_split.  */
896
DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
897
 
898
/* Define how to generate multiple insns for a standard insn name.
899
   1st operand: the insn name.
900
   2nd operand: vector of insn-patterns.
901
        Use match_operand to substitute an element of `recog_data.operand'.
902
   3rd operand: C expression that must be true for this to be available.
903
        This may not test any operands.
904
   4th operand: Extra C code to execute before generating the insns.
905
        This might, for example, create some RTX's and store them in
906
        elements of `recog_data.operand' for use by the vector of
907
        insn-patterns.
908
        (`operands' is an alias here for `recog_data.operand').  */
909
DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
910
 
911
/* Define a requirement for delay slots.
912
   1st operand: Condition involving insn attributes that, if true,
913
                indicates that the insn requires the number of delay slots
914
                shown.
915
   2nd operand: Vector whose length is the three times the number of delay
916
                slots required.
917
                Each entry gives three conditions, each involving attributes.
918
                The first must be true for an insn to occupy that delay slot
919
                location.  The second is true for all insns that can be
920
                annulled if the branch is true and the third is true for all
921
                insns that can be annulled if the branch is false.
922
 
923
   Multiple DEFINE_DELAYs may be present.  They indicate differing
924
   requirements for delay slots.  */
925
DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
926
 
927
/* Define attribute computation for `asm' instructions.  */
928
DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
929
 
930
/* Definition of a conditional execution meta operation.  Automatically
931
   generates new instances of DEFINE_INSN, selected by having attribute
932
   "predicable" true.  The new pattern will contain a COND_EXEC and the
933
   predicate at top-level.
934
 
935
   Operand:
936
   0: The predicate pattern.  The top-level form should match a
937
      relational operator.  Operands should have only one alternative.
938
   1: A C expression giving an additional condition for recognizing
939
      the generated pattern.
940
   2: A template or C code to produce assembler output.  */
941
DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
942
 
943
/* Definition of an operand predicate.  The difference between
944
   DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
945
   not warn about a match_operand with no mode if it has a predicate
946
   defined with DEFINE_SPECIAL_PREDICATE.
947
 
948
   Operand:
949
   0: The name of the predicate.
950
   1: A boolean expression which computes whether or not the predicate
951
      matches.  This expression can use IOR, AND, NOT, MATCH_OPERAND,
952
      MATCH_CODE, and MATCH_TEST.  It must be specific enough that genrecog
953
      can calculate the set of RTX codes that can possibly match.
954
   2: A C function body which must return true for the predicate to match.
955
      Optional.  Use this when the test is too complicated to fit into a
956
      match_test expression.  */
957
DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
958
DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
959
 
960
/* Definition of a register operand constraint.  This simply maps the
961
   constraint string to a register class.
962
 
963
   Operand:
964
   0: The name of the constraint (often, but not always, a single letter).
965
   1: A C expression which evaluates to the appropriate register class for
966
      this constraint.  If this is not just a constant, it should look only
967
      at -m switches and the like.
968
   2: A docstring for this constraint, in Texinfo syntax; not currently
969
      used, in future will be incorporated into the manual's list of
970
      machine-specific operand constraints.  */
971
DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
972
 
973
/* Definition of a non-register operand constraint.  These look at the
974
   operand and decide whether it fits the constraint.
975
 
976
   DEFINE_CONSTRAINT gets no special treatment if it fails to match.
977
   It is appropriate for constant-only constraints, and most others.
978
 
979
   DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
980
   to match, if it doesn't already, by converting the operand to the form
981
   (mem (reg X)) where X is a base register.  It is suitable for constraints
982
   that describe a subset of all memory references.
983
 
984
   DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
985
   to match, if it doesn't already, by converting the operand to the form
986
   (reg X) where X is a base register.  It is suitable for constraints that
987
   describe a subset of all address references.
988
 
989
   When in doubt, use plain DEFINE_CONSTRAINT.
990
 
991
   Operand:
992
   0: The name of the constraint (often, but not always, a single letter).
993
   1: A docstring for this constraint, in Texinfo syntax; not currently
994
      used, in future will be incorporated into the manual's list of
995
      machine-specific operand constraints.
996
   2: A boolean expression which computes whether or not the constraint
997
      matches.  It should follow the same rules as a define_predicate
998
      expression, including the bit about specifying the set of RTX codes
999
      that could possibly match.  MATCH_TEST subexpressions may make use of
1000
      these variables:
1001
        `op'    - the RTL object defining the operand.
1002
        `mode'  - the mode of `op'.
1003
        `ival'  - INTVAL(op), if op is a CONST_INT.
1004
        `hval'  - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1005
        `lval'  - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1006
        `rval'  - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1007
                  CONST_DOUBLE.
1008
      Do not use ival/hval/lval/rval if op is not the appropriate kind of
1009
      RTL object.  */
1010
DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1011
DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1012
DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1013
 
1014
 
1015
/* Constructions for CPU pipeline description described by NDFAs.  */
1016
 
1017
/* (define_cpu_unit string [string]) describes cpu functional
1018
   units (separated by comma).
1019
 
1020
   1st operand: Names of cpu functional units.
1021
   2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1022
 
1023
   All define_reservations, define_cpu_units, and
1024
   define_query_cpu_units should have unique names which may not be
1025
   "nothing".  */
1026
DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1027
 
1028
/* (define_query_cpu_unit string [string]) describes cpu functional
1029
   units analogously to define_cpu_unit.  The reservation of such
1030
   units can be queried for automaton state.  */
1031
DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1032
 
1033
/* (exclusion_set string string) means that each CPU functional unit
1034
   in the first string can not be reserved simultaneously with any
1035
   unit whose name is in the second string and vise versa.  CPU units
1036
   in the string are separated by commas.  For example, it is useful
1037
   for description CPU with fully pipelined floating point functional
1038
   unit which can execute simultaneously only single floating point
1039
   insns or only double floating point insns.  All CPU functional
1040
   units in a set should belong to the same automaton.  */
1041
DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1042
 
1043
/* (presence_set string string) means that each CPU functional unit in
1044
   the first string can not be reserved unless at least one of pattern
1045
   of units whose names are in the second string is reserved.  This is
1046
   an asymmetric relation.  CPU units or unit patterns in the strings
1047
   are separated by commas.  Pattern is one unit name or unit names
1048
   separated by white-spaces.
1049
 
1050
   For example, it is useful for description that slot1 is reserved
1051
   after slot0 reservation for a VLIW processor.  We could describe it
1052
   by the following construction
1053
 
1054
      (presence_set "slot1" "slot0")
1055
 
1056
   Or slot1 is reserved only after slot0 and unit b0 reservation.  In
1057
   this case we could write
1058
 
1059
      (presence_set "slot1" "slot0 b0")
1060
 
1061
   All CPU functional units in a set should belong to the same
1062
   automaton.  */
1063
DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1064
 
1065
/* (final_presence_set string string) is analogous to `presence_set'.
1066
   The difference between them is when checking is done.  When an
1067
   instruction is issued in given automaton state reflecting all
1068
   current and planned unit reservations, the automaton state is
1069
   changed.  The first state is a source state, the second one is a
1070
   result state.  Checking for `presence_set' is done on the source
1071
   state reservation, checking for `final_presence_set' is done on the
1072
   result reservation.  This construction is useful to describe a
1073
   reservation which is actually two subsequent reservations.  For
1074
   example, if we use
1075
 
1076
      (presence_set "slot1" "slot0")
1077
 
1078
   the following insn will be never issued (because slot1 requires
1079
   slot0 which is absent in the source state).
1080
 
1081
      (define_reservation "insn_and_nop" "slot0 + slot1")
1082
 
1083
   but it can be issued if we use analogous `final_presence_set'.  */
1084
DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1085
 
1086
/* (absence_set string string) means that each CPU functional unit in
1087
   the first string can be reserved only if each pattern of units
1088
   whose names are in the second string is not reserved.  This is an
1089
   asymmetric relation (actually exclusion set is analogous to this
1090
   one but it is symmetric).  CPU units or unit patterns in the string
1091
   are separated by commas.  Pattern is one unit name or unit names
1092
   separated by white-spaces.
1093
 
1094
   For example, it is useful for description that slot0 can not be
1095
   reserved after slot1 or slot2 reservation for a VLIW processor.  We
1096
   could describe it by the following construction
1097
 
1098
      (absence_set "slot2" "slot0, slot1")
1099
 
1100
   Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1101
   slot1 and unit b1 are reserved .  In this case we could write
1102
 
1103
      (absence_set "slot2" "slot0 b0, slot1 b1")
1104
 
1105
   All CPU functional units in a set should to belong the same
1106
   automaton.  */
1107
DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1108
 
1109
/* (final_absence_set string string) is analogous to `absence_set' but
1110
   checking is done on the result (state) reservation.  See comments
1111
   for `final_presence_set'.  */
1112
DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1113
 
1114
/* (define_bypass number out_insn_names in_insn_names) names bypass
1115
   with given latency (the first number) from insns given by the first
1116
   string (see define_insn_reservation) into insns given by the second
1117
   string.  Insn names in the strings are separated by commas.  The
1118
   third operand is optional name of function which is additional
1119
   guard for the bypass.  The function will get the two insns as
1120
   parameters.  If the function returns zero the bypass will be
1121
   ignored for this case.  Additional guard is necessary to recognize
1122
   complicated bypasses, e.g. when consumer is load address.  If there
1123
   are more one bypass with the same output and input insns, the
1124
   chosen bypass is the first bypass with a guard in description whose
1125
   guard function returns nonzero.  If there is no such bypass, then
1126
   bypass without the guard function is chosen.  */
1127
DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1128
 
1129
/* (define_automaton string) describes names of automata generated and
1130
   used for pipeline hazards recognition.  The names are separated by
1131
   comma.  Actually it is possibly to generate the single automaton
1132
   but unfortunately it can be very large.  If we use more one
1133
   automata, the summary size of the automata usually is less than the
1134
   single one.  The automaton name is used in define_cpu_unit and
1135
   define_query_cpu_unit.  All automata should have unique names.  */
1136
DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1137
 
1138
/* (automata_option string) describes option for generation of
1139
   automata.  Currently there are the following options:
1140
 
1141
   o "no-minimization" which makes no minimization of automata.  This
1142
     is only worth to do when we are debugging the description and
1143
     need to look more accurately at reservations of states.
1144
 
1145
   o "time" which means printing additional time statistics about
1146
      generation of automata.
1147
 
1148
   o "v" which means generation of file describing the result
1149
     automata.  The file has suffix `.dfa' and can be used for the
1150
     description verification and debugging.
1151
 
1152
   o "w" which means generation of warning instead of error for
1153
     non-critical errors.
1154
 
1155
   o "ndfa" which makes nondeterministic finite state automata.
1156
 
1157
   o "progress" which means output of a progress bar showing how many
1158
     states were generated so far for automaton being processed.  */
1159
DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1160
 
1161
/* (define_reservation string string) names reservation (the first
1162
   string) of cpu functional units (the 2nd string).  Sometimes unit
1163
   reservations for different insns contain common parts.  In such
1164
   case, you can describe common part and use its name (the 1st
1165
   parameter) in regular expression in define_insn_reservation.  All
1166
   define_reservations, define_cpu_units, and define_query_cpu_units
1167
   should have unique names which may not be "nothing".  */
1168
DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1169
 
1170
/* (define_insn_reservation name default_latency condition regexpr)
1171
   describes reservation of cpu functional units (the 3nd operand) for
1172
   instruction which is selected by the condition (the 2nd parameter).
1173
   The first parameter is used for output of debugging information.
1174
   The reservations are described by a regular expression according
1175
   the following syntax:
1176
 
1177
       regexp = regexp "," oneof
1178
              | oneof
1179
 
1180
       oneof = oneof "|" allof
1181
             | allof
1182
 
1183
       allof = allof "+" repeat
1184
             | repeat
1185
 
1186
       repeat = element "*" number
1187
              | element
1188
 
1189
       element = cpu_function_unit_name
1190
               | reservation_name
1191
               | result_name
1192
               | "nothing"
1193
               | "(" regexp ")"
1194
 
1195
       1. "," is used for describing start of the next cycle in
1196
       reservation.
1197
 
1198
       2. "|" is used for describing the reservation described by the
1199
       first regular expression *or* the reservation described by the
1200
       second regular expression *or* etc.
1201
 
1202
       3. "+" is used for describing the reservation described by the
1203
       first regular expression *and* the reservation described by the
1204
       second regular expression *and* etc.
1205
 
1206
       4. "*" is used for convenience and simply means sequence in
1207
       which the regular expression are repeated NUMBER times with
1208
       cycle advancing (see ",").
1209
 
1210
       5. cpu functional unit name which means its reservation.
1211
 
1212
       6. reservation name -- see define_reservation.
1213
 
1214
       7. string "nothing" means no units reservation.  */
1215
 
1216
DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1217
 
1218
/* Expressions used for insn attributes.  */
1219
 
1220
/* Definition of an insn attribute.
1221
   1st operand: name of the attribute
1222
   2nd operand: comma-separated list of possible attribute values
1223
   3rd operand: expression for the default value of the attribute.  */
1224
DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1225
 
1226
/* Definition of an insn attribute that uses an existing enumerated type.
1227
   1st operand: name of the attribute
1228
   2nd operand: the name of the enumerated type
1229
   3rd operand: expression for the default value of the attribute.  */
1230
DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1231
 
1232
/* Marker for the name of an attribute.  */
1233
DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1234
 
1235
/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1236
   in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1237
   pattern.
1238
 
1239
   (set_attr "name" "value") is equivalent to
1240
   (set (attr "name") (const_string "value"))  */
1241
DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1242
 
1243
/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1244
   specify that attribute values are to be assigned according to the
1245
   alternative matched.
1246
 
1247
   The following three expressions are equivalent:
1248
 
1249
   (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1250
                            (eq_attrq "alternative" "2") (const_string "a2")]
1251
                           (const_string "a3")))
1252
   (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1253
                                 (const_string "a3")])
1254
   (set_attr "att" "a1,a2,a3")
1255
 */
1256
DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1257
 
1258
/* A conditional expression true if the value of the specified attribute of
1259
   the current insn equals the specified value.  The first operand is the
1260
   attribute name and the second is the comparison value.  */
1261
DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1262
 
1263
/* A special case of the above representing a set of alternatives.  The first
1264
   operand is bitmap of the set, the second one is the default value.  */
1265
DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1266
 
1267
/* A conditional expression which is true if the specified flag is
1268
   true for the insn being scheduled in reorg.
1269
 
1270
   genattr.c defines the following flags which can be tested by
1271
   (attr_flag "foo") expressions in eligible_for_delay.
1272
 
1273
   forward, backward, very_likely, likely, very_unlikely, and unlikely.  */
1274
 
1275
DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1276
 
1277
/* General conditional. The first operand is a vector composed of pairs of
1278
   expressions.  The first element of each pair is evaluated, in turn.
1279
   The value of the conditional is the second expression of the first pair
1280
   whose first expression evaluates nonzero.  If none of the expressions is
1281
   true, the second operand will be used as the value of the conditional.  */
1282
DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1283
 
1284
#endif /* GENERATOR_FILE */
1285
 
1286
/*
1287
Local variables:
1288
mode:c
1289
End:
1290
*/

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