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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [g++.dg/] [eh/] [simd-2.C] - Blame information for rev 749

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Line No. Rev Author Line
1 693 jeremybenn
// Test EH when V4SI SIMD registers are involved.
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// Contributed by Aldy Hernandez (aldy@quesejoda.com).
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// { dg-options "-O -Wno-abi" }
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// { dg-options "-O -w -msse" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
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// { dg-options "-O -w" { target powerpc*-*-* } }
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// { dg-options "-O -w -maltivec" { target { powerpc*-*-* && vmx_hw } } }
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// { dg-do run }
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// { dg-require-effective-target sse_runtime { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
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#include "check-vect.h"
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typedef int __attribute__((vector_size (16))) vecint;
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vecint vecfunc (vecint beachbum)
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{
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  return beachbum;
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}
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void f3 (void)
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{
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  vecint foobar = (vecint) {0, 0};
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  foobar = vecfunc (foobar);
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  throw int();
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}
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void f2 (void)
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{
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  vecint foobar = (vecint) {0, 0};
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  foobar = vecfunc (foobar);
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  f3 ();
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}
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void f1 (void)
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{
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  int i;
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  try
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    {
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      f2 ();
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    }
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  catch (int)
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    {
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      i = 9;
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    }
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}
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int main ()
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{
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  /* Exit with zero if the hardware does not support AltiVec instructions.  */
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  check_vect ();
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  f1 ();
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  return 0;
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}

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