OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [g++.dg/] [eh/] [simd-3.C] - Blame information for rev 693

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 693 jeremybenn
// { dg-options "-O" }
2
// { dg-options "-O -maltivec" { target { powerpc*-*-darwin* && powerpc_altivec_ok } } }
3
// { dg-do run }
4
 
5
#include 
6
#include 
7
 
8
typedef int __attribute__((vector_size(16))) v;
9
 
10
v vv[32];
11
volatile v vt = { 1, 2, 3, 4 };
12
 
13
void clobber_vrs(void) { };
14
 
15
void (*volatile fp)() = clobber_vrs;
16
 
17
void thrower(void)
18
{
19
  v v00 = vv[ 0];
20
  v v01 = vv[ 1];
21
  v v02 = vv[ 2];
22
  v v03 = vv[ 3];
23
  v v04 = vv[ 4];
24
  v v05 = vv[ 5];
25
  v v06 = vv[ 6];
26
  v v07 = vv[ 7];
27
  v v08 = vv[ 8];
28
  v v09 = vv[ 9];
29
  v v10 = vv[10];
30
  v v11 = vv[11];
31
  v v12 = vv[12];
32
 
33
  fp();
34
 
35
  vv[ 0] = v00;
36
  vv[ 1] = v01;
37
  vv[ 2] = v02;
38
  vv[ 3] = v03;
39
  vv[ 4] = v04;
40
  vv[ 5] = v05;
41
  vv[ 6] = v06;
42
  vv[ 7] = v07;
43
  vv[ 8] = v08;
44
  vv[ 9] = v09;
45
  vv[10] = v10;
46
  vv[11] = v11;
47
  vv[12] = v12;
48
 
49
  throw 3;
50
}
51
 
52
v v2;
53
 
54
int main(void)
55
{
56
  v v1 = vt;
57
  try {
58
    thrower();
59
  } catch (int x) {
60
  }
61
  v2 = v1;
62
  if (memcmp (&v2, (v *)&vt, sizeof (v2)) != 0)
63
    abort ();
64
  return 0;
65
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.