OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20031220-1.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 688 jeremybenn
/* PR optimization/13031  */
2
/* The following code used to ICE on alphaev67-*-* at -O2 with an
3
   unrecognizable instruction, caused by local register allocation
4
   substituting a register for a constant in a conditional branch.  */
5
 
6
void emit(int, int);
7
int f(void);
8
static int signals[5];
9
 
10
static inline void select(int sel, void *klass)
11
{
12
  emit(klass ? 0 : f(), signals[sel ? 0 : 1]);
13
}
14
 
15
void all(void *gil, void *l, void *icon)
16
{
17
  while (l)
18
    if (icon)
19
      select(0, gil);
20
}
21
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.