OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20040101-1.c] - Blame information for rev 749

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 688 jeremybenn
/* { dg-skip-if "not enough registers" { pdp11-*-* } { "-O[12s]" } { "" } } */
2
 
3
typedef unsigned short uint16_t;
4
typedef unsigned int uint32_t;
5
 
6
#define CF (1<<0)
7
#define PF (1<<2)
8
#define AF (1<<4)
9
#define ZF (1<<6)
10
#define SF (1<<7)
11
#define OF (1<<11)
12
 
13
#define EFLAGS_BITS (CF|PF|AF|ZF|SF|OF)
14
 
15
void test16(uint16_t x, uint32_t eflags)
16
{
17
        uint16_t bsr_result;
18
        uint32_t bsr_eflags;
19
        uint16_t bsf_result;
20
        uint32_t bsf_eflags;
21
 
22
        __asm volatile(""
23
                : "=&r" (bsr_result), "=&r" (bsr_eflags)
24
                : "r" (x), "i" (~EFLAGS_BITS), "r" (eflags));
25
        __asm volatile(""
26
                : "=&r" (bsf_result), "=&r" (bsf_eflags)
27
                : "r" (x), "i" (~EFLAGS_BITS), "r" (eflags));
28
        printf("%08x %04x bsrw %02x %08x bsfw %02x %08x\n",
29
                x, eflags, bsr_result, bsr_eflags, bsf_result, bsf_eflags);
30
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.