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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20040109-1.c] - Blame information for rev 774

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/* PR target/13380.
   On m32r, the condition code register, (reg:SI 17), was replaced with
   a pseudo reg, which would cause an unrecognized insn.  */
 
void
foo (unsigned int a, unsigned int b)
{
  if (a > b)
    {
      while (a)
        {
          switch (b)
            {
            default:
              a = 0;
            case 2:
              a = 0;
            case 1:
              a = 0;
            case 0:
              ;
            }
        }
    }
}

Line No.	Rev	Author	Line
1	688	jeremybenn	`/* PR target/13380.`
2			`On m32r, the condition code register, (reg:SI 17), was replaced with`
3			`a pseudo reg, which would cause an unrecognized insn. */`
4
5			`void`
6			`foo (unsigned int a, unsigned int b)`
7			`{`
8			`if (a > b)`
9			`{`
10			`while (a)`
11			`{`
12			`switch (b)`
13			`{`
14			`default:`
15			`a = 0;`
16			`case 2:`
17			`a = 0;`
18			`case 1:`
19			`a = 0;`
20			`case 0:`
21			`;`
22			`}`
23			`}`
24			`}`
25			`}`

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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20040109-1.c] - Blame information for rev 774