OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [920501-4.c] - Blame information for rev 688

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 688 jeremybenn 
/* { dg-do assemble } */
2 
 
3 
foo ()
4 
{
5 
  int r0[8186 ];
6 
  int r1[2 ];
7 
  int r2[2 ];
8 
  int bitm0[2 ];
9 
  int bitm1[2 ];
10 
  int bitm2[2 ];
11 
 
12 
  int i,j,k,m,n,m_max;
13 
  int f;
14 
  double fm,ft;
15 
 
16 
  while (1) {
17 
 
18 
    if (m%4 == 2)
19 
      ++m;
20 
 
21 
    if (m_max != 0 && m > m_max)
22 
      break;
23 
 
24 
    fm=m;
25 
 
26 
    r0[k=1]=0;
27 
    bitm0[0] = 0;
28 
 
29 
      while ( n%f == 0 ) {
30 
        while ( (ft != 0) && (ft < fm )) {
31 
          bitm1[i] = 0;
32 
          r1[i]=0;
33 
          }
34 
 
35 
        while ( r0[i] != 0 && r1[i] != 0 ) {
36 
          if ( r0[i] < r1[i] ) {
37 
            bitm2[k] = bitm0[i];
38 
            r2[k++]=0;
39 
          }
40 
          else if ( r0[i] > r1[j] ) {
41 
            bitm2[k] = bitm1[j];
42 
            r2[k++]=r1[j++];
43 
          }
44 
          else {
45 
            bitm1[k] = bitm0[i];
46 
            r2[k++]=r0[i++];
47 
          }
48 
        }
49 
      }
50 
  }
51 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.