OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.c-torture/] [execute/] [simd-1.c] - Blame information for rev 774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 688 jeremybenn
/* Origin: Aldy Hernandez <aldyh@redhat.com>
2
 
3
   Purpose: Test generic SIMD support.  This test should work
4
   regardless of if the target has SIMD instructions.
5
*/
6
 
7
typedef int __attribute__((mode(SI))) __attribute__((vector_size (16))) vecint;
8
typedef int __attribute__((mode(SI))) siint;
9
 
10
vecint i = { 150, 100, 150, 200 };
11
vecint j = { 10, 13, 20, 30 };
12
vecint k;
13
 
14
union {
15
  vecint v;
16
  siint i[4];
17
} res;
18
 
19
/* This should go away once we can use == and != on vector types.  */
20
void
21
verify (siint a1, siint a2, siint a3, siint a4,
22
        siint b1, siint b2, siint b3, siint b4)
23
{
24
  if (a1 != b1
25
      || a2 != b2
26
      || a3 != b3
27
      || a4 != b4)
28
    abort ();
29
}
30
 
31
int
32
main ()
33
{
34
  k = i + j;
35
  res.v = k;
36
 
37
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 160, 113, 170, 230);
38
 
39
  k = i * j;
40
  res.v = k;
41
 
42
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 1500, 1300, 3000, 6000);
43
 
44
  k = i / j;
45
  res.v = k;
46
 
47
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 15, 7, 7, 6);
48
 
49
  k = i & j;
50
  res.v = k;
51
 
52
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 2, 4, 20, 8);
53
 
54
  k = i | j;
55
  res.v = k;
56
 
57
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 158, 109, 150, 222);
58
 
59
  k = i ^ j;
60
  res.v = k;
61
 
62
  verify (res.i[0], res.i[1], res.i[2], res.i[3], 156, 105, 130, 214);
63
 
64
  k = -i;
65
  res.v = k;
66
  verify (res.i[0], res.i[1], res.i[2], res.i[3],
67
          -150, -100, -150, -200);
68
 
69
  k = ~i;
70
  res.v = k;
71
  verify (res.i[0], res.i[1], res.i[2], res.i[3], -151, -101, -151, -201);
72
 
73
  exit (0);
74
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.