OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [20020206-1.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* This code is from the beginning of combine_reloads in reload.c in
2
   GCC 3.1-20020117, with simplifications.  It compiled incorrectly
3
   for -O2 -fprefetch-loop-arrays for ix86 targets.  */
4
 
5
/* { dg-do run } */
6
/* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
7
/* { dg-options "-O2 -fprefetch-loop-arrays -mtune=pentium3 -w" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
8
 
9
 
10
struct reload
11
{
12
  int first_member;
13
  int out;
14
  int final_member;
15
};
16
 
17
int n_reloads;
18
struct reload rld[10];
19
 
20
static int
21
combine_reloads ()
22
{
23
  int i;
24
  int output_reload = -1;
25
  int secondary_out = -1;
26
 
27
  for (i = 0; i < n_reloads; i++)
28
    if (rld[i].out != 0)
29
      {
30
        if (output_reload >= 0)
31
          return output_reload;
32
        output_reload = i;
33
      }
34
  return output_reload;
35
}
36
 
37
int
38
main ()
39
{
40
  n_reloads = 4;
41
  rld[2].out = 2;
42
  if (combine_reloads () != 2)
43
    abort ();
44
  exit (0);
45
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.