URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
689 |
jeremybenn |
/* { dg-do compile } */
|
| 2 |
|
|
/* { dg-options "-Wc++-compat" } */
|
| 3 |
|
|
|
| 4 |
|
|
int and; /* { dg-warning "operator" } */
|
| 5 |
|
|
int and_eq; /* { dg-warning "operator" } */
|
| 6 |
|
|
int bitand; /* { dg-warning "operator" } */
|
| 7 |
|
|
int bitor; /* { dg-warning "operator" } */
|
| 8 |
|
|
int compl; /* { dg-warning "operator" } */
|
| 9 |
|
|
int not; /* { dg-warning "operator" } */
|
| 10 |
|
|
int not_eq; /* { dg-warning "operator" } */
|
| 11 |
|
|
int or; /* { dg-warning "operator" } */
|
| 12 |
|
|
int or_eq; /* { dg-warning "operator" } */
|
| 13 |
|
|
int xor; /* { dg-warning "operator" } */
|
| 14 |
|
|
int xor_eq; /* { dg-warning "operator" } */
|
| 15 |
|
|
|
| 16 |
|
|
#define M1 and /* { dg-warning "operator" } */
|
| 17 |
|
|
#define M2 and_eq /* { dg-warning "operator" } */
|
| 18 |
|
|
#define M3 bitand /* { dg-warning "operator" } */
|
| 19 |
|
|
#define M4 bitor /* { dg-warning "operator" } */
|
| 20 |
|
|
#define M5 compl /* { dg-warning "operator" } */
|
| 21 |
|
|
#define M6 not /* { dg-warning "operator" } */
|
| 22 |
|
|
#define M7 not_eq /* { dg-warning "operator" } */
|
| 23 |
|
|
#define M8 or /* { dg-warning "operator" } */
|
| 24 |
|
|
#define M9 or_eq /* { dg-warning "operator" } */
|
| 25 |
|
|
#define M10 xor /* { dg-warning "operator" } */
|
| 26 |
|
|
#define M11 xor_eq /* { dg-warning "operator" } */
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.