OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [asm-b.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do run  { target powerpc*-*-* i?86-*-* x86_64-*-* } } */
2
/* { dg-options "-O1" } */
3
/* Test to make sure that inline-asm causes the tree optimizers to get the
4
   V_MAY_DEFs and clobber memory.  */
5
/* Test from Jakub Jelinek, modified by Andrew Pinski to work on all powerpc targets.  */
6
extern void abort (void);
7
 
8
unsigned short v = 0x0300;
9
 
10
void
11
foo (unsigned short *p)
12
{
13
  *p = v;
14
}
15
 
16
int
17
bar (void)
18
{
19
  unsigned short x;
20
  volatile unsigned short *z;
21
  foo (&x);
22
  const unsigned int y = x;
23
  z = &x;
24
#if defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (_POWER) || defined (__ppc64__) || defined (__ppc)
25
  __asm __volatile ("sthbrx %1,0,%2" : "=m" (*z) : "r" (y), "r" (z));
26
#elif defined __i386__ || defined __x86_64__
27
  __asm __volatile ("movb %b1,1(%2)\n\tmovb %h1,(%2)"
28
                    : "=m" (*z) : "Q" (y), "R" (z));
29
#endif
30
  return (x & 1) == 0;
31
}
32
 
33
int
34
main (void)
35
{
36
  if (bar ())
37
    abort ();
38
  return 0;
39
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.