OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [cpp/] [if-sc.c] - Blame information for rev 689

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* Copyright (C) 2000 Free Software Foundation, Inc.  */
2
 
3
/* { dg-do preprocess } */
4
 
5
/* Test that all operators correctly short circuit.  */
6
 
7
#if (2 || 3 / 0) != 1
8
#error          /* { dg-bogus "error" "|| short circuit" } */
9
#endif
10
 
11
#if 0 && 3 / 0
12
#error          /* { dg-bogus "error" "&& short circuit" } */
13
#endif
14
 
15
#if 1 ? 0 : 3 / 0
16
#error          /* { dg-bogus "error" "? : right short circuit" } */
17
#endif
18
 
19
#if 0 ? 3 / 0 : 2
20
#else
21
#error          /* { dg-bogus "error" "? : left short circuit" } */
22
#endif
23
 
24
#if -1 ? 0 && 3 / 0 : 3 / 0 + 5 == 5
25
#error          /* { dg-bogus "error" "nested short circuiting" } */
26
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.