OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [pr33619.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* PR tree-optimization/33619 */
2
/* { dg-do run } */
3
/* { dg-options "-O2" } */
4
 
5
#ifdef __powerpc__
6
# define REG1 __asm__ ("3")
7
# define REG2 __asm__ ("4")
8
#elif defined __x86_64__
9
# define REG1 __asm__ ("rdi")
10
# define REG2 __asm__ ("rsi")
11
#else
12
# define REG1
13
# define REG2
14
#endif
15
 
16
static inline void
17
bar (unsigned long x, int y)
18
{
19
  register unsigned long p1 REG1 = x;
20
  register unsigned long p2 REG2 = y;
21
  __asm__ volatile ("" : "=r" (p1), "=r" (p2) : "0" (p1), "1" (p2) : "memory");
22
  if (p1 != 0xdeadUL || p2 != 0xbefUL)
23
    __builtin_abort ();
24
}
25
 
26
__attribute__((const, noinline)) int
27
baz (int x)
28
{
29
  return x;
30
}
31
 
32
__attribute__((noinline)) void
33
foo (unsigned long *x, int y)
34
{
35
  unsigned long a = *x;
36
  bar (a, baz (y));
37
}
38
 
39
int
40
main (void)
41
{
42
  unsigned long a = 0xdeadUL;
43
  foo (&a, 0xbefUL);
44
  return 0;
45
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.