OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [pr41295.c] - Blame information for rev 695

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O1 -g" } */
3
 
4
enum reg_class
5
{
6
  BASE_REGS,
7
  GENERAL_REGS,
8
  LIM_REG_CLASSES
9
};
10
 
11
static __inline__ unsigned char
12
hard_reg_set_subset_p (const unsigned long x[4], const unsigned long y[4])
13
{
14
  return ((x[0] & ~y[0]) == 0
15
          && (x[1] & ~y[1]) == 0
16
          && (x[2] & ~y[2]) == 0
17
          && (x[3] & ~y[3]) == 0);
18
}
19
 
20
static __inline__ unsigned char
21
hard_reg_set_equal_p (const unsigned long x[4], const unsigned long y[4])
22
{
23
  return x[0] == y[0]
24
         && x[1] == y[1]
25
         && x[2] == y[2]
26
         && x[3] == y[3];
27
}
28
 
29
extern unsigned long reg_class_contents[(int) LIM_REG_CLASSES][4];
30
extern int ira_important_classes_num;
31
extern enum reg_class ira_important_classes[(int) LIM_REG_CLASSES];
32
extern enum reg_class ira_reg_class_intersect[(int) LIM_REG_CLASSES][(int)
33
                                                                     LIM_REG_CLASSES];
34
extern unsigned char ira_reg_classes_intersect_p[(int) LIM_REG_CLASSES][(int)
35
                                                                        LIM_REG_CLASSES];
36
extern enum reg_class ira_reg_class_super_classes[(int) LIM_REG_CLASSES][(int)
37
                                                                         LIM_REG_CLASSES];
38
static unsigned long temp_hard_regset[4];
39
 
40
static void
41
setup_reg_class_relations (void)
42
{
43
  int i, cl1, cl2, cl3;
44
  unsigned long temp_set2[4];
45
  for (cl1 = 0; cl1 < (int) LIM_REG_CLASSES; cl1++)
46
    {
47
      ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES;
48
      for (cl2 = 0; cl2 < (int) LIM_REG_CLASSES; cl2++)
49
        {
50
          ira_reg_classes_intersect_p[cl1][cl2] = 0;
51
          {
52
            unsigned long *scan_tp_ = (temp_set2), *scan_fp_ =
53
              (reg_class_contents[cl2]);
54
            scan_tp_[1] = scan_fp_[1];
55
            scan_tp_[2] = scan_fp_[2];
56
            scan_tp_[3] = scan_fp_[3];
57
          }
58
          for (i = 0; i < ira_important_classes_num; i++)
59
            {
60
              cl3 = ira_important_classes[i];
61
              {
62
                unsigned long *scan_tp_ = (temp_hard_regset), *scan_fp_ =
63
                  (reg_class_contents[cl3]);
64
                scan_tp_[0] = scan_fp_[0];
65
                scan_tp_[1] = scan_fp_[1];
66
                scan_tp_[3] = scan_fp_[3];
67
              }
68
              if (!hard_reg_set_subset_p (temp_hard_regset, temp_set2)
69
                  || (hard_reg_set_equal_p (temp_hard_regset, temp_set2)
70
                      && hard_reg_set_subset_p (reg_class_contents[cl3],
71
                                                reg_class_contents[(int)
72
                                                                   ira_reg_class_intersect
73
                                                                   [cl1]
74
                                                                   [cl2]])))
75
                ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
76
            }
77
        }
78
    }
79
}
80
 
81
static void
82
find_reg_class_closure (void)
83
{
84
  setup_reg_class_relations ();
85
}
86
 
87
void
88
ira_init (void)
89
{
90
  find_reg_class_closure ();
91
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.