OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [pr42715.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do compile { target fpic } } */
2
/* { dg-options "-fPIC -g -O2 -w" } */
3
/* var-tracking failed to clobber the reg holding v at the asm insn,
4
   so v ended up bound to an intermediate PIC expression.  */
5
 
6
struct A { unsigned a1; char a2[15]; };
7
struct B { long b1; unsigned char b2; long b3; };
8
struct C { void *c1; unsigned c2; unsigned c3; };
9
 
10
static struct A v1;
11
struct A *const v2 = &v1;
12
 
13
static inline
14
int foo (void)
15
{
16
  int *v;
17
  __asm__ __volatile__ ("" : "=r" (v));
18
  return v[1];
19
}
20
 
21
static void
22
bar (struct C *x)
23
{
24
  if (x->c2 == x->c3 && x->c1)
25
    f1 (foo (), x->c1, x->c3 * sizeof (x->c1[0]));
26
}
27
 
28
void
29
baz (struct B *y)
30
{
31
  int i;
32
  const char *j;
33
  char *k;
34
  char x[64];
35
  for (i = 0; i < sizeof (struct B); i++, y)
36
    {
37
      switch (y->b2)
38
        {
39
        case 0x20:
40
          if (__builtin_strchr (j, '='))
41
            continue;
42
        }
43
      switch (y->b2)
44
        {
45
        case 0x80:
46
          bar (&x);
47
          f2 (y->b3);
48
        case 0x2e:
49
        case 0x4e:
50
          break;
51
        default:
52
          if (v2->a1)
53
            f2 (y->b2);
54
        }
55
      k[0] = '\0';
56
      if (v2->a1)
57
        f2 (y->b1);
58
    }
59
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.