OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [sms-11.c] - Blame information for rev 706

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O2 -fmodulo-sched -fmodulo-sched-allow-regmoves -fdump-rtl-sms" } */
3
 
4
extern void abort (void);
5
 
6
float out[4][4] = { 6, 6, 7, 5, 6, 7, 5, 5, 6, 4, 4, 4, 6, 2, 3, 4 };
7
 
8
void
9
invert (void)
10
{
11
  int i, j, k = 0, swap;
12
  float tmp[4][4] = { 5, 6, 7, 5, 6, 7, 5, 5, 4, 4, 4, 4, 3, 2, 3, 4 };
13
 
14
  for (i = 0; i < 4; i++)
15
    {
16
      for (j = i + 1; j < 4; j++)
17
        if (tmp[j][i] > tmp[i][i])
18
          swap = j;
19
 
20
      if (swap != i)
21
        tmp[i][k] = tmp[swap][k];
22
    }
23
 
24
  for (i = 0; i < 4; i++)
25
    for (j = 0; j < 4; j++)
26
      if (tmp[i][j] != out[i][j])
27
        abort ();
28
}
29
 
30
int
31
main ()
32
{
33
  invert ();
34
  return 0;
35
}
36
 
37
/* { dg-final { cleanup-rtl-dump "sms" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.