OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [torture/] [mips-hilo-2.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* Due to a reload inheritance bug, the asm statement in f() would be passed
2
   the low part of u.ll on little-endian 32-bit targets.  */
3
/* { dg-do run { target mips*-*-* } } */
4
 
5
extern void abort (void);
6
extern void exit (int);
7
 
8
unsigned int g;
9
 
10
unsigned __attribute__ ((nomips16)) long long f (unsigned int x)
11
{
12
  union { unsigned long long ll; unsigned int parts[2]; } u;
13
 
14
  u.ll = ((unsigned long long) x * x);
15
  asm ("mflo\t%0" : "=r" (g) : "l" (u.parts[1]));
16
  return u.ll;
17
}
18
 
19
int __attribute__ ((nomips16)) main ()
20
{
21
  union { unsigned long long ll; unsigned int parts[2]; } u;
22
 
23
  u.ll = f (0x12345678);
24
  if (g != u.parts[1])
25
    abort ();
26
  exit (0);
27
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.