OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [tree-ssa/] [gen-vect-32.c] - Blame information for rev 689

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do run { target vect_cmdline_needed } } */
2
/* { dg-options "-O2 -ftree-vectorize -ftree-vectorizer-verbose=4 -fdump-tree-vect-stats" } */
3
/* { dg-options "-O2 -ftree-vectorize -ftree-vectorizer-verbose=4 -fdump-tree-vect-stats -mno-sse" { target { i?86-*-* x86_64-*-* } } } */
4
 
5
#include <stdlib.h>
6
 
7
#define N 16
8
 
9
int main ()
10
{
11
  struct {
12
    char ca[N];
13
  } s;
14
  int i;
15
 
16
  for (i = 0; i < N; i++)
17
    {
18
      s.ca[i] = 5;
19
    }
20
 
21
  /* check results:  */
22
  for (i = 0; i < N; i++)
23
    {
24
      if (s.ca[i] != 5)
25
        abort ();
26
    }
27
 
28
  return 0;
29
}
30
 
31
 
32
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
33
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
34
/* { dg-final { cleanup-tree-dump "vect" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.