OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [pr37482.c] - Blame information for rev 689

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-do compile } */
2
/* { dg-require-effective-target vect_int } */
3
 
4
void SexiALI_Convert(void *vdest, void *vsrc, unsigned int frames)
5
{
6
 unsigned int x;
7
 short *src = vsrc;
8
 unsigned char *dest = vdest;
9
 for(x=0;x<256;x++)
10
 {
11
  int tmp;
12
  tmp = *src;
13
  src++;
14
  tmp += *src;
15
  src++;
16
  *dest++ = tmp;
17
  *dest++ = tmp;
18
 }
19
}
20
/* { dg-final { cleanup-tree-dump "vect" } } */
21
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.